|Publication number||US7243339 B2|
|Application number||US 09/898,351|
|Publication date||Jul 10, 2007|
|Filing date||Jul 3, 2001|
|Priority date||Jul 3, 2001|
|Also published as||US20030009749|
|Publication number||09898351, 898351, US 7243339 B2, US 7243339B2, US-B2-7243339, US7243339 B2, US7243339B2|
|Inventors||Pratap Subrahmanyam, Nathaniel McIntosh|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (2), Classifications (8), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention generally relates to a system and method for analyzing a program and, more particularly, for decreasing the program analysis operation overhead.
2. Description of Related Art
As is known in the computer and software arts, when a software program is developed, there is generally a need to speed up the execution of the software program. One tool to assist a programmer in speeding up a software program are program analysis tools. Program analysis tools are used for the purpose of analyzing software programs in search of specific information, such as, for instance, analysis tools can be used to compute the number of times a branch is taken, versus executed, during the lifetime of the software program.
Programming analysis tools can also insert probes into a software program before a particular instruction that needs to be probed. This probe code will increment decrement a counter that is located in memory, i.e., such is a global data structure. Finally, when a software program is ready to end, the entire global data structure for the counters can be written to an output file in a human readable form. This allows the programmers to analyze the application program to determine instances and scenarios in which the application program may be modified to increase its efficiency.
However, there is a problem associated with these counters. Because the counters may be updated at anytime, the counters are loaded into memory as global data structures. These global data structures cause the memory footprint of the program analysis system to be dramatically increased, even if many of these counters are never accessed because the instructions being probed are never executed.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
The present invention provides a system and method for providing program analysis with data caching. Briefly described, in architecture, the system can be implemented as follows. The present invention for program analysis with data caching includes a counter for tracking each time one of a plurality of blocks of code in the computer program is executed. A counter cache stores the plurality of counters of the plurality of blocks of code that are most recently executed. A storage area stores a plurality of counters of the plurality of blocks of code that are not most recently executed code.
The present invention can also be viewed as providing a method for providing program analysis with data caching. In this regard, the method can be broadly summarized by the following steps executing said computer program; (1) using a counter for tracking each time one of said plurality of blocks of code is executed; (2) maintaining a counter cache for storing said plurality of counters of said plurality of blocks of code that are most recently executed; and (3) maintaining a storage area for storing a plurality of counters of said plurality of blocks of code that are not most recently executed.
The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present invention, and together with the description, serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail to the description of the invention as illustrated in the drawings. Although the invention will be described in connection with these drawings, there is no intent to limit it to the embodiment or embodiments disclosed therein. On the contrary, the intent is to include all alternatives, modifications, and equivalents included within the spirit and scope of the invention as defined by the appended claims.
The program analysis with paging system of the invention can be implemented in software (e.g., firmware), hardware, or a combination thereof. In the currently contemplated best mode, the program analysis with paging system is implemented in software, as an executable program, and is executed by a special or general purpose digital computer, such as a personal computer (PC; IBM-compatible, Apple-compatible, or otherwise), workstation, minicomputer, or mainframe computer. An example of a general-purpose computer that can implement the program analysis with paging system of the present invention is shown in
Generally, in terms of hardware architecture, as shown in
The processor 11 is a hardware device for executing software that can be stored in memory 12. The processor 11 can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer 5, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing software instructions. Examples of suitable commercially available microprocessors are as follows: a PA-RISC series microprocessor from Hewlett-Packard Company, an 80x86 or Pentium series microprocessor from Intel Corporation, a PowerPC microprocessor from IBM, a Sparc microprocessor from Sun Microsystems, Inc, or a 68xxx series microprocessor from Motorola Corporation.
The memory 12 can include any one or combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and nonvolatile memory elements (e.g., ROM, hard drive, tape, CDROM, etc.). Moreover, the memory 12 may incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the memory 12 can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processor 11.
The software in memory 12 may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions. In the example of
The program analysis with paging system 50 is a source program, executable program (object code), script, or any other entity comprising a set of instructions to be performed. When a source program, then the program needs to be translated via a compiler, assembler, interpreter, or the like, which may or may not be included within the memory 12, so as to operate properly in connection with the O/S 21. Furthermore, the program analysis with paging system 50 can be written as (a) an object oriented programming language, which has classes of data and methods, or (b) a procedure programming language, which has routines, subroutines, and/or functions, for example but not limited to, C, C++, Pascal, Basic, Fortran, Cobol, Perl, Java, and Ada.
The I/O devices may include input devices, for example but not limited to, a keyboard 15, mouse 14, scanner, microphone, etc. Furthermore, the I/O devices may also include output devices, for example but not limited to, a printer, display 16, etc. Finally, the I/O devices may further include devices that communicate both inputs and outputs, for instance but not limited to, a modulator/demodulator 17(modem; for accessing another device, system, or network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, etc.
If the computer 5 is a PC, workstation, or the like, the software in the memory 12 may further include a basic input output system (BIOS) (omitted for simplicity). The BIOS is a set of essential software routines that initialize and test hardware at startup, start the O/S 21, and support the transfer of data among the hardware devices. The BIOS is stored in ROM so that the BIOS can be executed when the computer 5 is activated.
When the computer 5 is in operation, the processor 11 is configured to execute software stored within the memory 12, to communicate data to and from the memory 2, and to generally control operations of the computer 5 pursuant to the software. The program analysis with paging system 50 and the O/S 21, in whole or in part, but typically the latter, are read by the processor 11, perhaps buffered within the processor 11, and then executed.
When the program analysis with paging system 50 is implemented in software, as is shown in
The program analysis with paging system 50 can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable medium” can be any means that can store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a nonexhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM) (electronic), a read-only memory (ROM) (electronic), an erasable programmable read-only memory (EPROM, EEPROM, or Flash memory) (electronic), an optical fiber (optical), and a portable compact disc read-only memory (CDROM) (optical). Note that the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
In an alternative embodiment, where the program analysis with paging system 50 is implemented in hardware, the program analysis with paging system 50 can implemented with any or a combination of the following technologies, which are each well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.
Next, the modified source code is executed at step 32. In the prior art methodology, memory for holding block execution counts is allocated monolithically at runtime. Thus at the start of program execution, the modified program allocates memory to store counter values for all the blocks in the program, even those blocks that are never subsequently executed. This allocation scheme is wasteful, and results in poor data locality when counter values are accessed at runtime. Lastly, the program analysis writes the block execution counts to a final data file at step 33. This allows the programmer to analyze which blocks of code were the most executed and if some blocks of code were not even executed during the running of program being analyzed.
As noted above, the adding block counter method causes increased developer time to insert the counter instructions into the program as well as time required to recompile or reassemble and link the program. The modified program will almost always runs much slower than the original program as a result of the additional instructions and input/output processing required for each block. There is also a resource requirement of a large amount of disk storage to hold the code block execution documentation.
The program analysis with data caching system 50 acquires the address of the next instruction in the original source code 22 to be executed from the program counter 24. The program analysis with data caching system 50 then performs the translation of the original source 22 and inserts this translated program code into the code cache 27. A new program counter (NPC) 26, which points to the beginning of the translated code, is returned for later execution during program analysis. The block counter cache 25 is utilized to store the block execution counter for each block of the translated code. The data storage 23 is utilized to store the stale code block frequency counter data that is not kept in the block counter cache 25. The method of the present invention performed by the program analysis with data caching system 50 is herein defined in further detail with regard to
At step 53, the program analysis with data caching system 50 checks to see if the new program counter is found. If it is determined at step 53 that the new program counter was found, the program analysis with data caching system 50 proceeds to step 57.
If it is determined at step 53, that the new program counter is not found, the program analysis with data caching system 50 then determines whether the code cache is full at step 54. If it is determined that the code cache is not full, the program analysis with data caching system 50 then translates the code and puts the translated code in the code cache 27, at step 56. This translation of the code and placing of the translated code into the code cache is herein defined in further detail with regard to
However, if it is determined at step 54 that the code cache is not full, the program analysis with data caching system 50 then translates the code and puts the translated code into the code cache 27, at step 56, as herein defined above. After translating the original source code 22 and placing the translated code into the code cache 27, the program analysis with data caching system 50 then proceeds to step 57.
At step 57 the program analysis with data caching system 50 checks whether backpatching the “B” pointer is necessary at step 57. Backpatching is the process of modifying the destination of the branch address to a different location so that a future lookup of the translation for the destination is avoided. Determination of backpatching is herein defined in further detail with regard to
Next at step 61, the program analysis with data caching process 50 then executes the code at the new program counter 26 in the code cache 27 until the translated code is done, or until reaching a branch that is not backpatched. Furthermore, at step 61, the code block frequency counter for each block counter in the block counter cache is incremented each time a block is executed.
Next, at step 62, the program analysis with data caching system 50 then determines whether the translated code in the code cache 27 has finished execution. If it is determined that the translated code in the code cache 27 has not finished execution, the program analysis with data caching process system 50 then receives the set 63 to pop from the stack the branch target address for the program counter. This branch target address is then loaded into the new program counter. The program analysis with data caching system 50 then proceeds to repeat steps 52 through 62. However, if it is determined at step 62 that the translated code and code cache 27 is done, the program analysis with data caching process 50 saves all the block frequency counters to the block counter cache and then terminates at step 69.
Next, the program analysis with data caching system 50 registers the translated code in the code cache's lookup table using the block number at step 74. The program analysis with data caching system 50 determines whether the block number for the translated code registered in the code cache 27 has been previously defined. If the block number for the translated code in the code cache 27 has been previously defined, the program analysis with data caching system 50 then proceeds to step 81 and reads in the stored code block frequency counter value from the data storage memory 23 into the code block counter cache 25, at step 81. The program analysis with data caching system 50 then proceeds to step 89 and returns to step 56 in
However, if it is determined at step 75 that the block number of the translated code and the code cache 27 has not been previously defined, the program analysis with data caching system 50 then provides notification of the first execution of that block of code at step 76. Next, at step 77, the program analysis with data caching system 50 then adds the code block frequency counter into the block counter cache 25. The process to add the block counter frequency counter to the block counter cache 25 is herein defined in further detail with regard to
Then the program analysis with data caching system 50 lets the new program counter point to the translated code in the code cache 27, at step 78. The program analysis with data caching system 50 then returns to continue processing at step 56 in
In an alternative embodiment, the counter caching methodology described in
The embodiment or embodiments discussed were chosen and described to provide the best illustration of the principles of the invention and its practical application to enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly and legally entitled.
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|U.S. Classification||717/130, 714/E11.2|
|International Classification||G06F9/44, G06F11/34|
|Cooperative Classification||G06F2201/88, G06F2201/885, G06F11/3466|
|Feb 20, 2002||AS||Assignment|
Owner name: HEWLETT-PACKARD COMPANY, COLORADO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUBRAHMANYAM, PRATAP;MCINTOSH, NATHANIEL;REEL/FRAME:012650/0699;SIGNING DATES FROM 20010627 TO 20010702
|Sep 30, 2003||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:014061/0492
Effective date: 20030926
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY L.P.,TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:014061/0492
Effective date: 20030926
|Nov 30, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Jan 1, 2013||CC||Certificate of correction|
|Feb 20, 2015||REMI||Maintenance fee reminder mailed|
|Jul 10, 2015||LAPS||Lapse for failure to pay maintenance fees|
|Sep 1, 2015||FP||Expired due to failure to pay maintenance fee|
Effective date: 20150710