|Publication number||US7248592 B1|
|Application number||US 10/219,028|
|Publication date||Jul 24, 2007|
|Filing date||Aug 14, 2002|
|Priority date||Aug 14, 2002|
|Publication number||10219028, 219028, US 7248592 B1, US 7248592B1, US-B1-7248592, US7248592 B1, US7248592B1|
|Inventors||Gregory S. Snider|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (1), Referenced by (5), Classifications (12), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention generally relates to data fabrics, and more particularly to a data fabric and interface that supports partitioning of the data fabric.
A data fabric is a communication network designed to interconnect large numbers of computation nodes such that the nodes can exchange data with high bandwidth and low latency. The fabric generally allows any-to-any connectivity between nodes. Data fabrics have evolved from simple shared-bus implementations, with serialized data transfers, to switched implementations, which provide highly-concurrent, high bandwidth communication between may processing nodes.
Two example applications of data fabrics include a clustered supercomputer arrangement and an Internet data center. A clustered supercomputer arrangement includes hundreds or thousands of processors and storage elements that are interconnected via the data fabric. The storage elements combine to form a single, global address space. Similarly, an Internet data center includes hundreds or thousands of processing nodes, storage elements, load distribution nodes, firewalls and other components interconnected by a data fabric. By configuring the data fabric the components can be divided (or “partitioned”) into isolated domains (or “partitions”), with each partition serving a different customer, for example.
Fabrics are currently partitioned through software-controlled configuration of switches within the fabric. The configuration software tends to be large and complex, which may lead to an increased likelihood of program bugs. Furthermore, the switch topology must be known to the configuration software in order for the configuration software to function correctly. If the topology is changed, which is likely in a typical data center as new switches and nodes are added over time, the configuration software must be kept strictly in sync with the hardware topology. Otherwise, the chances of a security lapse are greatly increased.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
In various embodiments, the invention provides a circuit arrangement and method for interfacing a node and a data fabric. In a computing arrangement that includes a plurality of nodes intercoupled by the data fabric, each node is assigned to one of a plurality of partitions. A node-interface circuit is configured to interface with the source node, and a translation circuit translates data between a first format compatible with the nodes and a second format compatible with the data fabric. An access control circuit either enables or disables transmission of data from the source node based on whether the source and destination nodes are in the same partition.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.
Various aspects and advantages of the invention will become apparent upon review of the following detailed description and upon reference to the drawings in which:
In various embodiments of the invention, a line card provides an interface between a node and a data fabric. Each node has a dedicated line card, which is configurable to control with which nodes the connected node can communicate via the data fabric. The various embodiments provide hardware-level control over communication via a partitioned data fabric without requiring complex software that accounts for the data fabric topology.
The desired attributes of a typical data fabric are high bandwidth and low latency, independence from higher level protocols (e.g., IP, RDMA, SCI, etc.), and partitioning into independent non-interacting domains. A high degree of assurance that communication between nodes in different domains via the data fabric is not achievable is also desirable. For example, if the computing arrangement is partitioned such that nodes 102 a, 102 e, and 102 f are in a first partition, nodes 102 b and 102 g are in a second partition, and nodes 102 c and 102 d are in a third partition, then nodes in the first partition are not allowed to communicate with nodes in either the second or third partition via the data fabric. The present invention provides hardware level control over the partition security and software level flexibility in defining the partitions.
The arbiter 154 receives cell transmission requests from each of the line cards and grants each card permission to transmit particular cells to the switch network 152. Depending on the nature of the switch network, the arbitration technique employed by the arbiter can range from simple to complex. For example, the arbiter may implement either the iSLIP or Full Frames algorithms.
The data fabric is implemented at the data link layer. In one embodiment of the invention, the partition control is implemented between the data link layer (layer 2) and the network layer (layer 3) in the OSI stack. This isolates the partition control from the particular requirements of protocols at the higher layers (3 and above), which means that the same partition control mechanism can be used for all the layers above the data link layer.
Most of the components of example line card 156 are illustrative of those components found in conventional line cards. For example, a physical layer component 202 is coupled to the associated node and provides the signal-level interface between the node and the line card. The framing component 204 extracts the structure of the bit stream in order to establish synchronization with the sender/receiver.
Outgoing packets are provided to the packet processing component 206, which uses lookup tables 208 to translate layer 3 addresses, for example, IP addresses, to layer 2 addresses, for example, another node coupled to the data fabric. The packets are then translated into cells for the data fabric by the packet-to-cell translation component 210. The access control component 212 determines whether the source node is in the same partition as the destination node. If so, the cells are provided to the buffer scheduling and management component 214, which first obtains authorization from the arbiter before transmitting the cells over the data fabric. If a transmission attempts to send data to a node in another partition, access control 212 signals the monitor and alarm component 215. The monitor and alarm component alerts a management processor (not shown) of attempted transmissions that are in violation of the partition definitions. The buffer and state memory component 216 is used by the buffer management for temporary storage of cells and tracking transmissions states of cells.
Incoming cells are received by buffer management and scheduling component 218, which uses memory 220 to temporarily store the cells and maintain state information. The cells are provided by cell-to-packet translation component 222, which converts the cells to packet formation and provides the packet to framing component 204.
In one embodiment, the access control component 212 is configurable via the access control interface 230, which is coupled to a management processor. The access control interface provides the interface between the configurable bits of the access control component and the management processor. For example, the management processor is coupled to the access control interfaces of the all the line cards of all the nodes by a secure local area network. The access control interface includes the logic needed to communicate with the management processor over the network and configure the access control component. In an example embodiment, the access control, monitor and alarm, and access control interface components are implemented with programmable logic, such an FPGA. Those skilled in the art will appreciate that other components of the line card may also be implemented in programmable logic, depending on implementation requirements. By implementing in the line card the control over which nodes can communicate over the data fabric, the partitioning is enforced by hardware, not software, thereby making the mechanism less susceptible to unauthorized access. Furthermore, with the access control implemented in the line cards, the fabric topology does not affect the security provided by the access control. That is, the data fabric can be extended or changed as long as management processor configures the line cards with the correct security policy governing communication between nodes.
In the example embodiment, each node connected to the data fabric is assigned a number. For example, in a data fabric with 1024 ports, each node is assigned a value of 0–1023. Thus, in transmitting data between nodes via the data fabric, 10 bits are needed to address the nodes. The destination address is input to demultiplexer 304, which activates a signal on one of 1024 output lines based on the input address. The output signals from the demultiplexer are input to respective AND gates 306, along with output signals from corresponding bits in the control register bank. Thus, when a node is addressed and the state of the configuration bit associated with the addressed node indicates that the addressed node is in the same partition as the source node, the output from the associated AND gate is logic level 1, which causes the output from OR gate 308 to enable transmission of the data.
The present invention is believed to be applicable to a variety of arrangements for interconnecting computing nodes and has been found to be particularly applicable and beneficial in a partitionable data fabric. Other aspects and embodiments of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and illustrated embodiments be considered as examples only, with a true scope and spirit of the invention being indicated by the following claims.
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|U.S. Classification||370/401, 370/400, 370/466|
|Cooperative Classification||H04L69/323, H04L69/08, H04L49/90, H04L49/253|
|European Classification||H04L49/25E, H04L49/90, H04L29/06E, H04L29/08A1|
|Dec 27, 2002||AS||Assignment|
Owner name: HEWLETT-PACKARD COMPANY, COLORADO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SNIDER, GREGORY S;REEL/FRAME:013627/0555
Effective date: 20020809
|Jun 18, 2003||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., COLORAD
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:013776/0928
Effective date: 20030131
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.,COLORADO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:013776/0928
Effective date: 20030131
|Nov 30, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Mar 6, 2015||REMI||Maintenance fee reminder mailed|
|Jul 24, 2015||LAPS||Lapse for failure to pay maintenance fees|
|Sep 15, 2015||FP||Expired due to failure to pay maintenance fee|
Effective date: 20150724