|Publication number||US7249329 B1|
|Application number||US 10/859,325|
|Publication date||Jul 24, 2007|
|Filing date||Jun 1, 2004|
|Priority date||Jun 1, 2004|
|Publication number||10859325, 859325, US 7249329 B1, US 7249329B1, US-B1-7249329, US7249329 B1, US7249329B1|
|Inventors||Gregg William Baeckler, Jinyong Yuan, David W. Mendel|
|Original Assignee||Altera Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (3), Referenced by (7), Classifications (8), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to technology mapping techniques for incomplete look-up tables, and more particularly, to techniques for determining functions in a circuit design can be implemented by incomplete lookup tables.
A lookup table is a memory circuit that stores binary bits of information. A lookup table can emulate a logic function that generates output values in response to receiving values of input signals. Each possible output of the logic function is stored in the lookup table at a memory address that matches corresponding values of the input signals.
A lookup table (LUT) can have any number of input terminals that receive input signals. A complete LUT has enough memory to store every (2N) binary value of its N input signals. For example, a complete 4 input LUT has enough memory to store 16 output bits that correspond to every binary value of the 4 input signals (24=16).
The term “incomplete LUT” is used to refer to a LUT that has less than 2N bits of memory to store output bits for every binary value of its N input signals. For example, a 5 input LUT can receive 25=32 possible binary values of its 5 input signals. A 5 input LUT is an incomplete LUT if it only has enough memory to store 16 different output bits.
Many reasonable configurations for incomplete LUTs have been made. For example, a 5 input incomplete LUT can be made from two 3 input LUTs and a multiplexer. The 3 input LUTs have two shared input signals. The fifth input signal controls the select terminal of the multiplexer. The multiplexer has two inputs that are coupled to the outputs of the LUTs.
A 7 input incomplete LUT can also be built from two 3 input LUTs and a multiplexer. The two 3 input LUTs have no shared input signals. The seventh input signal controls the select terminal of the multiplexer. The multiplexer has two inputs that are coupled to the outputs of the LUTs.
A different 7 input incomplete LUT can be built from a 5 LUT feeding a multiplexer. The LUT and sixth input signal feed the two data terminals of the multiplexer. The seventh input feeds the select terminal of the multiplexer.”
The number of functions that a LUT can implement equals 2M, where M is the number of storage bits in the LUT. However, not all of the functions that a complete LUT can implement are necessarily unique or useful. A complete 4 input LUT and the incomplete 5 input LUT described above can each implement 65536 functions. A complete 5 input LUT can implement about 4 billion functions.
The amount of area that is required to built a LUT on a silicon chip is proportional to the storage space in the LUT. An incomplete LUT uses far less silicon area than a complete LUT that has the same number of inputs, because incomplete LUTs have less storage space.
Technology mapping is a term that refers to the process of converting an arbitrary circuit design into an equivalent circuit that can be programmed onto a programmable integrated circuit such as field programmable gate array (FPGA). Most FPGAs use LUTs to implement logic functions. Technology mapping algorithms convert a circuit design into a network of available LUTs and other programmable circuit elements.
Traditional technology mapping algorithms operate on the assumption that all LUTs are complete in the sense described above. Such traditional algorithms assume, for example, that any 5 input function can be implemented in a 5 input LUT.
However, it may not be possible to implement a 5 input logic function in an incomplete 5 input LUT. An incomplete 5 input LUT may not have enough memory storage space to store all of the possible output values of a 5 input function.
It would be desirable to use incomplete LUTs in technology mapping tools, because incomplete LUTs can implement functions using less storage space than complete LUTs having the same number of inputs. Therefore, it would be desirable to provide technology mapping techniques that determine whether functions in a circuit design can be fully implemented using incomplete LUTs.
The present invention provides technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT). According to one embodiment of the present invention, the output of a function is compared directly to the output of an incomplete LUT using an exclusive OR (XOR) gate. The comparison is repeated for each binary value of the function's input signals. The outputs of each comparison are evaluated by an OR gate. The process can be repeated for each possible binary value of the bits stored in the incomplete LUT. For a LUT that is functionally asymmetric, the process is repeated for multiple rotations of the input signals with respect to the input terminals of the LUT.
According to another embodiment of the present invention, the user function is converted into a network of 2:1 multiplexers and complete LUTs. The network is then analyzed directly by a process to determine if a specific incomplete LUT can implement the function.
According to yet another embodiment of the present invention, a truth table is constructed for a function. The truth table variables are then tested one by one as candidates for each input position using two types of operations. The operations include co-factoring and dependency checking. Co-factoring is splitting the truth table into two halves corresponding to a given variable being high and low. Dependency checking is testing whether the value of a given variable effects the output of a truth table. This embodiment can also be performed using a binary decision diagram (BDD) instead of a truth table.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
According to a first embodiment of the present invention, a test procedure compares the outputs of an arbitrary function with the outputs of an incomplete lookup table (LUT) to determine if the LUT can implement the function. The incomplete LUT is tested for every binary value of the input signal and every binary value of the bits stored in the LUT's memory to determine if the LUT can implement the function.
System 120 is preferably a test process that is implemented in software to determine if LUT can implement function 108. For example, LUT 101 and function 108 can be modeled and tested in a binary decision diagram built in software.
Both LUT 101 and function 108 receive input signals A, B, and C and generate an output signal. The output signals of LUT 101 and function 108 are compared by XOR gate 110, which can also be implemented as a software function.
XOR gate 110 outputs a 0 (a logic low) when both outputs of LUT 101 and function 108 are the same. XOR gate 110 outputs a 1 (a logic high) when the outputs of LUT 101 and function 108 are different. The output of XOR gate 110 indicates whether there is a mismatch between the outputs of LUT 101 and function 108.
LUT 106 is a 2 input LUT that stores 4 possible output bits. The binary values of the bits stored in LUT 106 effect whether LUT 101 can implement function 108. Therefore, a test procedure of the present invention tests all binary values of the bits that can be stored in LUT 106 to determine whether LUT 101 can implement function 108.
LUT 101 can only implement function 108 if LUT 101 generates the same output values as function 108 for each binary value of the input signals A, B, and C. To determine whether LUT 101 can implement function 108, the output of LUT 101 is compared against the output of function 108 for every binary value of the input signals A, B, and C.
The output signals of the 8 XOR gates 110 are transmitted to the inputs of OR gate 150. The output signal of OR gate 150 indicates whether incomplete LUT 101 can implement function 108. If the output of OR gate 150 is 0, then there is no mismatch between the output of LUT 101A and the output of function 108 for any of the 8 binary values of the input signals A, B, and C. A zero output from OR gate 150 indicates that incomplete LUT 101 can implement function 108 for selected values of bit0, bit1, bit2, and bit3.
If the output of OR gate 150 is 1, then there is a mismatch between the output of LUT 101A and the output function 108 for at least one of the 8 binary values of the input signals A, B, and C. A one output from OR gate 150 indicates that incomplete LUT 101 cannot implement function 108 for the selected values of bit0, bit1, bit2, and bit3.
The test system shown and described with respect to
According to an embodiment of the present invention, the output of an incomplete LUT are compared to the output of a function for each binary value of the input signals, as shown for example in
Each round node in the BDD represents a storage bit in the incomplete LUT. The square end points of the BDD represent the possible values of the OR gate 150 output. End point 1 represents a 1 output at OR gate 150, and end point 0 represents a 0 output at OR gate 150. The arrows between the nodes represent the possible values for bits bit0-bit3.
Each complete path from the starting point (bit0) to the square node 0 represents binary values for bit0-bit3 that allow LUT 101 to implement function 8. For example, a path from bit0 to bit2 ends at end point 0. This path represents zero values for bit0 and bit2. Because the path ends at end point 0, which represents a 0 output from OR gate 150, LUT 101 can implement function 108 if the stored LUT values bit0 and bit2 are both zero. Any values for bit1 and bit3 will result in LUT 101 being able to implement function 108 as long as bit0 and bit2 are 0.
Another possible path from bit0 to bit1 to bit3 leads to end point 0. This path represents a 1 value for bit0 and 0 values for bit1 and bit3. As long as these values are stored in LUT 101 for bit0, bit1, and bit3, any value of bit2 will allow LUT 101 to implement function 108 according to the BDD of
If the BDD for a test system does not have a valid path to a zero end point output for the OR gate, and the incomplete LUT is a symmetric LUT, then the incomplete LUT cannot implement the function. However, an incomplete LUT that is asymmetrical may generate different sets of functions depending on how the input signals are coupled to its input terminals.
For example, LUT 101 is asymmetric, because one input signal is coupled to the select terminal of multiplexer 104, while the other two input signals are coupled to inputs of LUT 106. If a particular placement of input signals A, B and C on the input terminals of LUT 101 does not enable LUT 101 to implement function 108, the input signals are permutated with respect to the input terminals of LUT 101, and the above described test procedures are repeated.
In the event that OR gate 150 does not output a 0 value for any of the 16 unique binary values of bit0, bit1, bit2, and bit3, input signals A/B/C are permutated with respect to the input terminals of LUT 101. The above test procedures are then repeated. For example, input signals A and B can be swapped. Input signal A is now coupled to the select terminal of multiplexer 104, and input signals B and C are coupled to inputs of LUT 106.
After input signals A, B, and C have been permutated, a new BDD is constructed for the test system to determine if any values of bit0, bit1, bit2, and bit3 allow incomplete LUT 101 to implement function 108. A valid path through the BDD to a zero end point indicates that LUT 101 can implement function 108 for the corresponding binary value of bit0-bit3 and the second permutation of input signals A, B, and C.
If no valid path exists through the BDD to a zero end point, incomplete LUT 101 cannot implement function 108 for the second permutation of input signals A/B/C. The input signals are then permutated again with respect to the input terminals of LUT 101. In the third permutation, input signal B is coupled to the select input of multiplexer 104, and input signals A and C are coupled to the inputs of LUT 106.
After input signals A, B, and C have been permutated again, a new BDD is constructed for the test system to determine if any values of bit0, bit1, bit2, and bit3 allow incomplete LUT 101 to implement function 108. A valid path through the BDD to a zero end point indicates that LUT 101 can implement function 108 for the corresponding binary value of bit0-bit3 and the third permutation of input signals A, B, and C.
If no valid path exists through the BDD to a zero end point, incomplete LUT 101 cannot implement function 108 for the third permutation of input signals A/B/C. Six (23) permutations of the input signals are possible for LUT 101. Swapping the inputs of a symmetric LUT does not count as a unique permutation of the input signals.
Input signals in portions of an incomplete LUT that are symmetric do not need to be permutated. For example, if LUT 101 was an incomplete 4 input LUT in which the 1 input of multiplexer 104 was driven by an input signal D instead of B, 24 permutations of the 4 input signals are possible. However, only 12 of these permutations need to be tested, because inputs and A and B are now interchangeable.
XOR gate 220 compares the output of LUT 201 to the output of user function 210. Many functions that users program into programmable integrated circuits do not require all of the storage space that a LUT with the same number of inputs provides. An incomplete LUT such as LUT 201 can implement many user functions, while using substantially less memory storage space than complete LUTs.
User function 210 includes OR gates 211 and 212 and multiplexers 213 and 214. Function 210 receives 7 input signals A-G. According to an embodiment of the present invention, a user function with N input signals can be implemented in an incomplete LUT that has greater than N input terminals. For example,
Some of the input signals can be duplicated on more than one input of LUT 201. For example, input signals A and B can be coupled to inputs of LUTs 202 and 203. Duplicating a function's input signals on more than one input of an incomplete LUT can count as an additional rotation/placement of the input signals.
The test system of
The test system of
A BDD is constructed to represent the test system that includes XOR gates and the OR gate that tests each binary value of the function's input signals. All valid paths through the BDD to the zero end point represent the binary values for the dummy variables d0-d31 that will allow the incomplete LUT to implement the function.
If there is not valid path through the BDD to the zero end point, the input signals A-G are permutated with respect to the input terminals of LUT 201. For example, input signals E and F can be coupled to LUT 202, and input signals C and D can be coupled to LUT 203. The tests are then repeated for each binary value of input signals A-G using a new BDD that represents each binary value of the input signals according to the second input permutation.
The tests can be repeated for each possible permutation of the input signals with respect to the input terminals of LUT 201. Tests that provide a duplicate input signal (A-G) to more than one input terminal of LUT 201 are treated as separate rotations from the tests that do not use duplicates of the input signals.
At step 313, a BDD representing the XOR/OR comparison network from step 312 is constructed. Then, any valid paths from the starting node of the BDD that lead to the zero end point are identified. The zero end point represents a zero output of the OR gate. The valid paths through the BDD to the zero end point indicate the binary values that can be stored in the incomplete LUT to implement the function.
At decisional step 314, a determination is made whether a path exists through the BDD to the zero end point. If a path exists to the zero end point, a solution exists and the process is terminated. If a path does not exist to the zero end point, a determination is made at decisional step 315 as to whether the incomplete LUT is asymmetric. If the incomplete LUT is symmetric, a solution does not exist and the process terminates.
If the incomplete LUT is asymmetric, the input signals are permutated with respect to the input terminals of the incomplete LUT at step 316. The previous steps are then repeated. The steps of
The structure of software that implements the embodiment of
Modern circuits are typically implemented in a hardware description language (HDL). These languages usually have the “if-then-else” code structure. The if-then-else code structures can naturally be implemented in 2:1 multiplexers. An incomplete LUT can always be viewed as a network of 2:1 multiplexers fed by inputs and smaller complete LUTs. Programmers often rely on the if-then-else structure to characterize numerous types of functions in their circuit designs. The fact that programmers frequently use the if-then-else structure makes it very natural to match up portions of a user HDL design with incomplete LUTs.
The present invention includes other embodiments for determining whether an incomplete LUT can implement a function. One of these embodiments analyzes software code (e.g., in an HDL) that describes a circuit design that includes functions. A synthesis tool converts the software code for a function in the design into a network of multiplexers and smaller complete LUTs.
The present invention then determines whether the network of multiplexers and complete LUTs can be implemented by an incomplete LUT on the FPGA that has the same or a larger number of inputs. This technique is referred to as pattern matching on the input netlist. The netlist refers to the software code that describes a circuit design.
The following software Code A will be used as an example of this embodiment. Code A implements a function 400 in a circuit design.
A synthesis and technology mapping tool such as Quartus II can convert Code A into a network of multiplexers and smaller LUTs using well known techniques. The output of this conversion is network 410 shown in
The present invention can analyze network 410 to determine if incomplete LUT 101 shown in
For each gate in the network
If (is_a_2to1_mux (gate))
X = signal feeding MUX select
Y = signal feeding MUX data 0
Z = signal feeding MUX data 1
If there is a 2 input gate feeding Y
Q = input 1 on the source gate
R = input 2 on the source gate
If Q or R is the same as Z
LUT input B = Z
LUT input C = X
LUT input A = The Q or R that does not match Z
Software procedure B is merely an example that is provided for illustrative purposes and is not intended to limit the scope of the present invention. According to the present invention, numerous other procedures are possible for determining whether an incomplete LUT can implement a network of multiplexers and smaller complete LUTs. The pattern matching can be updated to work with any new LUT structure.
Procedure B is now described in further detail. For each gate in network 410, procedure B determines whether the gate is a 2:1 multiplexer using the first If condition. If the gate is a 2:1 multiplexer, procedure B assigns X to the signal feeding the multiplexer 402 select terminal, Y to the signal feeding the multiplexer 402 data 0 input, and Z to the signal feeding the multiplexer 402 data 1 input.
If there is a source gate with 2 inputs that feeds the Y input of multiplexer 402, Q is assigned to the first input of the source gate, and R is assigned to the second input of the source gate. If Q or R are the same signal as Z, then incomplete LUT 101 can implement function 400. In this case, input B of LUT 101 is assigned to input Z of multiplexer 402, input C of LUT 101 is assigned to input X of multiplexer 402, and input A of LUT 101 is assigned to the Q or the R input that does not match input Z. Thus, procedure B determines whether that an incomplete LUT 101 can implement a function, and the order in which the input signals of the function should be assigned to the inputs of the incomplete LUT.
Nesting of if-then-else blocks in user HDL programs is also very common. The nesting of if-then-else blocks leads to trees of multiplexers that also can be mapped into incomplete LUTs using the techniques of the present invention. The following Code C provides an example of the how the present invention can map a function described in a nested if-then statement into an incomplete LUT.
The present invention can easily convert Code C into two 2:1 multiplexers, where the first multiplexer is coupled to an input of the second multiplexer. Inputs A and B feed into the first multiplexer, and input C feeds into the second multiplexer. The select input of the first multiplexer is controlled by condition 1, and the select input of the second multiplexer is controlled by condition 2.
Any arrangement of if-then-else statements can be converted into a desirable multiplexer implementation. For example, moving the block under condition 2 in Code C down to the else half of the first If-Else block produces a symmetric 2 multiplexer result. Adding another If block at any point in the example adds a third multiplexer, but does not disturb the suitability of the code for an incomplete 5 input LUT.
An advantage of this embodiment of the present invention is that the procedures (such as procedure B) are extremely fast to execute. Procedure B, for example, constructs the appropriate ordering for the A, B, and C LUT inputs rather than needing to explore all binary values of the inputs as with the
A disadvantage of this embodiment is the fact that the procedures (such as procedure B) that determine whether an incomplete LUT can implement the function have to be customized for every incomplete LUT. Also, there are many functions that can be implemented in an incomplete LUT, but that are not expressed by a particular conversion procedure such as procedure B.
For incomplete LUTs that have a large number of inputs, it becomes less feasible to implement some of the embodiments of the present invention, because the runtime burden increases exponentially with increasing inputs. However, the runtime of the
The present invention can also recognize common sub-circuits at the HDL level and replace the sub-circuits directly with technology mapped equivalents. For example, the software can recognize an 8:1 multiplexer function and replace it with two 5 input LUTs implementing 3:1 multiplexers followed by an incomplete 7 input LUT implementing the selection between the two 3:1 multiplexers and the other two data elements. The code used is very similar to the example above. The difference is that logic is selected to be implemented in an incomplete LUT as well as two complete LUTs instead of targeting a single incomplete LUT.
Another embodiment of the present invention for determining whether an incomplete LUT can implement a function is now described. This embodiment has the advantage of being able to recognize all functions that can be implemented by a particular type of incomplete LUT. According to this embodiment, a truth table is constructed for the function under consideration. The truth table variables are tested one by one as candidates for each input position using two types of operations.
The operations involved include co-factoring and dependency checking. Co-factoring involves splitting a truth table into two halves corresponding to a given variable being high and low. Dependency checking involves testing whether the value of a given variable effects the output of a truth table. For example, if the co-factors for a variable are equal, the function does not depend on that variable.
The following generic code is one example of a procedure that can determine whether LUT 101 can implement a particular function. Procedure D below is merely an illustrative example that is not intended to limit the scope of the present invention.
For each variable V
Co-factor on V
If the V = 1 portion of the table depends only on 1 variable and the
V = 0 portion of the table depends on 2 variables
Then a solution exists
The LUT 101 C input is assigned to the variable V signal
The LUT 101 B input is assigned to the signal appearing in the
The LUT 101 A input is the unused signal
The appropriate LUT storage contents can be computed from the V=0 co-factor truth table. The LUT storage contents need to be customized for each different incomplete LUT.
A more general methodology for determining whether an incomplete LUT can implement a function using a truth table is shown in
At step 511, the next 2:1 multiplexer in the network is selected starting from the output of the incomplete LUT and working backwards towards the inputs of the incomplete LUT. In the first iteration of the methodology, the 2:1 multiplexer that is nearest to the output of the incomplete LUT is selected. At step 512, a select signal from the truth table for the function is proposed to drive the select terminal of the 2:1 multiplexer.
At step 513, the truth table for the function is split into the 0 and 1 co-factors of the select signal. For each smaller complete LUT connected to an input of the current 2:1 multiplexer, the truth table is checked at step 514 to determine if the truth table depends on variables that can be fed into one of the smaller complete LUTs.
At decisional step 515, the network is analyzed to determine if there are any more 2:1 multiplexers that have not been evaluated yet. If all of the 2:1 multiplexers in the network have been evaluated, the process terminations. If there are 2:1 multiplexers in the network that have not been evaluated, steps 511-514 are repeated for the next 2:1 multiplexer.
An example of a specific process for implementing this embodiment for incomplete 9 input LUT 201 is now discussed. Incomplete 9 input LUT 201 is divided into two complete LUTs that each have 4 inputs and a 2:1 multiplexer. The two LUTs feed into the 2:1 multiplexer. The select input of the multiplexer is controlled by the ninth input signal.
According to this example process, a truth table is built for a function in a user circuit that has up to 9 inputs. For each input signal S of the function, a co-factor of the complete 9 input truth table is built for the case where S=0. The S=0 co-factor truth table is checked for dependency on 4 or fewer variables. If the S=0 co-factor truth table depends on more than 4 variables, the process skips ahead to the next S input signal.
For each input signal S of the function, a co-factor of the complete 9 input truth table is built for the case were S=1. The S=1 co-factor truth table is checked for dependency on 4 or fewer variables. If the S=0 co-factor truth table depends on more than 4 variables, the process skips ahead to the next S input signal.
If the process has not skipped the first S input signal because the S=0 and the S=1 co-factor truth tables each depend on 4 or less variables, the incomplete 9 input LUT can implement the function. The S=1 co-factor truth table is applied to one of the 4 input complete LUTs, and the S=0 co-factor truth table is applied to the second 4 input complete LUT. The S input signal that lead to the solution is applied to the select terminal of the 2:1 multiplexer. If the first iteration of the process fails, the process considers all of the other S input signals to determine if a solution can be found.
According to another embodiment of the present invention, the truth table embodiment is implemented using binary decision diagram (BDD) operations instead of a truth table. Co-factoring a variable is equivalent to rotating that variable to the top of the BDD and considering the high and low branches of the BDD that correspond to high and low co-factors, as described above. Thus, the 1 and the 0 co-factors of a variable of a function are the high and low branches of the BDD. Dependency checking is implemented in a BDD by traversing down the BDD tree looking for a node on that variable's level. The variables can be reordered or rotated into any order. The coding complexity and runtime of this embodiment of roughly equivalent to the truth table embodiment.
The techniques of the present invention can be used as part of a technology mapping process to convert a circuit design into a network of LUTs and other circuit elements that can be programmed into a programmable logic integrated circuit. Programmable logic integrated circuits include programmable logic devices (PLDs), field programmable gate arrays (FPGAs), programmable logic arrays, configurable logic arrays, etc.
An LE is a programmable logic block that provides for efficient implementation of user defined logic functions. PLD 600 has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration.
PLD 600 also includes a distributed memory structure including RAM blocks of varying sizes provided throughout the array. The RAM blocks include, for example, 512 bit blocks 604, 4K blocks 606 and a M-RAM block 608 providing 512K bits of RAM. These memory blocks can also include shift registers and FIFO buffers.
PLD 600 further includes digital signal processing (DSP) blocks 610 that can implement, for example, multipliers with add or subtract features. I/O elements (IOEs) 612 located, in this example, around the periphery of the device support numerous single-ended and differential I/O standards. It is to be understood that PLD 600 is described herein for illustrative purposes only and that the present invention can be implemented for many different types of PLDs, FPGAs, and the like.
While PLDs of the type shown in
System 700 includes a processing unit 702, a memory unit 704 and an I/O unit 706 interconnected together by one or more buses. According to this exemplary embodiment, a programmable logic device (PLD) 708 is embedded in processing unit 702. PLD 708 can serve many different purposes within the system in
Processing unit 702 can direct data to an appropriate system component for processing or storage, execute a program stored in memory 704 or receive and transmit data via I/O unit 706, or other similar function. Processing unit 702 can be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, programmable logic device programmed for use as a controller, network controller, and the like. Furthermore, in many embodiments, there is often no need for a CPU.
For example, instead of a CPU, one or more PLDs 708 can control the logical operations of the system. In an embodiment, PLD 708 acts as a reconfigurable processor, which can be reprogrammed as needed to handle a particular computing task. Alternately, programmable logic device 708 can itself include an embedded microprocessor. Memory unit 704 can be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, PC Card flash disk memory, tape, or any other storage means, or any combination of these storage means.
While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes, and substitutions are intended in the present invention. In some instances, features of the invention can be employed without a corresponding use of other features, without departing from the scope of the invention as set forth. Therefore, many modifications may be made to adapt a particular configuration or method disclosed, without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments and equivalents falling within the scope of the claims.
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|U.S. Classification||716/103, 716/107|
|Cooperative Classification||Y02T10/82, G06F17/505, G06F17/5054|
|European Classification||G06F17/50D4, G06F17/50D2|
|Aug 6, 2004||AS||Assignment|
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BAECKLER, GREGG WILLIAM;YUAN, JINYONG;MENDEL, DAVID W.;REEL/FRAME:014986/0726;SIGNING DATES FROM 20040513 TO 20040527
|Dec 28, 2010||FPAY||Fee payment|
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