|Publication number||US7251268 B2|
|Application number||US 10/003,065|
|Publication date||Jul 31, 2007|
|Filing date||Nov 2, 2001|
|Priority date||Nov 22, 2000|
|Also published as||CN1206817C, CN1419750A, EP1240726A1, US20020080862, WO2002043263A1|
|Publication number||003065, 10003065, US 7251268 B2, US 7251268B2, US-B2-7251268, US7251268 B2, US7251268B2|
|Original Assignee||Koninklijke Philips Electronics N.V.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Non-Patent Citations (2), Referenced by (6), Classifications (13), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a Rake receiver having particular, but not exclusive, application as a direct-sequence CDMA (code division multiple access) receiver suitable for use in IS95 and third generation (3 GPP) telephones.
The Rake receiver is known from article by R. Price and P. E. Green, “A Communication Technique for Multipath Channel” 1958 Proceedings of the IRE pp 555 to 570. In simple terms a Rake receiver architecture provides an effective immunity to the effects of inter-symbol interference (ISI) in the presence of multipath propagation conditions which cause the same signal to be repeatedly received at an antenna at a plurality of different time intervals. The received signal is received and frequency down-converted and the down-converted signals are applied to a plurality of signal paths, frequently called Rake fingers, each having a different time delay. Each signal path includes a correlator which produces its version of the received signal. The versions are combined and integrated over a symbol period.
In earlier versions of the Rake receiver the delays were provided by a delay line having a plurality of taps, successive taps being separated by substantially equal time delays. Only a small number of the signal paths contribute energy to the received symbol and the relative delays of these paths vary slowly with time.
A more modern version of the disclosed Rake receiver has fewer taps but each has a variable delay. The optimum delay for each tap is maintained by a delay-locked loop. A typical delay-locked loop is disclosed in an article by J. J. Spilker, Jr. “Delay-Lock Tracking of Binary Signals” 1963 IEEE Transactions on Space Electronics and Telemetry, 9(1963) pages 1 to 8. In an implementation of a delay-locked loop for use in a direct-sequence CDMA receiver the transmitted signal includes a pilot code and at the Rake receiver a frequency down-converted signal in each of the signal paths is correlated with a locally generated version of the pilot code. The correlation is done a fraction of a chip early and also a fraction of a chip late and the delay of the delay-locked loop is adjusted in the direction of the more favourable correlation. This technique gives an early-late gate for time tracking. The optimal delay, halfway between the early and late signals, is multiplied with the output of the delayed lock loop and is combined with outputs from the other signal paths (or Rake fingers) for optimal decoding of the wanted signal.
Modern implementations of a Rake receiver are digital and the output signal from the receiver/ADC is therefore digital being both level-discrete and time-discrete. It has been found in the case of 3GPP that in order to extract most of the energy from a given signal path, the time delay in that path should be controllable to a fraction of a chip, typically ¼ of a chip, so the sampling rate of the ADC needs to be at least four times the chip rate, the signal bandwidth being roughly half the chip rate. In order to prevent adjacent channel signals from interfering with the operation of the delay-locked loop, the signal from the receiver/ADC needs to be filtered of the order of 4 times more strongly than would be required by its sampling rate. Such strong filtering is wasteful of resources, such as the component count and current consumption, as larger integration time constants will be required for analogue filtering prior to analogue to digital conversion and/or a larger number of taps will be required for digitally filtering of oversampled ADCs.
An object of the present invention is to reduce the effects of adjacent channel interference in a cost effective manner.
According the present invention there is provided a Rake receiver comprising a radio signal receiving stage, an analogue-to-digital converter (ADC) coupled to the receiving stage, the ADC output being coupled to an input of each of a plurality of signal paths each of the signal paths including signal processing means, combining means for combining outputs from the signal paths and means for recovering symbols from the combined outputs, the receiver further comprising code generation means for generating a filtered pilot code, and the signal processing means in each of the signal paths comprising a variable delay means for delaying a signal in that path by a desired amount and a means for correlating the delayed signal with the filtered pilot code.
The present invention is based on the realisation that interference from out-of-band signals only occurs because the pilot code, which comprises a sequence of +1 and −1 values, has harmonics which occur outside the signal bandwidth. Filtering the pilot code signal, which may be implemented by interpolating the pilot code signal which starts as ±1 values, gives it a multibit representation and is much easier than filtering the received signal in a higher order filter than is justified by the chip rate.
In an embodiment of the invention the signal processing means includes signal deriving means coupled to an output of the code generation means and to the variable delay means for deriving an early-late timing error signal for the signal path, which timing error signal is supplied to means for adjusting the variable time delay of the variable delay means and for deriving an indication of the strength of the received signal in the respective signal path, and means for multiplying the delayed signal from the variable delay means by the complex conjugate of the indication of its strength and applying the result to the combining means.
In a further embodiment of the invention the code generation means comprises fixed delay means and the signal deriving means comprises first, second and third correlators, each of the first, second and third correlators having first and second inputs, the first input of the first correlator being coupled to the output of the variable delay means, first and second differential delay means having inputs coupled to the output of the variable delay means and outputs coupled respectively to the first inputs of the second and third correlators, the first differential delay means delaying the output of the variable delay means by half a chip period and the second differential delay means delaying the output of the variable delay means by a chip period, second inputs of the first, second and third correlators being coupled to an output of the code generation means, a differencing circuit having inputs connected respectively to outputs of the first and third correlators and an output for the early-late timing error signal, and the second correlator having an output for the indication of the strength of the received signal in the signal path.
The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein:
In the drawings, the same reference numerals have been used to indicate corresponding features.
The Rake receiver shown in
The signal from the signal splitter 18 is applied to a variable delay element 20. The delay of the variable delay element 20 is adjusted to optimise the signal being processed in the signal path RF1. The variable delay element 20 provides three signal outputs, namely early, on-time and late, which are coupled respectively to first inputs 22, 24, 26 of three correlators CR1, CR2 and CR3.
A code generation means 300 comprises a source of pilot code 30 coupled to a fixed delay stage 32 which provides an output 36 and which is connected to second inputs 23, 25 and 27 of the correlators CR1, CR2 and CR3.
Each of the three correlators CR1, CR2, CR3 comprises a multiplier 40 for multiplying the signals on the respective first and second inputs and a stage 42 for determining the amplitude, a, and the phase, ø, of the signal from the multiplier 40. Early and late outputs from the correlators CR1, CR3 are applied to a differencing stage 44 from which an early-late timing error for the Rake finger RF1 is determined and applied to a stage 46 which decides if the delay of the variable delay element 20 should be updated and if so it sends a signal on a line 47. The timing error is generally compared to a threshold and if it exceeds the threshold the delay is adjusted, otherwise it is left as it is. The combination of the variable delay element 20 and the generation of the feedback signal on the line 47 constitute a delay lock loop.
An on-time output of the correlator CR2 is applied to a multiplier 48 which also receives the signal from the delay element 20. This signal is delayed in a delay stage 50 by an amount to compensate for the processing of the signals in the correlator CR2. In the multiplier 48 the signal from the delay stage 50 is multiplied by the complex conjugate of the correlation obtained from the correlator CR2 to provide a best version of the signal. This best signal is combined maximally with the best signals from the other Rake fingers RF2, RFN in a summation stage 52 and the sum signal is applied to a despread stage 54. The signal obtained is applied to an integrate and dump stage 56 in which the symbols are recovered.
In the case of using the circuit of
In operation the ADC 14 oversamples the I and Q signals at 4 times the chip rate and the correlators CR1, CR2 and CR3 are also operating at 4 times the chip rate to avoid aliasing. The output from the variable delay element 20 is at the chip rate and the output from the correlator CR2 gives the amplitude, a, and the phase, φ, values of the on-time pilot. More particularly the stage 42 of the correlator CR2 integrates and dumps the applied signals and optionally interpolates the output to provide a signal at lower than the chip rate and perhaps slower than the symbol rate.
Since the interpolated pilot code from the digital filter 60 is no longer ±1, the multiplications inside the correlators CR1, CR2, CR3 become true multiplications at the sample rate rather than additions or subtractions. There are simplications which can be made to reduce signal processing because the number of interpolated pilot values is small.
The stages 42 of the correlators CR1, CR2, CR3 comprise integrate and dump stages which provide implicit filtering of the signals.
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|1||By J.J. Spiklker, Jr. Entitled: "Delay-Lock Tracking of Binary Signals" 1962 IEEE Transactions on Space Electronics and Telemetry, 9 (1963) pp. 1-8.|
|2||By R. Price & P.E. Green Entitled: "A Communication Technique for Multipath Channel" 1958 Proceedings of the IRE pp. 555-570.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
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|US8984035 *||Jan 27, 2010||Mar 17, 2015||Ess Technology, Inc.||Channel select filter apparatus and method|
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|U.S. Classification||375/150, 375/142, 375/152, 375/E01.032, 375/343|
|International Classification||H04B1/707, H04B7/02, H04B1/00, H04L27/06|
|Cooperative Classification||H04B2201/70701, H04B1/7117, H04J13/10|
|Nov 2, 2001||AS||Assignment|
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., NETHERLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ALI, DANISH;REEL/FRAME:012355/0926
Effective date: 20010919
|Mar 7, 2011||REMI||Maintenance fee reminder mailed|
|Jul 31, 2011||LAPS||Lapse for failure to pay maintenance fees|
|Sep 20, 2011||FP||Expired due to failure to pay maintenance fee|
Effective date: 20110731