|Publication number||US7256465 B2|
|Application number||US 10/761,704|
|Publication date||Aug 14, 2007|
|Filing date||Jan 21, 2004|
|Priority date||Jan 21, 2004|
|Also published as||US20050156254|
|Publication number||10761704, 761704, US 7256465 B2, US 7256465B2, US-B2-7256465, US7256465 B2, US7256465B2|
|Inventors||Tingkai Li, Sheng Teng Hsu, Bruce D. Ulrich|
|Original Assignee||Sharp Laboratories Of America, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (4), Classifications (28), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a MOS transistor with a shallow metal oxide surface channel, and a method for fabricating the same.
2. Description of the Related Art
State-of-the-art CMOS transistors are often made using a gate material having a high work function, which corresponds to a high threshold voltage. For example, P+ polysilicon and N+ polysilicon (polySi) are used as the gate electrodes for nMOS and pMOS transistors, respectively. These poly gate transistors can be made using simple, lower cost fabrication processes, and the end product is reliable. High work function polySi gate electrodes are formed as a result of a high surface doping density. However, the high surface doping density reduces the electron and hole mobility, degrading transistor performance parameters such as switching time.
Gate electrodes can also be formed from metals, which have a relatively high work function as compared to polySi. However, metal gate transistors require the use of a different metal for nMOS transistors, than is used for pMOS transistors. This two-metal gate electrode approach adds to process complications and costs.
It would be advantageous if a high performance CMOS transistor could be fabricated, that also had a high work function.
It would be advantageous if the above-mentioned transistor could be fabricated without the use of highly doped polySi, or two-metal gate electrode materials.
The present invention transistor device structure uses a semiconductive metal oxide as conductive channel. This structure permits a single metal, with mid-gap work function, to be used for both n-channel and p-channel transistors. As a result of using only a single gate electrode material for both types of transistors, the fabrication process is greatly simplified.
Accordingly, a method is provided for fabricating an ultra-shallow surface channel MOS transistor. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3.
In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; conformally depositing oxide; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material, and the placeholder is etched to the level of the high-k dielectric. Alternately, the high-k dielectric is deposited following the etching of the placeholder material to form the gate region, and the gate electrode is deposited overlying the high-k dielectric.
Additional details of the above-described method and an ultra-shallow surface channel MOS transistor are provided below.
As mentioned above, the present invention device can be fabricated using many conventional processes. The device isolation and P- (or N-) well may be formed using any of the state of the art process. However, the well doping density can be much higher than a conventional process, to avoid the short channel effect. Additional fabrication process can be as follows:
1. Deposit an un-doped semiconductive metal oxide of thickness 10 nm to 20 nm.
2. Deposit a thin layer of high-k gate dielectric insulator. The material can be any high-k dielectric, such as HfO2, HfAlOx, ZrO2, Al3O4, etc. The thickness may be from 1 nm to 5 nm, depending on the channel length of the device.
3. Deposit a layer of material such as polysilicon, but not Si3N4, and pattern to form a sacrificial gate placeholder. The thickness of this material is essentially the same as that of the metal gate material. During patterning, the sacrificial gate placeholder, the high-K dielectric, but not semiconductive metal oxide, are also etched.
4. LDD ion implant, followed by sidewall insulator formation. The sidewall insulator may be Si3N4. During sidewall etching, the semiconductive metal oxide is also (partially) etched. A heavy ion implantation and activation follow, to completely form the source/drain regions of the device.
5. Deposit oxide having thickness about 1.2 to 1.5 time thicker than that of the material deposited in step 3. CMP the oxide, stopping at the sacrificial gate placeholder.
6. Selectively etch the sacrificial gate placeholder.
7. Deposit metal and CMP metal to form gate electrode.
8. Deposit additional oxide for device passivation.
9. Form contact holes using a photoresist process to etch the oxide.
10. Deposit metal and pattern to form metal interlevel interconnects.
The above-mentioned steps refer essentially to the device shown in
Step 702 forms CMOS source and drain regions with a surface, and an intervening well region with a surface. Step 704 deposits a surface channel on the surface overlying the well region. Step 706 forms a high-k dielectric overlying the surface channel. Step 708 deposits a placeholder material overlying the surface channel. Step 710 conformally deposits oxide. Step 712 etches the placeholder material to form a gate region overlying the surface channel. Step 714 forms a gate electrode overlying the high-k dielectric. That is, Step 714 forms the gate electrode in the gate region.
In one aspect of the method, Step 709, following the deposition of the placeholder material (Step 708), lightly doped drain (LDD) processes the source and drain regions. Then, forming a high-k dielectric insulator overlying the surface channel (Step 706) includes depositing the high-k dielectric prior to the deposition of the placeholder material. Step 716 forms sidewall insulators adjacent the surface channel, high-k dielectric insulator, and gate region. Step 718 heavy ion implants and activates the source and drain regions.
In some aspects, forming sidewall insulators adjacent the surface channel, high-k dielectric insulator, and gate region (Step 716) includes forming sidewalls from a material such as Si3N4 or Al2O3. However, other insulator materials are known in the art.
In this aspect, Step 803 a, prior to the deposition of the surface channel, lightly doped drain (LDD) processes the source and drain regions. Step 803 b heavy ion implants and activates the source and drain regions. Unlike the method of
In one aspect, depositing a placeholder material overlying the surface channel Step 708 (806) includes forming placeholder material to a first thickness with a placeholder material surface. Isotropically depositing oxide in Step 710 (808) includes depositing oxide to a second thickness in the range of 1.2 to 1.5 times the first thickness. The method further comprises Step 713 (813) of chemical mechanical polishing (CMP) the oxide to the level of the placeholder material surface. Steps 713 and 813 are not shown.
A shallow surface channel MOS transistor and corresponding fabrication process have been presented. Specific materials have been used as examples to illustrate the invention. However, the above description is not intended to list every possible type of material. Likewise, the mentioned thicknesses and electrical specifications may be modified to suit desired transistor operating characteristics. Other variations and embodiments of the invention will occur to those skilled in the art.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6621114 *||May 20, 2002||Sep 16, 2003||Advanced Micro Devices, Inc.||MOS transistors with high-k dielectric gate insulator for reducing remote scattering|
|US6656852 *||Dec 6, 2001||Dec 2, 2003||Texas Instruments Incorporated||Method for the selective removal of high-k dielectrics|
|US6753230 *||Dec 30, 2002||Jun 22, 2004||Hynix Semiconductor Inc.||Method for fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by decaborane doping|
|US6794234 *||Dec 9, 2002||Sep 21, 2004||The Regents Of The University Of California||Dual work function CMOS gate technology based on metal interdiffusion|
|US6900094 *||Jun 14, 2002||May 31, 2005||Amberwave Systems Corporation||Method of selective removal of SiGe alloys|
|US20030234439 *||Jun 25, 2002||Dec 25, 2003||Amberwave Systems Corporation||SiGe gate electrodes on SiGe subtrates and methods of making the same|
|US20040150052 *||Dec 15, 2003||Aug 5, 2004||Damiano Riccardi||Integrated electronic device and manufacturing method thereof|
|US20040155846 *||Feb 7, 2003||Aug 12, 2004||Randy Hoffman||Transparent active-matrix display|
|US20060011983 *||Sep 22, 2005||Jan 19, 2006||Amberwave Systems Corporation||Methods of fabricating strained-channel FET having a dopant supply region|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7566904 *||Jun 7, 2006||Jul 28, 2009||Casio Computer Co., Ltd.||Thin film transistor having oxide semiconductor layer and manufacturing method thereof|
|US7585698||Aug 12, 2008||Sep 8, 2009||Casio Computer Co., Ltd.||Thin film transistor having oxide semiconductor layer and manufacturing method thereof|
|US20060284172 *||Jun 7, 2006||Dec 21, 2006||Casio Computer Co., Ltd.||Thin film transistor having oxide semiconductor layer and manufacturing method thereof|
|US20080305575 *||Aug 12, 2008||Dec 11, 2008||Casio Computer Co., Ltd.||Thin film transistor having oxide semiconductor layer and manufacturing method thereof|
|U.S. Classification||257/410, 257/E29.056, 438/261, 257/E21.444, 438/215, 257/E29.266, 257/289, 257/E29.079, 257/411, 257/E21.426, 257/288|
|International Classification||H01L21/8238, H01L29/10, H01L29/78, H01L29/94, H01L29/26, H01L21/336, H01L27/092|
|Cooperative Classification||H01L29/66651, H01L29/66545, H01L29/26, H01L29/6659, H01L29/7833, H01L29/1054|
|European Classification||H01L29/66M6T6F8, H01L29/10D2B4, H01L29/26, H01L29/78F|
|Jan 21, 2004||AS||Assignment|
Owner name: SHARP LABORATORIES OF AMERICA, INC., WASHINGTON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, TINGKAI;HSU, SHENG TENG;ULRICH, BRUCE D.;REEL/FRAME:014923/0893
Effective date: 20040120
|Sep 10, 2007||AS||Assignment|
Owner name: SHARP KABUSHIKI KAISHA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHARP LABORATORIES OF AMERICA, INC.;REEL/FRAME:019795/0646
Effective date: 20070910
|Feb 1, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Mar 27, 2015||REMI||Maintenance fee reminder mailed|
|Aug 14, 2015||LAPS||Lapse for failure to pay maintenance fees|
|Oct 6, 2015||FP||Expired due to failure to pay maintenance fee|
Effective date: 20150814