|Publication number||US7268384 B2|
|Application number||US 11/292,028|
|Publication date||Sep 11, 2007|
|Filing date||Dec 1, 2005|
|Priority date||Jul 7, 2003|
|Also published as||US6921692, US7008843, US7419865, US20050009270, US20050207215, US20060082004, US20070004132|
|Publication number||11292028, 292028, US 7268384 B2, US 7268384B2, US-B2-7268384, US7268384 B2, US7268384B2|
|Inventors||Kunal R. Parekh, Byron N. Burgess|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (49), Referenced by (4), Classifications (32), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This patent resulted from a continuation application of U.S. patent application Ser. No. 11/135,534, filed May 23, 2005, now U.S. Pat. No. 7,008,843 entitled “Methods of Forming Memory Circuitry”, naming Kunal R. Parekh and Byron N. Burgess as inventors, the disclosure of which is incorporated by reference, which resulted from a continuation application of U.S. patent application Ser. No. 10/615,287, filed Jul. 7, 2003, entitled “Methods of forming Memory Circuitry”, naming Kunal R. Parekh and Byron N. Burgess as inventors, and which is now U.S. Pat. No. 6,921,692, the disclosure of which is incorporated by reference.
The invention is related to methods of forming memory circuitry.
Many types of memory circuitry utilize a combination of word lines, bit lines and capacitors which are arranged to form one or more memory arrays. In some instances, the bit lines are formed elevationally higher than or overlapping with the capacitors, while in other instances the bit lines are formed elevationally lower than the capacitors. Regardless, peripheral control or other circuitry is commonly fabricated at some location external to the array, and is conventionally referred to as peripheral circuitry. Such circuitry typically includes local interconnect lines which interconnect various conductive nodes of different devices in the peripheral circuitry. Such nodes might constitute metal or metal compounds and/or diffusion regions of common or differing conductivity types.
While the invention was motivated in addressing processing associated with the above-described circuitry, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.
The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
Other aspects and implementations are contemplated.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
Exemplary preferred embodiments of methods of forming memory circuitry are described with reference to
A plurality of spaced-apart word lines 19, 21, 23 and 25 is formed over substrate 22, and in part defines individual substrate locations 26, 28 and 30 with which electrical communication is desired. Substrate locations 26 and 30, on opposite sides of substrate location 28, constitute locations with which electrical communication will be established with individual storage capacitors, and are referred to herein as capacitor nodes. Substrate location 28 constitutes a location with which electrical communication will be established with a bit line, and is herein referred to as a bit node. In a preferred embodiment, the substrate locations comprise diffusion regions 27, 29 and 31, respectively, which are received within substrate 22. However of course, nodes 26, 28 and 30 might comprise other structures, for example elevated source/drains, plugs, etc., and include one or more conductive/semiconductive layers and whether existing or yet-to-be developed.
Word lines 19, 21, 23 and 25, and substrate locations 26, 28 and 30, are formed relative to an active area 32 which is isolated relative to other active areas by isolation regions 33, and which can be formed through conventional or yet-to-be developed techniques, such as shallow trench isolation. Each exemplary preferred embodiment word line is depicted as including a gate oxide layer 37, a polysilicon layer 13 and a silicide or higher conductive layer 15. An insulative cap 17 is provided, as are insulative sidewall spacers 42. Other word line constructions and or materials can, of course, be utilized. For purposes of the continuing discussion, word lines 21 and 23 can be considered as comprising a first pair of word lines having a bit node 28/29 received therebetween, and word lines 23 and 25 can be considered as a second pair of word lines having a capacitor node 30/31 received therebetween.
Peripheral circuitry area 14, by way of example only, is depicted as having a first node 34 and a second node 35. Such might constitute common or differing conductivity diffusion regions, as depicted, or might constitute any other conductive material node location where it is desired in one implementation to form some sort of local interconnecting line interconnecting a first node and a second node in the peripheral circuitry area.
Subsequent processing will preferably form a capacitor of a memory cell of the memory circuitry after having formed the bit line and local interconnect line. Such is shown, by way of example only, with respect to
Such provides but one example of forming exemplary capacitors of respective memory cells of memory circuitry in electrical connection with capacitor nodes 26 and 30, and whereby an elevationally outermost electrode (i.e., 80) of a capacitor is received everywhere elevationally outward of the illustrated bit line. Of course, attributes of the invention might be practiced in the formation of memory circuitry not comprising buried bit line memory cells without departing from certain principles and aspects of the invention.
By way of example only, and not in any way of limitation, the invention might provide an advantage over certain previous technology in the provision of low resistant contacts to the digit line node while enabling the commensurate fabrication of one, more or all local interconnect lines within the periphery between various metal, metal compound, n+ and p+ regions, with reduced masking steps where masking is utilized.
In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means wherein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
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|U.S. Classification||257/314, 257/907, 257/906, 257/71, 257/70, 257/309, 257/305, 257/68, 257/296, 257/300, 257/905|
|International Classification||H01L27/108, H01L21/8242, H01L21/8234, G11C11/00, H01L21/60|
|Cooperative Classification||Y10S257/905, Y10S257/907, Y10S257/906, H01L27/10814, H01L27/10894, H01L21/76831, H01L21/76834, H01L27/10888, H01L21/76897, H01L21/76895, H01L27/10855|
|European Classification||H01L27/108M8, H01L27/108M4D4, H01L21/768B10S, H01L21/768S, H01L21/768C10|
|Feb 10, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Feb 25, 2015||FPAY||Fee payment|
Year of fee payment: 8
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426