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Publication numberUS7273768 B2
Publication typeGrant
Application numberUS 11/213,847
Publication dateSep 25, 2007
Filing dateAug 30, 2005
Priority dateAug 30, 2005
Fee statusPaid
Also published asUS20070048901
Publication number11213847, 213847, US 7273768 B2, US 7273768B2, US-B2-7273768, US7273768 B2, US7273768B2
InventorsLu-Chen Hwan
Original AssigneeMutual-Pak Technology Co. Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Wafer-level package and IC module assembly method for the wafer-level package
US 7273768 B2
Abstract
A wafer-level package and an IC module assembly method for a wafer-level package are provided in the present invention. The method comprises forming a metal bump on a wafer, applying a high polymer resin coating to the wafer, grinding a surface of the resin coating, printing an endpoint on the wafer, a grinding and cutting step and bonding the chips to an antenna or substrate with SMT. The present invention can be used to manufacture high quality chips of low cost with mass production to significantly reduce cost and maintain high quality of the products.
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Claims(6)
1. A wafer-level package and an IC module assembly method for the wafer-level package comprising:
forming a metal bump on a wafer: printing a conductive metal paste on an I/O pad of the wafer with a steel plate printing technique, then solidifying to form the metal bump;
applying a high polymer resin coating: applying the high polymer resin coating to the surface of the wafer over the metal bump with a printing technique and solidifying the resin coating;
grinding a surface of the resin coating: grinding the solidified resin coating on the surface of the wafer until the metal bump is exposed and a required thickness of the resin coating is reached;
printing an endpoint on the exposed metal bump: an endpoint referring to a joint point of a wafer die part and an antenna or a substrate;
grinding and cutting: grinding a back side of the wafer to a required thickness, then cutting the wafer into multiple chips to complete a package process; and
bonding the chips to an antenna or substrate with SMT (surface mounting technology).
2. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the conductive metal paste is a cooper paste.
3. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the conductive metal paste is a silver paste.
4. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the conductive metal paste is a solder paste.
5. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the endpoint is a silver paste.
6. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the endpoint is a solder paste.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a wafer-level package comprising a printing technique for a small sized IC (integrated circuit) such as a RFID (radio frequency identification) IC, an LED (light emitting diode) IC, a diode IC and the like, which has just a few pins. The wafer-level package is further fabricated into a SMT (surface mounting technology) component after grinding and cutting, and can be then assembled on an antenna or a substrate with SMT.

2. Description of the Related Art

In a conventional chip scale package (CSP), production capability and yield of small sized ICs (integrated circuits) are not high. Each wafer is used to manufacture many chips. The chips are then used to fabricate small sized ICs (integrated circuits) such as an RFID (radio frequency identification) IC, an LED (light emitting diode) IC, a diode IC and the like with a few pins. Since the chips are packaged individually, packaging the chips on a wafer with, for example, 30K chips requires a lot of time. On the other hand, a wafer-level package fabricates the ICs on a wafer as a compete IC rather than individual chips, and cuts the wafers into complete packaged ICs. The production efficiency of the wafer-level package for small IC chips is very high. Because a production unit is based on wafers, the general wafer-level package uses equipment similar to equipment used in semiconductor manufacturing, for example, the semiconductor manufacturing processes of metal sputtering, photo etching, polymer coating, solder ball application and the like. Since the wafer-level package is accomplished on wafers, the manufacturing cost for the wafer-level ICs is very high because the investment cost for the manufacturing equipment is very expensive.

For typical small-sized ICs such as RFID or LED ICs, packaging and assembly efficiency is a crucial factor in the determination of product cost. With reference to FIGS. 1A-1E and 2A-2F, conventional single chip packaging and assembly methods comprise scoring and cutting individual ICs from a wafer, bonding the ICs to a substrate, attaching bonding wires and covering or encapsulating the assembly to form an IC module. The IC module is then connected to an antenna or mounted on a substrate to make a product. Mass production equipment for single chip packaging and assembly is very expensive, and the production capability is rather low, so that product unit price is very high. Furthermore, the single chip package is too thick to make very thin small products.

A number of sequential processes are involved in fabricating and packaging single chip products. First, process of FIG. 1A prepares a wafer (70) with multiple wire pads (72). Process of FIG. 1B is wafer cutting and grinding to form chip (71), wherein each chip (71) has several wire pads (72). Process of FIG. 1C is die bonding and wire bonding, wherein the chip (71) is mounted on a substrate (73) and is connected to wire pads (731) on the substrate (73) via wires (74). Process of FIG. 1D is encapsulating, wherein the chip (71) is encapsulated by packaging material (75). The last process of FIG. 1E is packaging, wherein films (77) are applied to package the encapsulated chip (71).

A flip chip packaging method is used to fabricate thin small products, such as IC cards and RFIDs. A metal bump is formed on the wafer. Then the flip chip method is used to attach the IC to a module or directly connect the IC to an antenna or mount the IC on a substrate after wafer grinding and cutting to form a semi-finished wafer-level package.

A number of sequential processes are involved in fabricating thin small products. First, process of FIG. 2A prepares a wafer (80) with multiple wire pads (81). Process of FIG. 2B is bump forming, wherein multiple metal bumps (82) such as gold bumps are formed on the wire pads (81). Process of FIG. 2C is wafer grinding and cutting to form multiple chips (83). Process of FIG. 2D prepares a substrate (90) on which conductive circuits (92) and a layer of conductive paste (91) such as silver paste are applied. The last two processes of FIGS. 2E and 2F are flip chip assembly, wherein the chip (83) is mounted on the substrate (90) and further encapsulated and packaged by films (100)(101).

However, this fabrication method only can be used for flip chip assembly products and cannot be used for SMD products. Problems with flip chip processes are also low production efficiency and high equipment cost that cause a high product unit price, so this method is not used by many manufacturers.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a wafer-level package and an IC module assembly method for the wafer-level package.

According to the objective of the present invention, the wafer-level package makes use of features of the IC module of a small sized IC with few pins to apply an inexpensive wafer-level package method, and then to grind and cut a wafer into a SMD (surface mount device) product. The SMD product can be effectively manufactured and connected to an antenna or mounted on a substrate with mass production.

With the wafer-level package and the IC module assembly method for the wafer-level package in accordance with the present invention, designed products can be accomplished by simple techniques at low cost.

The method comprises:

1. forming a metal bump on a wafer;

2. applying a high polymer resin coating;

3. grinding a surface of the resin;

4. printing endpoint;

5. grinding and cutting; and

6. bonding the chips to an antenna or a substrate with SMT (surface mounting technology).

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1E show a sequential partial product diagrams of a conventional wafer-level package method.

FIGS. 2A-2F show sequential partial product diagrams of another conventional wafer-level package method.

FIGS. 3A-3I show sequential partial product diagrams of a preferred embodiment of an IC module assembly method for a wafer-level package in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention fabricates and assembles a wafer-level package with a method using a printing technique to fabricate a small sized IC (integrated circuit) such as a RFID (radio frequency identification) IC, an LED (light emitting diode) IC, a diode IC and the like with few pins. A wafer is fabricated into an SMT (surface mounting technology) component product by grinding and cutting, and then assembly onto an antenna or a substrate with SMT.

With reference to FIGS. 3A-31, the method in accordance with the present invention comprises forming metal bumps (11) on a wafer (10), applying a high polymer resin coating (20) to the wafer (10), grinding a surface of the resin coating (20), printing an endpoint on the wafer (10), a grinding and cutting step (50) and bonding the chips to an antenna or substrate with SMT.

With reference to FIGS. 3A-3B, the metal bumps (11) are formed on a surface of the wafer (10) by printing a conductive metal paste on I/O pads (12) of the wafer (10) with a steel plate printing technique. Then the conductive metal paste is dried and baked to form the metal bump (11). The conductive metal paste may be a cooper, silver or solder paste.

With reference to FIG. 3C, a high polymer resin coating (20) is applied to the surface of the wafer (10) over the metal bump (11) with a printing technique and dried and baked.

With reference to FIG. 3D, grinding a surface of the resin coating (20): the solidified resin coating (20) on the surface of the wafer (10) is ground until the metal bump (11) is exposed and a required thickness of the resin coating (20) is reached.

With reference to FIG. 3E, printing an endpoint (40): an endpoint (40) refers to a joint point of a wafer die part and an antenna or a substrate and is normally a silver or solder paste.

With reference to FIGS. 3F-3G, grinding and cutting a step: grinding a back side of the wafer (10) to a required thickness and then cutting the wafer (10), along the broken lines, into multiple chips (50).

With reference to FIG. 3H, the step comprises bonding the chip (50) to an antenna or substrate (60) with SMT (surface mounting technology). The substrate (60) includes conductive circuits (61) formed on a surface of the substrate (60). The chip (50) can be contacted with the circuits (61) by conductive metal paste (62) such as a cooper, silver or solder paste.

With reference to FIG. 3I, the chip (50) bonded on the substrate (60) is further packaged by lamination films (64)(65).

The wafer-level package and the IC module assembly method for the wafer-level package make use of features of the IC module of a small sized IC with a few pins to apply an inexpensive wafer-level package method, then grind and dice a wafer into an SMD (surface mount device) product. The SMD product can be effectively manufactured and mounted on an antenna or substrate with mass production.

The present invention can be used to manufacture high quality chips of low cost with mass production to significantly reduce cost and maintain high quality of the products.

Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and features of the invention, the disclosure is illustrative only. Changes may be made in the details, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7989950 *Aug 14, 2008Aug 2, 2011Stats Chippac Ltd.Integrated circuit packaging system having a cavity
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US8704365Jul 20, 2011Apr 22, 2014Stats Chippac Ltd.Integrated circuit packaging system having a cavity
Classifications
U.S. Classification438/113, 438/114, 438/108, 438/465, 257/E21.51, 257/E23.021
International ClassificationH01L21/60, H01L21/58, H01L21/50
Cooperative ClassificationH01L21/561, H01L2924/01029, H01L2924/01047, H01L2924/14, H01L23/3114, H01L2224/83801, H01L2924/01079, H01L2224/274, H01L24/83, H01L2224/13099, H01L24/10, H01L2924/01005, H01L2924/01006, H01L2924/014
European ClassificationH01L24/10, H01L23/31H1, H01L21/56B
Legal Events
DateCodeEventDescription
Mar 22, 2011FPAYFee payment
Year of fee payment: 4
Nov 8, 2006ASAssignment
Owner name: MUTUAL-PAK TECHNOLOGY CO. LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HWAN, LU-CHEN;REEL/FRAME:018492/0888
Effective date: 20061106