|Publication number||US7279783 B1|
|Application number||US 10/977,355|
|Publication date||Oct 9, 2007|
|Filing date||Oct 29, 2004|
|Priority date||Oct 29, 2003|
|Publication number||10977355, 977355, US 7279783 B1, US 7279783B1, US-B1-7279783, US7279783 B1, US7279783B1|
|Inventors||Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Thomas J. Obenhuber, deceased|
|Original Assignee||Silicon Pipe, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (7), Classifications (37), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority from, and hereby incorporates by reference, U.S. Provisional Application No. 60/515,843, filed Oct. 29, 2003 and entitled: “Partitioned Integrated Circuit Package with Central Clock Driver.”
The present invention relates to the field of electronic interconnections and IC packaging technology and semiconductor design architecture.
The current state of semiconductor lithography has enabled electrical circuits on a scale which has been unthinkable even a few years ago. As semiconductor chip features shrink into the nanometer range, overall integrated circuit performance becomes limited by numerous factors among them are cross chip routes, on-chip clock skew and power and ground distribution. Moreover, as IC chips get larger with greater numbers of transistors, they require more signal routing, more I/O and more power to operate. Thus with such a large quantity of circuit elements, the challenges of delivering common signals and power to millions of circuit elements, has become a significant impediment to increasing overall chip performance.
While limited I/O IC packages can normally be easily packaged in leadframe type structures, higher I/O devices typically require more complex interconnection structures. These structures all serve to redistribute the fine pitch I/O of the IC chip to coarser pitches that are more manageable for interconnection at the next level of assembly such as when they are interconnected to a printed circuit board. While ceramic based interconnection structures are not uncommon, most users prefer reinforced organic materials for packaging ICs due to the lower dielectric constant and lower cost.
Present generation printed circuit based IC packaging technologies follow traditional design practices which typically involve the manufacture of monolithic substrates having one, two or more interconnection layers as required to redistribute the IC chip terminations to the more manageable pitch, while providing the best possible interconnection signal integrity. While there have been continuing advances to meet the needs of higher I/O devices, there remain limits to the performance potential of these solutions and it is not clear that the advances achieved will be capable of meeting the performance needs of next generation IC chips at reasonable costs and with reasonably short design cycles. For example, there are proposed solutions that involve total packaging of the IC on the wafer that include power, ground and redistribution wiring in the packaging elements that are bonded to the surface of the wafer. While attractive and offering the potential to reduce the number of I/O by managing, to a degree, the power and ground distribution inside the packaging portion of the completed structure, the manufacturing infrastructure is not yet prepared to deliver this type of solution because of the yield risks associated with assembly of a complete wafer.
Another challenge of present design practice is the management of circuit clocks which are vital to the efficient operation of the IC chip. Clock drivers are in normal practice integrated into the design of the IC chip. As such, they tend to be located in areas of convenience which often results in clock skew and timing errors that must be then addressed either using software or complex circuit routing solutions. Given the present challenges it is clear that there is opportunity and need for improvements which will address the gap between present approaches to and future requirements.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
The present invention has come about in response to the problems occurring in the prior art. A first object of the present invention is to provide a semiconductor package in which the interconnection and packaging elements are partitioned into separate structures that are assembled and interconnected to the IC in separate steps. An example of such an embodiment would be a partial package that provides power, ground and cross chip interconnections which is mounted and interconnected on the face of the chip. The completed subassembly would then be made part of a second package element that would be used for signals and the chip interconnected to it. Thus the final assembly would have at least two separately constructed and interconnected packaging elements as a part of its final construction.
A second object of the present invention is to provide a semiconductor package structure that addresses the need for clock time control, accomplished by separating the clock functions from the chip and packaging them in a separate IC that is a part of the partitioned package interconnection structure. Alternatively, the clock driver chip can be packaged separately from the primary chip
The present invention offers a novel alternative approach to addressing the stated problems by partitioning the IC package into pieces that allow the overall assembly process to separately address the needs of clock, power and ground in a sub-package while continuing to address the needs of high speed signals using more traditional or standard packaging methods. Moreover, it is also noted by the inventors, that a central clock driver chip can be enabled by these methods to further improve the performance of the IC package structure in operation.
The innovative concept comprises a the use of any of a number or alternative signal distribution structures for a semiconductor integrated circuit that provide for the distribution of clocks, power and grounds in a substrate or structure that is separate from, but proximate to the semiconductor chip.
Clocks, power, ground and signal I/O are all required circuit elements of an IC and all must reliably perform their functions. However, the distribution of these signals is impacted by increased resistivity, time delays and general skew differences and these degrading effects tend to increase with increases in the size of the IC chip and thus the advantages of large scale integration begins to quickly evaporate.
A solution to eliminating these particular problems lies just above a mass scale IC chip. By utilizing external signal paths, in conjunction with die bond wires or other interconnection media in non-standard ways, it is possible to distribute clocks, power and ground signals to alleviate the problems associated with on-die routing. Moreover a clock driver chip can be placed either on the chip or near to it in a manner that allows the clocks to be distributed from the center of the main chip to control the distribution of clock signals. This element of the invention may potentially be advantageously employed in standard packaging wherein a separate circuit with the central clock is attached to the surface of the chip and assembled. The figures provided help to better illustrate the invention.
The first stage of assembly involves the placement and interconnection of the smaller portion of the assembly 105 onto the wafer as discrete elements, each having bumped contacts 106 such as solder balls. These discrete elements will desirably provide such functions as power and ground distribution, critical routes and clock distribution or any combination of these functions. While the illustration shows discrete elements 105 attached to the wafer, it is also possible to build the interconnection structure up directly on the surface of the wafer using a suitable process to improve process efficiency. In addition, while the bumps are shown to exist as the package elements are placed onto the IC chips, the bumps could be added after the second stage of assembly is complete.
The second stage of assembly involves the dicing of the wafer into discrete sub-assembled IC packages 107. The sub-assembled packages are placed into the larger partition portion of the package 110 and it is interconnected to the package to the peripheral terminals using a suitable method such as wire bonding (not shown) and the structure is then coated with a suitable encapsulant 109 to protect the chip and produce a completed portioned package assembly 108 having a set of bumps 106 for interconnection at the next level of assembly.
In each of foregoing embodiments it is anticipated that the testing of sorted, unpackaged IC devices 101 will require special considerations since power, ground and clock terminals may require special test probe setup. To alleviate the problem, it is anticipated that power 104P and grounds 104G connections on the IC device 101 may be electrically connected to each other, respectively within the interconnect structure of the IC devices 101 thus easing the burden of probe attaché for low current testing. The addition of the power and ground grids provides for higher speed testing. It is also anticipated that each of the clock connections 104C may have circuitry to drive them from within the IC chip 104 during bare die testing but these drivers are disabled once a clock distribution circuit layer is added.
Although the invention has been described briefly with reference to specific exemplary embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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|U.S. Classification||257/686, 257/E23.079, 257/784, 257/E23.069, 257/E21.5, 257/E25.013, 257/E23.141, 257/723, 257/691, 257/E23.14, 257/E21.502|
|International Classification||H01L23/34, H01L23/02, H01L23/52, H01L23/48|
|Cooperative Classification||H01L2224/48091, H01L21/52, H01L23/50, H01L23/3128, H01L2225/06596, H01L2225/06586, H01L2225/06513, H01L2225/06541, H01L23/24, H01L2225/06527, H01L2225/0652, H01L2225/06572, H01L23/49816, H01L2225/0651, H01L25/0657, H01L21/56|
|European Classification||H01L25/065S, H01L23/24, H01L23/50, H01L23/31H2B, H01L21/52, H01L21/56|
|Jan 3, 2005||AS||Assignment|
Owner name: SILICON PIPE, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FJELSTAD, JOSEPH C.;GRUNDY, KEVIN P.;SEGARAM, PARA K.;AND OTHERS;REEL/FRAME:015520/0953;SIGNING DATES FROM 20041116 TO 20041216
|Aug 7, 2008||AS||Assignment|
|Oct 24, 2008||AS||Assignment|
Owner name: NOVIAS, LLC,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOLDERS, SECURE NOTE;ANDERSON, DAN;FJELSTAD, JOE;AND OTHERS;REEL/FRAME:021744/0512
Effective date: 20080301
|Nov 18, 2008||AS||Assignment|
Owner name: INTERCONNECT PORTFOLIO, LLC,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NOVIAS LLC;REEL/FRAME:021861/0127
Effective date: 20080314
|Mar 4, 2009||AS||Assignment|
Owner name: TECHNOLOGY PROPERTIES LIMITED LLC,CALIFORNIA
Free format text: LICENSE;ASSIGNOR:INTERCONNECT PORTFOLIO LLC;REEL/FRAME:022343/0351
Effective date: 20080315
|Oct 7, 2010||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TECHNOLOGY PROPERTIES LIMITED;REEL/FRAME:025105/0596
Effective date: 20100610
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:INTERCONNECT PORTFOLIO, LLC;INTELLASYS BEC LIMITED;TECHNOLOGY PROPERTIES LIMITED;REEL/FRAME:025105/0634
Effective date: 20100914
|Mar 28, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Mar 25, 2015||FPAY||Fee payment|
Year of fee payment: 8