Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7282375 B1
Publication typeGrant
Application numberUS 10/824,903
Publication dateOct 16, 2007
Filing dateApr 14, 2004
Priority dateApr 14, 2004
Fee statusPaid
Publication number10824903, 824903, US 7282375 B1, US 7282375B1, US-B1-7282375, US7282375 B1, US7282375B1
InventorsNikhil Vishwanath Kelkar
Original AssigneeNational Semiconductor Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Wafer level package design that facilitates trimming and testing
US 7282375 B1
Abstract
A wafer level method of packaging, trimming and testing integrated circuits is described. A wafer having trim pads is bumped before the wafer is trimmed. After the bumping, the dice on the wafer are trimmed and tested using standard trim probing and test probing techniques. After the trimming and testing, an electrically insulative undercoating is applied to the active surface of the wafer. The undercoating directly covers the trim pads while leaving at least portions of the contact bumps exposed. The undercoating may be applied using a variety of different processes, including spin-on coating, molding, screen printing or stencil printing. The undercoating may be formed from a wide variety of material including epoxy, polyimide and silicone-polyimide copolymers. With this approach, the wafer may be trimmed and final tested at substantially the same stage of wafer processing. The trimming and testing operations may be performed either sequentially or substantially simultaneously.
Images(5)
Previous page
Next page
Claims(13)
1. A method comprising:
providing a semiconductor wafer having a plurality of integrated circuit dice formed therein, the integrated circuit dice including a plurality of electrically conductive contact pads and solder-wettable electrically conductive trim pads exposed on an active surface of the wafer, wherein the trim pads are not covered by a passivation layer;
forming contact bumps on a plurality of the contact pads, wherein the solder-wettable electrically conductive trim pads are exposed on the active surface of the wafer during the forming of the contact bumps;
probing the wafer after the contact bumps have been formed, wherein the wafer probing includes,
a trimming operation that includes directly probing solder-wettable portions of the plurality of exposed solder-wettable electrically conductive trim pads and trimming selected circuits associated with selected trims pads, and
a testing operation that involves probing at least some of the plurality of contact bumps to test selected functionalities of the integrated circuits; and
applying an electrically insulating undercoating to the active surface of the wafer that directly contacts and covers the solder-wettable trim pads while leaving at least portions of the contact bumps exposed, the undercoating being applied after the wafer probing, whereby the wafer may be trimmed and tested at substantially the same stage of wafer processing.
2. A method as recited in claim 1 wherein the probing for the trimming and testing operations is performed sequentially.
3. A method as recited in claim 1 wherein the probing for the trimming and testing operations are performed substantially simultaneously.
4. A method as recited in claim 1 wherein the undercoating is formed from a material selected from the group consisting of: epoxies, polyimides, and silicone-polyimide copolymers.
5. A method as recited in claim 1 wherein the undercoating has a final thickness in the range of approximately 0.2 and 4 mils.
6. A method as recited in claim 1 wherein the undercoating is formed from an underfill material that is suitable for filling a region between a die and a substrate that the die is mounted to after the wafer has been diced and the die mounted to the substrate.
7. A method as recited in claim 1 wherein the undercoating is formed from a B-stageable material.
8. A method as recited in claim 1 wherein the undercoating is formed from a curable material, the method further comprising curing the undercoating to permanently affix the undercoating to the surface of the wafer.
9. A method as recited in claim 1 wherein the undercoating is applied by one of a spin-on coating process, a molding process, a screen printing process and a stencil printing process.
10. A method as recited in claim 1 wherein the contact pads each include a metallization stack.
11. A method as recited in claim 10 wherein the trim pads each include a metallization stack.
12. A method as recited in claim 1 further comprising dicing the wafer after the undercoating has been applied to provide a multiplicity of singulated dice each having an undercoat thereon.
13. A method comprising:
providing a semiconductor wafer having a plurality of integrated circuit dice formed therein, the integrated circuit dice including a plurality of electrically conductive contact pads and solder-wettable electrically conductive trim pads exposed on an active surface of the wafer, wherein the trim pads are not covered by a passivation layer;
forming contact bumps on a plurality of the contact pads, wherein the solder-wettable electrically conductive trim pads are exposed on the active surface of the wafer during the forming of the contact bumps;
probing the wafer after the contact bumps have been formed, wherein the wafer probing includes,
a trimming operation that includes directly probing solder-wettable portions of the plurality of exposed solder-wettable electrically conductive trim pads and trimming selected circuits associated with selected trims pads, and
a testing operation that involves probing at least some of the plurality of contact bumps to test selected functionalities of the integrated circuits; and
applying an electrically insulating undercoating to the active surface of the wafer that directly contacts and covers the solder-wettable trim pads while leaving at least portions of the contact bumps exposed, the undercoating being formed from a polymer based adhesive material selected from the group consisting of: epoxies, polyimides, silicone-polyimide copolymers, and BCB and wherein,
the undercoating has a final thickness in the range of approximately 0.2 and 4 mils.
the undercoating is applied after the wafer probing, whereby the wafer may be trimmed and tested at substantially the same stage of wafer processing; and
dicing the wafer after the undercoating has been applied to provide a multiplicity of singulated dice each having an undercoat thereon.
Description
BACKGROUND

The present invention relates generally wafer level processing of integrated circuits. More particularly, a wafer level packaging arrangement is described that permits parameter trimming and final testing to be accomplished during a single probing sequence.

A variety of semiconductor devices (particularly precision analog semiconductor devices) require that the circuits be trimmed after fabrication. Generally, trimming is the process of fine-tuning the performance of an integrated circuit device after fabrication in order to ensure conformance to a desired performance specification. In order to facilitate trimming, it is common to provide metal pads, often referred to as “trim pads” on the active surface of the die. Generally, a specific current is applied to each trim pad at a specific voltage in order to activate components (e.g. fuses) that can adjust the performance of the circuits of interest.

There are a number of conventional processes for packaging integrated circuits. One approach that is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on the face of an integrated circuit die. In some situations, the contacts are formed directly on I/O pads formed on the die, whereas in other situations the contacts are redistributed. The die is then typically attached to a substrate such as a printed circuit board or a package substrate such that the die contacts directly connect to corresponding contacts on the substrate.

When trim pads are included in flip chip package designs (or other wafer level chip scale packages) it is common to deposit a passivation material over the trim pads after the device has been trimmed. By way of example, a representative process might proceed as illustrated in FIG. 5. Specifically, after the wafer is fabricated (302), the wafer is taken to a wafer prober which tests and trims the appropriate circuits (304). The trim pads are generally formed from aluminum and thus they will corrode if left exposed in an ambient environment. Also, if they are left exposed when the singulated die is soldered to a substrate, there is a significant risk that the solder may bridge the gap between one of the bond pad/trim pad pairs, thereby shorting out the die. To avoid these problems, some manufacturing approaches contemplate covering the trim pads with a passivation material after the wafer has been trimmed. This helps reduce corrosion of the trim pads but requires returning to the wafer to the wafer processing chamber where a passivation layer (e.g. polyimide or benzocyclobutene (BCB)) is applied over the trim pads (306). Typically, the passivation layer also extends over edge portions of the I/O pads as well. Thus, the passivation layer is used to isolate the trim pads.

After the passivation layer is applied, appropriate underbump metallization stacks are typically formed on the I/O pads (308) and the wafer is bumped (310). It should be appreciated that there may be a number of other processing steps that occur before, as part of, or after the bumping. When the desired processing is completed, the wafer is again taken to a wafer prober where the final testing occurs.

In this scenario, wafer probe testing must be done twice. Initially, the wafer must be probed to facilitate trimming, which must occur before the trim pads are insulated by the passivation material. The wafer must also be probed a second time to test for electrical function after the contact bumps have been placed on the dies. Although the described process works well, this two-part wafer probing process is inefficient, since the wafer must go to a testing facility for trimming, and subsequently, to a manufacturing facility to cover the trim pads and then back to the testing facility for the final wafer probing before the dies are cut and shipped to customers. These inefficiencies add to the overall cost of manufacturing these IC devices. Therefore, there are continuing efforts to reduce the costs and time associated with the manufacturing process.

SUMMARY

To achieve the foregoing and other objects of the invention, a wafer level method of packaging, trimming and testing integrated circuits is described. In a method aspect of the invention, a wafer having trim pads is bumped before the wafer is trimmed. After the bumping, the dice on the wafer are trimmed and tested using standard trim probing and test probing approaches. After the trimming and testing, an electrically insulative undercoating is applied to the active surface of the wafer. The undercoating directly covers the trim pads while leaving at least portions of the contact bumps exposed. With this approach, the wafer may be trimmed and tested at substantially the same stage of wafer processing. The trimming and testing operations may be performed either sequentially or substantially simultaneously.

The undercoating may be applied using a variety of different processes, including spin-on coating, molding, screen printing or stencil printing. The undercoating may be formed from a wide variety of material including epoxy, polyimide and silicone-polyimide copolymers. In some specific applications, it may be desirable to utilize a curable material (such as an epoxy material) to form the undercoating or even a B-stageable material. In some embodiments, the undercoating may even be arranged to act as an underfill.

The resulting wafers and integrated circuits do not have a passivation layer that extends over the trim pads. Rather, the undercoating electrically isolates the trim pads. In some applications, the undercoating may have a thickness in the range of approximately 0.2 and 4 mils.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1( a) illustrates in top plan view an exemplary wafer that has been formed in accordance with an embodiment the present invention.

FIG. 1( b) illustrates in top perspective view a surface mount semiconductor die scribed from the wafer of FIG. 1.

FIG. 2( a) is a diagrammatic cross sectional view of a portion of a wafer prior to bumping.

FIG. 2( b) is a diagrammatic cross sectional view of the portion of a wafer illustrated in FIG. 2( a) after bumping and undergoing simultaneous testing and trim probing in accordance with an embodiment of the present invention.

FIG. 3 is a diagrammatic cross sectional view of the portion of a wafer illustrated in FIG. 2( b) after application of an undercoat in accordance with an embodiment of the present invention.

FIG. 4 is a process flow diagram illustrating a method of packaging, trimming and testing a wafer in accordance with one embodiment of the present invention.

FIG. 5 is a process flow diagram illustrating an earlier method of packaging, trimming and testing a wafer.

It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the figures are diagrammatic in nature and not to scale.

DETAILED DESCRIPTION

In the described embodiments, a wafer is bumped prior to trimming. The bumped wafer may then be trimmed and final tested at substantially the same stage of wafer processing. The dice on the wafer are trimmed and tested using standard trim probing and test probing approaches. After the trimming and testing, an electrically insulative undercoating is applied to the active surface of the wafer. The undercoating directly covers the trim pads while leaving at least portions of the contact bumps exposed.

Referring initially to FIG. 4 in conjunction with FIG. 2( a), a method of fabricating a wafer in accordance with one embodiment of the invention will be described. Initially, a wafer 100 is fabricated using conventional and/or appropriate wafer fabrication techniques (400). As will be appreciated by those skilled in the art, there are a wide variety of suitable wafer fabrication techniques. The wafer generally will include a multiplicity of dice 102, which each include a number of I/O pads 103 and trim pads 105. FIG. 2( a) diagrammatically illustrates what a cross section of a suitable wafer might look like. Of particular note, a passivation layer 107 generally covers the top surface of the wafer. However, the passivation layer 107 has opening that expose the I/O pads 103 and trim pads 105.

When solder bumps are to be formed directly on the die, it is often desirable to form underbump metallization (UBM) stacks 110 over the I/O pads 103 to provide a good/non-corrosive adhesion base for the solder bumps. (Step 402). In the illustrated embodiment, corresponding metallization stacks 108 are also formed over the trim pads 105. When the trim pads 105 are formed from a material (e.g. aluminum) that oxidizes when exposed to air, it can be particularly advantageous to metalize the trim pads 105 in addition to the I/O pads 103. However, it should be appreciated that the trim pads could alternatively be masked so that the metallization stacks 108 are eliminated. After the underbump metallization stacks 110 have been formed, the wafer may be bumped by any of a wide variety of bumping processes (404). Typically, bumping involves forming solder balls on the underbump metallization stacks, however other suitable contact bump formation techniques (including non-solder based bump formation) can be used as well.

A representative resulting bumped wafer 100 is illustrated in FIG. 1. As seen therein, the representative wafer 100 includes a plurality of dice 102. Each of the dice 102 includes a plurality of solder balls, contacts or “bumps” 106 that are intended to be mounted directly onto contact pads of a substrate, such as a printed circuit board (PCB). The bumps 106 may be formed on the metallization stacks 108 as described above, directly on I/O pads on the die or redistributed using conventional redistribution techniques. (In the case of redistribution, if desired, the trim pads could also be redistributed). It should be noted that while only a relatively small number of dice 102 are shown on the wafer 100 for purposes of illustration, most wafers have significantly more dice formed thereon. By way of example, current state of the art wafers typically have several hundred to several thousand dice formed thereon, and some have more than ten thousand dice. As is well known in the art, most wafers and dice are formed of silicon, although any other appropriate semiconductor material can also be used, including, for example, gallium arsenide (GaAs), indium gallium phosphide, silicon germanium, and the like.

After the wafer has been bumped, other desired wafer level processing such as applying an opaque backcoating to the back surface of the wafer, wafer thinning, marking the wafer, etc. may be performed as desired (406). After the other desired wafer processing (if any) is performed, the wafer is trimmed and final tested (410). The trimming and final testing may be performed either sequentially (i.e., using two or more passes of the wafer prober) or simultaneously (i.e., using a single pass of the wafer prober). The step of wafer probing is diagrammatically illustrated in FIG. 2( b).

After the testing, an undercoating is applied to the active surface of the wafer (412). The structure of a representative wafer 100 having an undercoating 130 formed thereon is diagrammatically illustrated in FIG. 3. The undercoating 130 may be formed from a wide variety of materials. By way of example, a wide variety of polymer based materials including epoxies, polyimides, silicone-polymide copolymers or BCB work well. The undercoating can be applied using any of a variety of conventional coating techniques, including spin-on coating processes, molding processes, screen printing processes, stencil printing processes, etc. The important point is that an undercoating is used as opposed to a conventional semiconductor passivation material such as silicon-nitride or silicon-oxide. As will be appreciated by those skilled in the art, the deposition of a passivation material would require reintroduction of the wafer into a deposition chamber, whereas the simple application of an undercoating does not.

The described undercoating covers the trim pads thereby both electrically insulating the trim pads and isolating the trim pads from the surrounding environment (thereby lowering the risk of corrosion). Since the application of the undercoating (as well as any other wafer processing that occurs after the testing/trimming step is not expected, intended or likely to affect the electrical characteristics of the integrated circuits in any significant manner, there is generally no need to retest the dice at the wafer level after the undercoating has been applied. This is a significant advantage over approaches where the wafer is passivated and bumped after trimming. In those situations, it is generally considered necessary and important to retest the wafer after the passivation and bumping processes have been completed.

It should be appreciated that there are a number of existing processes that contemplate the application of an undercoating to the active surface of a wafer for a variety of different reasons. In many applications, the undercoating 130 used in the present invention may perform multiple functions including some of the functions performed by existing undercoatings. By way of example, U.S. Pat. Nos. 6,352,881 and 6,245,595 and pending application Ser. Nos. 10/080,913 and 10/224,291 (which are incorporated herein by reference) all describe the application of an underfill adhesive material to the front surface of the wafer. Some of the described embodiments utilize B-stageable materials (e.g. B-stageable epoxy materials) as the underfill material. If desired, the undercoating 130 may be an underfill material, as for example a B-stageable underfill material. It should be appreciated that generally, an underfill material is intended to fill the region between the die and a substrate that the die is mounted to after the wafer has been diced and the die mounted to the substrate. U.S. patent application Ser. No. 10/707,208 (which is incorporated herein by reference) describes the use of a hardened undercoat material to constrain the interface between solder balls and their associated contact pads. The undercoating 130 may advantageously be used for this purpose as well. Still other undercoatings and/or underfill adhesives are designed to be optically opaque in order to protect the front surface of a die from exposure to light. Again, it should be appreciated that the undercoating 130 may be optically opaque to accomplish this function as well.

The thickness of the undercoating 130 may be varied widely depending on the needs of a particular situation. Typically undercoatings utilized as underfill materials will be thicker than undercoating that are not also used as underfill. In the illustrated embodiment, the undercoating (which is not used as an underfill) has a final thickness in the range of approximately 0.2 and 4 mils. In some applications, thicknesses in the range of 0.3 to 2 mils work well.

In the illustrated embodiment, the undercoating is formed from a curable material such as an epoxy resin. However, this is not a requirement. A wide variety of materials including thermosetting resins, thermoplastic materials, epoxies, polyimides, silicone-polymide copolymers may be used.

After the undercoating has been applied to the active surface of a wafer, then any additional wafer level processing that is desired may be performed, although it is generally preferable that only processes that are not expected to significantly impact the electrical characteristics of the integrated circuits be done after the wafer has been tested and trimmed. After any additional wafer level processing, the wafer may be singulated (414) using conventional wafer dicing techniques and the resulting dice may be handled as appropriate.

Although only a few embodiments of the invention have been described in detail, it should be appreciated that the invention may be implemented in many other forms without departing from the spirit or scope of the invention. In some circumstances, the ordering of the various described steps (and particularly the order of the other desired wafer processing steps) may be varied to suit the needs of a particular application. The undercoating coating may be formed from an opaque, partially opaque, a translucent or a transparent material.

In some embodiments, an opaque undercoating may be combined with a backcoating and/or wafer level side coating applications so that the dice are effectively encapsulated when they are singulated. The trim pads and contact pads may be formed from a wide variety of materials and/or stacks of materials. By way of example, common materials for use in the trim pads include aluminum, nickel, gold, copper, titanium, palladium, silver, chromium, tungsten and vanadium and various alloys that include some of these materials. Therefore, the present embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5008189Jun 20, 1989Apr 16, 1991UopEnhanced membrane separation of monosaccharides utilizing concentration polarization
US5128746Sep 27, 1990Jul 7, 1992Motorola, Inc.Adhesive and encapsulant material with fluxing properties
US5136365Sep 27, 1990Aug 4, 1992Motorola, Inc.Anisotropic conductive adhesive and encapsulant material
US5214308Jan 23, 1991May 25, 1993Sumitomo Electric Industries, Ltd.Substrate for packaging a semiconductor device
US5244143Apr 16, 1992Sep 14, 1993International Business Machines CorporationApparatus and method for injection molding solder and applications thereof
US5250843Sep 8, 1992Oct 5, 1993Integrated System Assemblies Corp.Multichip integrated circuit modules
US5329423Apr 13, 1993Jul 12, 1994Scholz Kenneth DCompressive bump-and-socket interconnection scheme for integrated circuits
US5376403Oct 1, 1991Dec 27, 1994Capote; Miguel A.Electrically conductive compositions and methods for the preparation and use thereof
US5495439Sep 7, 1994Feb 27, 1996Mitsubishi Denki Kabushiki KaishaSemiconductor memory device having SOI structure and manufacturing method thereof
US5500534Mar 31, 1994Mar 19, 1996Iowa State University Research FoundationIntegrated energy-sensitive and position-sensitive x-ray detection system
US5587342Apr 3, 1995Dec 24, 1996Motorola, Inc.Method of forming an electrical interconnect
US5668059Jul 12, 1996Sep 16, 1997International Business Machines CorporationSolder interconnection structure and process for making
US5698894 *Oct 28, 1996Dec 16, 1997Sgs-Thomson Microelectronics, Inc.Double mask hermetic passivation structure
US5736456Jul 17, 1996Apr 7, 1998Micron Technology, Inc.Method of forming conductive bumps on die for flip chip applications
US5767010Nov 5, 1996Jun 16, 1998McncSolder bump fabrication methods and structure including a titanium barrier layer
US5768290 *Apr 1, 1997Jun 16, 1998Mitsubishi Denki Kabushiki KaishaSemiconductor integrated circuit device incorporating fuse-programmable pass/fail identification circuit and pass/fail determination method thereof
US5773359Dec 26, 1995Jun 30, 1998Motorola, Inc.Interconnect system and method of fabrication
US5872633Feb 12, 1997Feb 16, 1999Speedfam CorporationMethods and apparatus for detecting removal of thin film layers during planarization
US5880530Mar 29, 1996Mar 9, 1999Intel CorporationMultiregion solder interconnection structure
US5895976Jun 3, 1996Apr 20, 1999Motorola CorporationMicroelectronic assembly including polymeric reinforcement on an integrated circuit die, and method for forming same
US5925936Feb 26, 1997Jul 20, 1999Kabushiki Kaisha ToshibaSemiconductor device for face down bonding to a mounting substrate and a method of manufacturing the same
US5937320Apr 8, 1998Aug 10, 1999International Business Machines CorporationBarrier layers for electroplated SnPb eutectic solder joints
US5953623Apr 10, 1997Sep 14, 1999International Business Machines CorporationBall limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection
US5977632Feb 2, 1998Nov 2, 1999Motorola, Inc.Flip chip bump structure and method of making
US6023094Jan 14, 1998Feb 8, 2000National Semiconductor CorporationSemiconductor wafer having a bottom surface protective coating
US6060373Jul 9, 1999May 9, 2000Citizen Watch Co., Ltd.Method for manufacturing a flip chip semiconductor device
US6063647Dec 8, 1997May 16, 20003M Innovative Properties CompanyMethod for making circuit elements for a z-axis interconnect
US6071757Oct 20, 1998Jun 6, 2000Micron Technology, Inc.Condensed memory matrix
US6100114Aug 10, 1998Aug 8, 2000International Business Machines CorporationEncapsulation of solder bumps and solder connections
US6121689Jul 21, 1998Sep 19, 2000Miguel Albert CapoteSemiconductor flip-chip package and method for the fabrication thereof
US6130473Apr 2, 1998Oct 10, 2000National Semiconductor CorporationLead frame chip scale package
US6171887May 4, 1999Jan 9, 2001Kabushiki Kaisha ToshibaSemiconductor device for a face down bonding to a mounting substrate and a method of manufacturing the same
US6190940Jan 21, 1999Feb 20, 2001Lucent Technologies Inc.Flip chip assembly of semiconductor IC chips
US6228678Mar 10, 1999May 8, 2001Fry's Metals, Inc.Flip chip with integrated mask and underfill
US6245595Jul 22, 1999Jun 12, 2001National Semiconductor CorporationTechniques for wafer level molding of underfill encapsulant
US6258626Jul 6, 2000Jul 10, 2001Advanced Semiconductor Engineering, Inc.Method of making stacked chip package
US6288444Jun 4, 1999Sep 11, 2001Fujitsu LimitedSemiconductor device and method of producing the same
US6297560Aug 21, 1998Oct 2, 2001Miguel Albert CapoteSemiconductor flip-chip assembly with pre-applied encapsulating layers
US6307269Jul 10, 1998Oct 23, 2001Hitachi, Ltd.Semiconductor device with chip size package
US6316528Jan 16, 1998Nov 13, 2001Loctite (R&D) LimitedThermosetting resin compositions
US6327158 *Jan 15, 1999Dec 4, 2001National Semiconductor CorporationMetal pads for electrical probe testing on wafer with bump interconnects
US6346296Sep 14, 1999Feb 12, 2002Alliedsignal Inc.Highly stable packaging substrates
US6352881Jul 22, 1999Mar 5, 2002National Semiconductor CorporationMethod and apparatus for forming an underfill adhesive layer
US6358627Jan 23, 2001Mar 19, 2002International Business Machines CorporationRolling ball connector
US6372547Mar 11, 1998Apr 16, 2002Matsushita Electric Industrial Co., Ltd.Method for manufacturing electronic device with resin layer between chip carrier and circuit wiring board
US6391683Jun 21, 2000May 21, 2002Siliconware Precision Industries Co., Ltd.Flip-chip semiconductor package structure and process for fabricating the same
US6429238Jun 9, 2000Aug 6, 2002Shin-Etsu Chemical Co., Ltd.Flip-chip type semiconductor device sealing material and flip-chip type semiconductor device
US6455920Sep 25, 1998Sep 24, 2002Fujitsu LimitedSemiconductor device having a ball grid array and a fabrication process thereof
US6468832Jul 19, 2000Oct 22, 2002National Semiconductor CorporationMethod to encapsulate bumped integrated circuit to create chip scale package
US6479308 *Dec 27, 2001Nov 12, 2002Formfactor, Inc.Semiconductor fuse covering
US6486562Jun 7, 2000Nov 26, 2002Nec CorporationCircuit device with bonding strength improved and method of manufacturing the same
US6507118Jul 14, 2000Jan 14, 20033M Innovative Properties CompanyMulti-metal layer circuit
US6605479Jul 27, 2001Aug 12, 2003Advanced Micro Devices, Inc.Method of using damaged areas of a wafer for process qualifications and experiments, and system for accomplishing same
US6649445Sep 11, 2002Nov 18, 2003Motorola, Inc.Wafer coating and singulation method
US6683379Jan 11, 2002Jan 27, 2004Matsushita Electric Industrial Co., Ltd.Semiconductor device with reinforcing resin layer
US6791194Jan 28, 2000Sep 14, 2004Hitachi, Ltd.Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US6818550Jul 11, 2002Nov 16, 2004Rohm Co., Ltd.Method of cutting a wafer into individual chips
US6822324Jan 28, 2003Nov 23, 2004Advanced Semiconductor Engineering, Inc.Wafer-level package with a cavity and fabricating method thereof
US20020003299Mar 11, 1998Jan 10, 2002Yoshifumi NakamuraChip carrier and method of manufacturing and mounting the same
US20020014703Aug 20, 2001Feb 7, 2002Capote Miguel A.Semiconductor flip-chip package and method for the fabrication thereof
US20020027257Jul 27, 2001Mar 7, 2002Kinsman Larry D.Method for fabricating a chip scale package using wafer level processing and devices resulting therefrom
US20020031868Sep 7, 2001Mar 14, 2002Capote Miguel AlbertSemiconductor flip-chip package and method for the fabrication thereof
US20020109228Feb 13, 2001Aug 15, 2002Buchwalter Stephen L.Bilayer wafer-level underfill
US20020171152May 20, 2002Nov 21, 2002Nec CorporationFlip-chip-type semiconductor device and manufacturing method thereof
US20030001283Jun 29, 2001Jan 2, 2003Takashi KumamotoMulti-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies
US20030013233Jul 11, 2002Jan 16, 2003Kazutaka ShibataSemiconductor device and method for manufacturing the same
US20030080360 *Oct 28, 2002May 1, 2003Samsung Electronics Co., Ltd.Wafer treatment method for protecting fuse box of semiconductor chip
US20030087475Nov 8, 2001May 8, 2003Terry SterrettMethod and apparatus for improving an integrated circuit device
US20030099767Dec 24, 2002May 29, 2003Jen-Kuang FangBumping process for chip scale packaging
US20030127502 *Dec 10, 2002Jul 10, 2003Alvarez Romeo Emmanuel P.Method for forming a wafer level chip scale package, and package formed thereby
US20030129789Jan 29, 2003Jul 10, 2003Smith John W.Method of assembling a semiconductor chip package
US20030169064 *Jan 15, 2003Sep 11, 2003Pirkle Rex W.Selective trim and wafer testing of integrated circuits
US20030193096Jan 28, 2003Oct 16, 2003Advanced Semiconductor Engineering, Inc.Wafer-level package with a cavity and fabricating method thereof
US20030218258May 20, 2003Nov 27, 20033M Innovative Properties CompanyNanoparticle filled underfill
US20040002181Apr 2, 2003Jan 1, 2004Scheifers Steven M.Microelectronic assembly with die support and method
US20050212142Apr 28, 2005Sep 29, 2005Chuichi MiyazakiSemiconductor device and manufacturing metthod thereof
US20050516331 Title not available
Non-Patent Citations
Reference
1"Polymer Collar WLP(TM), Wafer Level Package Family", (C) 2002, downloaded from www.kns.com/prodserv/PDFS/FCD/polymer<SUB>-</SUB>collar.pdf, 2 pages.
2"Presenting Polymer Collar WLP(TM)-A New Wafer Level Package for Improved Solder Joint Reliability", (C) 2002, downloaded from www.kns.com/prodserv/flipchip/pdf/PC<SUB>-</SUB>ad.pdf, 1 page.
3Barrett et al., Kulicke & Soffa, "Polymer Collar WLP(TM)-A New Wafer Level Package for Improved Solder Joint Reliability", (C) 2002, downloaded from www.kns.com/resources/articles/PolymerCollar.pdf, 9 pages.
4Bogatin, Eric, "All Dressed Up and Nowhere to Go"; Semiconductor International, May 1, 2002, downloaded Dec. 23, 2003, from www.reed-electronics.com/semiconductor/index.asp?layout=article@articleid=CA213812@rid=0&rme=0&cfd=1, 2 pages.
5Kulicke & Soffa, Flip Chip Division, Polymer Collar(TM) Wafer Level Package, "See the Polymer Collar(TM) WLP Difference!", Dec. 7, 2001, www.kns.com.
6Kulicke & Soffa, Flip Chip Division, Polymer Collar(TM) Wafer Level Package; "Achieve Maximum Reliability for Wafer Level Packages!", Dec. 7, 2001, www.kns.com.
7Lau et al., "Chip Scale Package: Design, Materials, Process, Reliability, and Applications," Feb. 28, 1999, McGraw-Hill Professional Publishing; Chapter 1, pp. 1-41.
8Nguyen et al., "Effect of Underfill Fillet Configuration on Flip Chip Package Reliability", SEMI(R) Technology Symposium: International Electronics Manufacturing Technology (IEMT) Symposium, SEMICON(R) West 2002.
9Rao R. Turnmala, "Fundamentals of Microsystem Packaging," May 8, 2001, McGraw-Hill Professional Publishing; Chapters 2, 10 and 17.
10U.S. Appl. No. 10/080,913, filed Feb. 21, 2002.
11U.S. Appl. No. 10/224,291, filed Aug. 19, 2002.
12U.S. Appl. No. 10/707,208, filed Nov. 26, 2003.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7838991 *Feb 5, 2007Nov 23, 2010National Semiconductor CorporationMetallurgy for copper plated wafers
US8568961Nov 25, 2009Oct 29, 2013Lord CorporationMethods for protecting a die surface with photocurable materials
Classifications
U.S. Classification438/15, 257/E21.531
International ClassificationG01R31/26, H01L21/66
Cooperative ClassificationH01L2224/05572, H01L22/14, H01L2924/014
European ClassificationH01L22/14
Legal Events
DateCodeEventDescription
Apr 18, 2011FPAYFee payment
Year of fee payment: 4
Apr 14, 2004ASAssignment
Owner name: NATIONAL SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KELKAR, NIKHIL VISHWANATH;REEL/FRAME:015228/0696
Effective date: 20040405