|Publication number||US7292069 B2|
|Application number||US 11/323,950|
|Publication date||Nov 6, 2007|
|Filing date||Dec 30, 2005|
|Priority date||Dec 30, 2005|
|Also published as||CN101351965A, EP1966893A1, US20070194810, WO2007078840A1|
|Publication number||11323950, 323950, US 7292069 B2, US 7292069B2, US-B2-7292069, US7292069 B2, US7292069B2|
|Inventors||Eric C. Hannah, David Tennenhouse|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Non-Patent Citations (2), Referenced by (17), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Embodiments of the present invention relate to analog circuits, and in particular, to analog sub-threshold CMOS circuits.
High performance microprocessors utilize CMOS process technology. Historically, as CMOS (Complementary Metal Oxide Semiconductor) technology scales to smaller sizes, the energy expended per logic operation decreases, but this decrease slows down as the technology scales below 100 nanometers. In digital logic, the ratio of ON-current (ION) to OFF-current (IOFF) for a transistor is important, where for CMOS logic, ION for a transistor denotes the source-drain current when ON and IOFF denotes the source-drain current when OFF. Unfortunately, this ratio decreases as scaling decreases. This is due to transistors becoming leaky as the technology scales to smaller and smaller sizes. That is, transistors do not actually turn OFF, and the corresponding leakage current is somewhat substantial. Furthermore, as technology scales to smaller dimensions, various transistor characteristics become highly variable, such as threshold voltage, delay, and so forth. In particular, as technology scales below 0.18 microns, the expended power due to leakage, as a percentage of total power consumed, may rise substantially.
Accordingly, it is expected that as technology scales to smaller dimensions, other types of circuit technologies may be needed so that expended power does not become an issue. In this regard, sub-threshold CMOS circuits have been of interest to researchers because in some cases they may be designed as so-called ultra low power circuits. However, in the past, such sub-threshold CMOS circuits have been inadequate for high performance applications.
Low power sub-threshold CMOS circuits may be viable candidates for high performance systems as process technology scales well below 100 nanometers.
When a CMOS transistor is operating in a sub-threshold region, its drain-to-source current is relatively very small, such as on the order of a few nano-amps. When a transistor is operating in the sub-threshold region, it is said to be in weak inversion. A NMOS transistor is in its sub-threshold region if its gate-to-source voltage VGS is less than its threshold voltage, denoted as VTN. That is, VGS<VTN. For a pMOS transistor, if we follow the convention that its threshold voltage, denoted as VTP, is negative, then a pMOS transistor is in its sub-threshold region if its gate-to-source voltage is larger than VTP. That is, VGS>VTP. Operating CMOS circuits in their sub-threshold regions may bring about a significant reduction in power, but also a reduction in performance because the switching times increase. However, if sub-threshold CMOS circuits are designed properly, there is an overall reduction in power consumed per performance metric. We shall discuss two types of circuits employing sub-threshold CMOS transistors. The first type of circuit discussed will be sub-threshold current-mode logic, and the second type of circuits discussed will be sub-threshold circuits used in soft-gates. We first begin the discussion with current-mode logic.
The particular logic gate shown in
When in operation, there is always a static bias current steered through some of the transistors, depending upon the input logic levels. The static bias current is set by the nMOS transistor Q1. If the input voltage to input port B is high, then the static bias current is steered through transistors Q2 and Q4 and to ground via transistor Q1. Now, suppose that the input voltage B is LOW so that its complementary voltage
The presence of pMOS transistors Q2 and Q3 reduces the overall voltage swings at the output ports. Very high speed operation may be possible because in a sense the logic gate is always ON; all that is changed is the path through which the bias supply current is steered. Because of the differential output, power supply noise and ground noise are coupled to the output signals as a common-mode signal, which may be cancelled out from the differential output voltage. However, there is a relatively high static power dissipation due to the high bias current and supply voltage. Note that the bias voltage supplied to the gate of transistor Q1 may be taken LOW to turn the entire logic gate OFF if the logic gate is not being used.
We see that the way in which the currents are steered is similar to the previous logic gate discussed in
Maintaining a controlled differential output voltage swing is important for correct operation of current-mode logic gates. If the output voltage swing is too high, for example, then gate delay may be unnecessarily too large. On the other hand, if the output voltage swing is too low, then the logic “gain” is less than one, in which case the gate delay of any following stage may be increased.
A sub-threshold CMOS logic gate employing current-mode logic may be abstractly represented as in
The output port voltages from output ports 404 and 406 are provided to interface block 416. Interface block 416 thresholds the output voltages so that they are restored to their full logic values. These full logic voltages may drive other current-mode logic gates, represented by block 418. Voltage swing controller 402 monitors the voltages applied to interface block 416 and applies bias voltages to active loads 412 and 414 so as to maintain the proper differential output voltage.
Current mode logic gates for high speed operation are traditionally implemented using nMOS transistors as steering devices with resistive loads. Implementing cascaded complementary current-mode logic gates may enhance operation at low supply voltages.
We now turn the discussion to soft-gates using sub-threshold CMOS circuits. A soft-gate is a logical device for passing probabilities. They are useful for implementing Bayesian networks. Bayesian networks are graphical models that map together existing beliefs about the relationships between events, and provide a mathematical rule explaining how to change those beliefs in light of new evidence. Such networks may find application to computationally demanding decision-making applications such as expert systems, decoding turbo codes, and other decision and communication problems.
Consider a simple soft-gate relating three Boolean variables: x, y, and z. Associated with each of these variables is a probability function. For example, we have for x a probability that it is either equal to one or zero. Similar statements apply to other variables. We denote these probability functions for x, y, and z as px(x), py(y), and pz(z), respectively. The variables x, y, and z are related to each other by some Boolean relationship. This Boolean relationship may be represented by the function f(x, y, z), where f=1 when x, y, and z satisfy the Boolean relationship and f=0 otherwise. Using f(x, y, z), the probability functions are related by
where γ is a normalization constant so that pz(0)+pz(1)=1. The above expression gives a method for computing the probability function of z given the probability functions for the variables y, and z.
As an example, consider the exclusive-OR gate z=x⊕y, where ⊕ is the exclusive-OR operator. That is, z=1 if and only if x #y. The function f(x, y, z) for representing this Boolean relationship may be expressed as
where δ(TRUE)=1 and δ(FALSE)=1.
Using the expression in Eq. (2) for the function f(x, y, z) in Eq. (1), one easily obtains the probabilities for the variable z:
p z(1)=p x(0)p y(1)+p x(1)p y(0), (3)
p z(0)=p x(0)p y(0)+p x(1)p y(1). (3)
The soft exclusive-OR gate may be represented by the factor graph shown in
As another example of a factor graph, an inverter soft-gate is shown in
A more complicated soft-gate may be represented using simpler soft-gates as building blocks. For example,
Bayesian networks are useful because they can model expert knowledge systems. Bayesian networks may be represented as factor graphs, but in practice such factor graphs may be relatively complicated, and calculating the marginal probabilities may be somewhat difficult. An algorithm called a sum-product algorithm has been developed for the efficient calculation of marginal probabilities associated with factor graphs. We do not need to discuss this algorithm in this description. The algorithm may be found in various references related to factor graphs. See for example “Factor Graphs and the Sum-Product Algorithm”, F. R. Kschischang, et al., IEEE Transactions on Information Theory, Vol. 47, no. 2, February 2001.
As its names implies, the sum-product algorithm involves forming sums and products. As a simple example, considering the exclusive-OR soft-gate in Eq. (3). We see that the marginal probability for the variable z in terms of the marginal probabilities for the variables x and y involve products and sums. These operations may be performed in analog circuits, and sub-threshold circuits may be utilized to perform these computations. Sums are very easy to synthesize for we only need make use of Kirchhoff's Current Law in which the sum of currents into a node must sum to zero. So to perform an addition operation, we need only short one wire to another. Performing a product or a multiplication is of course more difficult, but sub-threshold CMOS circuits may be used for such operations.
Suppose we have two quantities, a and b, that we wish to multiply to form a third quantity, c. This multiplication could be accomplished by taking the logarithm of a and adding to that the logarithm of b. This sum of logarithms is merely the logarithm of c, so to find c, we merely take the antilog of that expression. That is, as is well known, for c=ab, we have ln(c)=ln(a)+ln(b). Sub-threshold circuits synthesizing the exponential function and the log function may be utilized to synthesize the product operation.
It has been well known for some time that bipolar junction transistor circuits may be synthesized to perform the exponential operation, and that diode-connected transistors may be used for the logarithm operation. See, for example, “A precise Four-Quadrant Multiplier with Subnanonsecond Response,” B. Gilbert, IEEE Journal on Solid State Circuits, Vol. 3, Issue 4, 1968, pp. 365-373. It is also well known that these functions may also be synthesized using sub-threshold CMOS transistors. See for example, “Analog VLSI and Neural Systems”, Carver Mead, Addison-Wesley, 1989, and a more recent discussion by Samuel Luckenbill in http://www.eng.vale.edu/pik/EESrProi O2/Luckenbill html/node5.htmlas.
For sub-threshold NMOS transistor operating in its saturation mode so that changes in the source-drain voltage do not affect the drain-source current, the source-drain current is given by the expression
I=I S exp(V GS /V T), (4)
where VGS is the gate-to-source voltage and IS is a saturation current. A diode connected sub-threshold CMOS transistor is usually in saturation, so that Eq. (4) would apply. Solving for the gate-source voltage in Eq. (4), one obtains
V GS =V T ln(I/I 0), (5)
and we see that the gate-to-source voltage is proportional to the logarithm of the ratio of the source drain current I to the saturation current IS. So, generally speaking, we see from Eq. (5) that a diode-connected sub-threshold transistor gives a voltage as a logarithm of a current. To synthesize a multiplier, we also need a circuit that takes the exponential of a voltage and outputs of current. This exponential function can be synthesized by a differential pair of transistors.
A differential pair is illustrated is in
I 1 +I 2 =I B, (6)
where these currents are given by
I 1 =I S exp[(V 1 −V)/V T]
I 2 =I S exp[(V 2 −V)/V T]′ (7)
where V denotes the voltage at the node labeled “V” in Fig. K. As shown in Luckenbill, cited above, Eqs. (6) and (7) may be manipulated to yield Eqs. (8) and (9) below:
The above two equations look like they perform the exponential function as desired, except perhaps for the terms appearing in their denominators. But these terms in the denominators may be eliminated by combining a differential pair with three diode-connected transistors connected as current mirrors. This is illustrated in the circuit of
If now the following expression holds:
I N1 +I N2=1, (13)
then from Eqs. (10) and (12) we obtain the results:
I 1 =I NB I N1, (14)
I 2 =I NB I N2. (15)
The above two equations show that the circuit of
As an example, a sub-threshold circuit for synthesizing an exclusive-OR soft-gate is given in
We see that sub-threshold transistors have many advantages. Sub-threshold transistors employed in current-mode logic circuits may achieve very low power dissipation and may be used to synthesize conventional Boolean logic gates. Sub-threshold transistors may also be utilized to perform products which may be used to implement soft-gates with applications to Bayesian networks. Despite these advantages, analog circuits have their own scaling limits. Analog circuits are generally not fully modular, so that redesign of one part often requires redesign of all the other parts. Analog circuits are not easily scalable because a new process technology may change enough parameters of some parts of the circuit so that a full re-design is needed. By contrast, digital circuits are modular, so that re-design for a new process technology may be as simple as re-designing a few logic gates.
This design problem may be overcome by utilizing configurable logic blocks. Gate arrays pioneered the idea of using reconfigurable logic blocks between clocked registers to form flexible digital circuits. Within such a block, there is a free propagation of signals between logic elements that compute a desired Boolean expression. The exact Boolean expression computed is set by storing programming bits inside each configurable logic block at power start time or by programming switches in some initialization procedure. Clock synchronization inside the chip occurs via register transfer operations on the edges of each configurable logic block on the clock transitions.
In an embodiment illustrated in
It is expected that the approach illustrated in
The resulting input-output soft-gate function for the configurable logic block of
Clocked registers 1508 and 1510 may be clocked by two clock signals, indicated in
Note that in the above description regarding the currents IW1 and IW2, we have assumed that they sum up to one. This assumption is also applied to the other currents that represent the various probabilities and their complements. However, this assumption is maintained merely for simplicity of discussion, and ignores the units used to represent currents. In practice, one need only require that the various currents and their complements sum to some fixed number. A final scaling may then be performed for each configurable logic block, where this scaling may be absorbed within the functionality of the clocked registers.
Functional unit 1502 may be synthesized in various ways. For example, fuses, or anti-fuses, may be “blown” (programmed) to provide the desired currents so that the variable node w to its desired level.
It should be appreciated that
The output of soft-gate 1604 is a set of currents, again representing probabilities. Interface circuit 1610 is coupled to output clocked register 1612 so that the state of clocked register 1612 is updated when it is clocked to represent this set of output currents. The resulting output bits stored in clocked register 16112 may then be provided as input to other configurable logic blocks.
Configurable logic blocks may find use in various systems, such as illustrated in
Configurable logic blocks may also include sub-threshold, current mode logic circuits.
Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below.
It is to be understood in these letters patent that the meaning of “A is connected to B”, where A or B may be, for example, a node or device terminal, is that A and B are connected to each other so that the voltage potentials of A and B are substantially equal to each other. For example, A and B may be connected by way of an interconnect, transmission line, etc. In integrated circuit technology, the “interconnect” may be exceedingly short, comparable to the device dimension itself. For example, the gates of two transistors may be connected to each other by polysilicon or copper interconnect that is comparable to the gate length of the transistors. As another example, A and B may be connected to each other by a switch, such as a transmission gate, so that their respective voltage potentials are substantially equal to each other when the switch is ON.
It is also to be understood that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements. For example, A may be connected to a circuit element which in turn is connected to B.
It is also to be understood in these letters patent that a “current source” may mean either a current source or a current sink. Similar remarks apply to similar phrases, such as, “to source current”.
It is also to be understood in these letters patent that various circuit blocks, such as current mirrors, amplifiers, etc., may include switches so as to be switched in or out of a larger circuit, and yet such circuit blocks may still be considered connected to the larger circuit because the various switches may be considered as included in the circuit block.
Throughout the description of the embodiments, various mathematical relationships are used to describe relationships among one or more quantities. For example, a mathematical relationship may express a relationship by which a quantity is derived from one or more other quantities by way of various mathematical operations, such as addition, subtraction, multiplication, division, etc. More simply, a quantity may be set to some known value, such as a real number, which is merely a trivial mathematical relationship. These numerical relationships are in practice not satisfied exactly, and should therefore be interpreted as “designed for” relationships. That is, one of ordinary skill in the art may design various working embodiments to satisfy various mathematical relationships, but these relationships can only be met within the tolerances of the technology available to the practitioner. In the following claims, the word “substantially” is used to reflect this fact. For example, a claim may recite that one resistance is substantially equal to another resistance, or that one voltage is substantially equal to another voltage. Or, a claim may relate one quantity to one or more other quantities by way of stating that these quantities substantially satisfy or are substantially given by a mathematical relationship or equation. It is to be understood that “substantially” is a term of art, and is meant to convey the principle discussed above that mathematical relationships, equalities, and the like, cannot be met with exactness, but only within the tolerances of the technology available to a practitioner of the art under discussion.
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|U.S. Classification||326/115, 326/104, 326/37, 326/127|
|International Classification||H03K19/094, H03K19/20|
|Cooperative Classification||H03K19/094, H03K19/0813|
|European Classification||H03K19/094, H03K19/08L|
|Dec 30, 2005||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HANNAH, ERIC C.;REEL/FRAME:017420/0290
Effective date: 20051228
|Jul 13, 2006||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TENNENHOUSE, DAVID;REEL/FRAME:017940/0226
Effective date: 20060616
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