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Publication numberUS7294556 B2
Publication typeGrant
Application numberUS 11/031,696
Publication dateNov 13, 2007
Filing dateJan 7, 2005
Priority dateJul 7, 2003
Fee statusPaid
Also published asCN1860251A, CN100537839C, DE602004016659D1, EP1641958A2, EP1641958B1, US7125815, US7790632, US20050009368, US20050124171, US20070161260, WO2005008746A2, WO2005008746A3
Publication number031696, 11031696, US 7294556 B2, US 7294556B2, US-B2-7294556, US7294556 B2, US7294556B2
InventorsBrian A. Vaartstra
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of forming trench isolation in the fabrication of integrated circuitry
US 7294556 B2
Abstract
This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.
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Claims(21)
1. A method of forming trench isolation in the fabrication of integrated circuitry, comprising:
forming a masking layer over a semiconductor substrate;
etching isolation trenches through the masking layer into semiconductive material of the semiconductor substrate; and
after etching the isolation trenches, introducing first and second vapor phase reactants in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles effective to deposit a phosphorus doped silicon dioxide-comprising layer within the isolation trenches, one of the first and second vapor phase reactants being PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants being Si(OR)3OH where R is hydrocarbyl.
2. The method of claim 1 wherein the deposit is effective to fill the isoiation trenches.
3. The method of claim 1 wherein the deposit does not fill the isolation trenches.
4. The method of claim 1 wherein the deposition cycles are effective to deposit the phosphorus doped silicon dioxide-comprising layer on the masking layer.
5. The method of claim 1 wherein the deposition cycles are not effective to selectively deposit the phosphorus doped silicon dioxide-comprising layer within the isolation trenches.
6. The method of claim 1 wherein the deposition cycles are effective to form the silicon dioxide-comprising layer to have no more than 0.5 atomic percent phosphorus.
7. The method of claim 1 wherein the deposition cycles are effective to form the silicon dioxide-comprising layer to have at least 1.0 atomic percent phosphorus.
8. The method of claim 1 being void of introducing any vapor phase reactant to the chamber other than said first and second vapor phase reactants in said forming of the phosphorus doped silicon dioxide-comprising layer.
9. The method of claim 1 comprising introducing another vapor phase reactant different from the first and second vapor phase reactants intermediate at least some of said separated pulses of the first and second vapor phase reactants.
10. The method of claim 9 wherein the another vapor phase reactant is oxygen-containing.
11. The method of claim 10 wherein the another vapor phase reactant comprises O3.
12. The method of claim 9 wherein the another vapor phase reactant is boron-containing, the phosphorus doped silicon dioxide-comprising layer comprising boron.
13. The method of claim 1 wherein the PO(OR)3 comprises triethyl phosphate.
14. The method of claim 1 wherein the Si(OR)3OH comprises tris(tert-butoxy)silanol.
15. The method of claim 1 wherein the PO(OR)3 comprises triethyl phosphate and wherein the Si(OR)3OH comprises tris(tert-butoxy)silanol.
16. The method of claim 1 comprising purging the chamber with an inert gas intermediate the separated pulses.
17. The method of claim 1 being void of aluminum on the substrate in said forming of the phosphorus doped silicon dioxide-comprising layer.
18. The method of claim 1 being void of introducing any vapor phase aluminum-containing reactant to the chamber in said forming of the phosphorus doped silicon dioxide-comprising layer.
19. The method of claim 1 wherein the deposition cycles comprise atomic layer deposition.
20. The method of claim 1 wherein the deposition cycles comprise plasma generation of at least one of the first and second reactants.
21. The method of claim 1 wherein the deposition cycles are void of plasma generation of the first and second reactants.
Description
RELATED PATENT DATA

This patent resulted from a divisional application of U.S. patent application Ser. No. 10/615,051, filed Jul. 7, 2003, now U.S. Pat. No. 7,125,815 entitled “Methods of Forming a Phosphorus Doped Silicon Dioxide Comprising Layers”, naming Brian A. Vaartstra as inventor, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

This invention relates to methods of forming phosphorus doped silicon dioxide comprising layers, and to methods of forming trench isolation in the fabrication of integrated circuitry.

BACKGROUND OF THE INVENTION

One commonly used material in the fabrication of integrated circuitry is silicon dioxide. Such might be utilized as essentially 100% pure, or in combination with other materials, including property-modifying dopants. Accordingly, silicon dioxide might be utilized as a mixture with other materials in forming a layer or layers and may or may not constitute a majority of the given layer. Exemplary materials are borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and borosilicate glass (BSG). Typically, such materials have anywhere from 1% to 4% atomic concentration of each of boron and/or phosphorus atoms, although atomic percent concentrations in excess of 5% have also been used.

As semiconductor devices continue to shrink geometrically, such has had a tendency to result in greater shrinkage in the horizontal dimension than in the vertical dimension. In some instances, the vertical dimension increases. Regardless, increased aspect ratios (height to width) of the devices result, making it increasingly important to develop processes that enable dielectric and other materials to fill high aspect or increasing aspect ratio trenches, vias and other steps or structures. A typical dielectric material of choice has been doped and/or undoped silicon dioxide comprising materials, for example those described above. Dopants such as boron and phosphorus can facilitate a reflowing of the deposited layer at a higher temperature to facilitate more completely filling openings on a substrate. Various reactant precursors can be utilized in forming silicon dioxide layers, for example the silanols disclosed in U.S. Pat. No. 6,300,219.

SUMMARY OF THE INVENTION

This invention includes methods of forming phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.

In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. A first species is chemisorbed to a surface of the substrate to form a first species monolayer onto the surface within the chamber from a first vapor phase reactant comprising PO(OR)3, where R is hydrocarbyl. The chemisorbed first species is contacted with a second vapor phase reactant comprising Si(OR)3OH, where R is hydrocarbyl, to form a monolayer comprising Si and O. Chemisorbing with the first species and contacting the chemisorbed first species with the second reactant are successively repeated under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate.

Other aspects and implementations are contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.

FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.

FIG. 3 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 2.

FIG. 4 is a diagrammatic sectional view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.

FIG. 5 is a view of the FIG. 4 wafer fragment at a processing step subsequent to that shown by FIG. 4.

FIG. 6 is a view of the FIG. 5 wafer fragment at a processing step subsequent to that shown by FIG. 5.

FIG. 7 is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate to be deposited upon within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3, where R is hydrocarbyl. An other of the first and second vapor phase reactants is Si(OR)3OH, where R is hydrocarbyl. Such might be conducted by atomic layer deposition (ALD) methods (for example including chemisorbing and contacting methods), by chemical vapor deposition (CVD) methods, and by other methods, as well as by combinations of these and other methods. CVD and ALD are used herein as referred to in the co-pending U.S. patent application Ser. No. 10/133,947, filed on Apr. 25, 2002, entitled “Atomic Layer Deposition Methods and Chemical Vapor Deposition Methods”, and listing Brian A. Vaartstra as the inventor, which is now U.S. Publication No. 2003-0200917. This U.S. Publication No. 2003-0200917, filed on Apr. 25, 2002 is hereby fully incorporated by reference as if presented in its entirety herein. Preferred and understood reduction-to-practice examples provided herein are understood to be primarily by atomic layer deposition.

The R hydrocarbyl of the PO(OR)3 and the R hydrocarbyl of the Si(OR)3OH may be the same or different, and regardless in one preferred embodiment the R hydrocarbyl of each contains only from one to five carbon atoms. One preferred and reduction-to-practice PO(OR)3 material comprises triethyl phosphate. One preferred exemplary and reduction-to-practice Si(OR)3OH material comprises tristertbutylsilanol. Exemplary preferred conditions comprise a temperature of from about 50° C. to about 500° C., and more preferably at from about 100° C. to about 300° C. Exemplary pressure conditions are subatmospheric, preferably being from about 10−7 Torr to about 10 Torr, and more preferably from about 10−4 Torr to about 1 Torr. The conditions might comprise plasma generation of at least one of the first and second reactants, or be void of plasma generation of the first and second reactants. If plasma generation is utilized, such might occur within the chamber of deposition, and/or externally thereof. Most preferred are believed to be conditions which are void of plasma generation of the first and second reactants.

The conditions might be effective to form the silicon dioxide comprising layer to have very low phosphorus content, for example to have no more than 0.5 atomic percent phosphorus, including lesser amounts. Alternately, the conditions might be effective to form the silicon dioxide comprising layer to have at least 1.0 atomic percent phosphorus including, for example, 5.0 and greater atomic percent phosphorus.

The method might be void of introducing any vapor phase reactant to the chamber other than the first and second vapor phase reactants in the forming of the phosphorus doped silicon dioxide comprising layer. Alternately, the method might include introducing another vapor phase reactant, different from the first and second vapor phase reactants, intermediate at least some of the separated pulses of the first and second vapor phase reactants. By way of example only, an exemplary another vapor phase reactant is oxygen containing, for example O2, O3 and/or any vapor phase oxygen containing compound. Ozone pulses, for example as a mixture of O2 and O3, in addition to the PO(OR)3 flows have been determined to facilitate greater phosphorus incorporation, for example above 5 atomic percent, if such is desired.

Another exemplary vapor phase reactant would be boron containing, and whereby the phosphorus doped silicon dioxide comprising layer would also then comprise boron, for example in fabricating a BPSG or BPSG-like material. An exemplary boron containing material reactant is B(OR)3.

The alternate and temporally separated pulses might include one or a combination of chamber pump down and/or purging of the chamber with an inert gas (i.e., N2 and/or any noble gas) intermediate the separated pulses to remove unreacted precursor/reactant.

One prior art technique of forming a silicon dioxide comprising layer is described in Hausmann et al., Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates, SCIENCE MAGAZINE, Vol. 298, pp. 402–406 (2002). Such a process initially utilizes a methylaluminum reactant precursor, for example triethyl aluminum or aluminum dimethylamide, which forms an initial aluminum containing layer on the substrate. An alkoxysilanol, for example tris(tert-butoxy)silanol, is thereafter flowed to the substrate. Apparently, the aluminum presence provides a self-limited catalytic reaction whereby a silicon dioxide comprising layer deposits to some self-limiting thickness anywhere from 100 Angstroms to 700 Angstroms. In other words, continued exposure to the alkoxysilanol does not result in continuing growth of the silicon dioxide comprising layer. Apparently, the silicon dioxide layer self-limited growth occurs in some catalytic manner, as opposed to a simple ALD-like manner due to significantly more than a few monolayers being formed by the silanol exposure/pulsing. Regardless, aluminum is incorporated in the resultant layer, which may not be desired.

While the invention disclosed herein does not preclude its use with the Hausmann et al.-like process, most preferably the inventive process is void of introducing any vapor phase aluminum containing reactant to the chamber in the forming of the phosphorus doped silicon dioxide comprising layer. Further preferably in accordance with the invention, the substrate is void of aluminum in the forming of the phosphorus doped silicon dioxide comprising layer.

In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes at least some ALD processing. By way of example only, an exemplary such process is described with reference to FIGS. 1–3. Referring to FIG. 1, a substrate 10 is positioned within any suitable deposition chamber (not shown). In one exemplary embodiment, substrate 10 is a semiconductor substrate, for example comprising some material 12 which preferably includes at least some semiconductive material, and may, of course, include multiple materials and layers. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Substrate 10 has a surface 14 which is provided to be hydroxylated (having pending OH groups) as shown. Other surface termination is also contemplated to be effective in the process herein described. If hydroxylated, such surface might by hydroxylated prior to provision within the deposition chamber, or hydroxylated within the deposition chamber. An exemplary technique for hydroxylating surface 14 includes exposure of the surface to water vapor. Further, the surface might be naturally hydroxylated simply from exposure to ambient atmosphere.

Referring to FIG. 2, a first species is chemisorbed to form a first species monolayer 16 onto the hydroxylated surface within the chamber from a first vapor phase reactant comprising PO(OR)3, where R is hydrocarbyl, for example as described above. Such is depicted as being comprised of a variable “A” as constituting at least a part of layer 16 in FIG. 2. Preferred conditions and other attributes are as described above with respect to the first described implementation.

Referring to FIG. 3, the chemisorbed first species has been contacted with a second vapor phase reactant comprising Si(OR)3OH, where R is hydrocarbyl, to form a monolayer 18 which will comprise Si and O. Again, conditions are preferably as described above with respect to the first implementation. FIG. 3 depicts layer 18 as comprising a variable “B”, with the chemisorbed first species monolayer being depicted as A′ exemplary of some modification of the A species in the chemisorbing of B with A, with the exact preferred and typical species A and B not having been determined. Regardless, chemisorbing with the first species and contacting the chemisorbed first species with the second reactant is successively repeated under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. Typically and preferably, such chemisorbings and contactings are conducted in alternate and temporally separated pulses to the substrate, for example as described above in the first described implementation.

The immediately above-described implementation was relative to the chemisorbing of a surface with PO(OR)3 followed by a second vapor phase reactant exposure comprising Si(OR)3OH, and by which an aspect of the invention was reduced-to-practice, although aspects of the invention are not necessarily so limited.

Regardless, aspects of the invention might preferably be utilized in methods of forming trench isolation in the fabrication of integrated circuitry, for example as shown and described with reference to FIGS. 4–7. FIG. 4 shows a semiconductor substrate 26 comprising a bulk monocrystalline silicon or other semiconductive material substrate 28. A masking layer 30 is formed over semiconductor substrate 28. Such is depicted as comprising a pad oxide layer 32 and an overlying nitride comprising layer 34, for example silicon nitride.

Referring to FIG. 5, isolation trenches 36 and 38 have been etched through masking layer 30 into the semiconductive material of substrate 28/26. A thermal oxide layer or other layer, for example silicon nitride (not shown), might be provided now or subsequently, for example with respect to silicon dioxide by exposing substrate 26 to thermal oxidizing conditions.

Referring to FIG. 6, a phosphorus doped silicon dioxide comprising layer 40 has been formed within semiconductive material isolation trenches 36 and 38. Exemplary techniques for doing so include introducing first and second vapor phase reactants in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles, as described above, and also for example, by the chemisorbings and contacting methods as described above. As depicted, the depositing is effective to deposit phosphorus doped silicon dioxide comprising layer 40 onto masking layer 30, and also is depicted as not being effective to selectively deposit phosphorus doped silicon dioxide layer 40 within isolation trenches 36 and 38. In the context of this document, a “selective/selectively deposit” is one which deposits a material over one region of a substrate as compared to another at a deposition thickness ratio of at least 2:1.

The depositing might be effective to completely fill isolation trenches 36 and 38, or to not fill such isolation trenches for example as shown in FIG. 6. Deposition processing, for example as described in any of the above, could continue to completely fill such trenches, for example as shown in FIG. 7. Alternately by way of example only, the FIG. 6 construction could be filled with another material before or after removing the material from over masking layer 30.

An exemplary reduction-to-practice example utilized triethyl phosphate and tris(tert-butoxy)silanol as first and second respective vapor phase reactants. A 650 Angstrom conformal layer of PSG (8 atomic percent phosphorus) was deposited over a silicon nitride lined trench using respective two second reactive pulses of each reactant, with a one second argon purge followed by a three second pump down without flowing argon between the reactant pulses. This was conducted for 600 complete cycles at 300° C. No ozone was utilized. Respective bubbler/ampoule temperatures for feeding the triethyl phosphate and tris(tert-butoxy)silanol were 50° C. and 40° C.

Such processing was also conducted with the triethyl phosphate having a temperature of 60° C. and with tris(tert-butoxy)silanol at 70° C. One (1) second and 0.5 second respective pulses of such triethyl phosphate and of the tris(tert-butoxy)silanol yielded a 650 Angstrom film after 300 complete cycles, providing an approximate 2.2 Angstrom per cycle rate of deposition. This was somewhat higher than the first reduction-to-practice example deposition, which was at 1.1 Angstroms per cycle. The deposited film was substantially carbon-free, and the phosphorus content was below 0.5 atomic percent. Longer triethyl phosphate exposure at such reactant temperature is expected to yield higher growth rates and increase phosphorus content in the deposited film.

In another reduction-to-practice example, triethyl phosphate from a 60° C. bubbler/ampoule was fed to a substrate within a deposition chamber for one second. This was followed by the flow of 30 sccm Ar for one second, followed by three seconds of pumping down the chamber without flowing any gas thereto. Thereafter, 25 sccm of a combined stream of O2/O3 (5% to 12% O3 by volume) was flowed to the chamber for two seconds. This was followed by a 30 sccm flow of Ar for one second, followed by three seconds of pump down while feeding no gas to the chamber. Then, tris(tert-butoxy)silanol was flowed to the chamber from a 60° C. bubbler/ampoule for two seconds. This was followed by one second of Ar flow at 30 sccm, again followed by three seconds of pump down while no gas flowed to the chamber. This was conducted for 400 complete cycles, with pressure during all of the processing varying from 0.24 Torr to 10−6 Torr. Such resulted in a 1000 Angstrom thick layer having 5.7 atomic percent phosphorus incorporated therein.

In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3809574Jul 15, 1971May 7, 1974Rca CorpAluminum oxide films for electronic devices
US3990927Nov 15, 1974Nov 9, 1976Commissariat A L'energie AtomiqueMethod for isolating the components of an integrated circuit
US4474975May 9, 1983Oct 2, 1984The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationProcess for producing tris (N-methylamino) methylsilane
US5105253Dec 28, 1990Apr 14, 1992Synergy Semiconductor CorporationStructure for a substrate tap in a bipolar structure
US5156881Apr 16, 1991Oct 20, 1992Kabushiki Kaisha ToshibaMethod for forming a film on a substrate by activating a reactive gas
US5182221Jun 12, 1991Jan 26, 1993Sony CorporationOxidizing silicon compound to silicon dioxide
US5387539Jun 18, 1993Feb 7, 1995Hyundai Electronics Industries Co., Ltd.Method of manufacturing trench isolation
US5410176May 24, 1993Apr 25, 1995Sgs-Thomson Microelectronics, Inc.Integrated circuit with planarized shallow trench isolation
US5470798May 28, 1991Nov 28, 1995Mitel CorporationMoisture-free sog process
US5604149Mar 13, 1995Feb 18, 1997France TelecomMethod of and device for isolating active areas of a semiconducor substrate by quasi-plane shallow trenches
US5616513Jun 1, 1995Apr 1, 1997International Business Machines CorporationShallow trench isolation with self aligned PSG layer
US5702977Mar 3, 1997Dec 30, 1997Taiwan Semiconductor Manufacturing Company, Ltd.Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer
US5719085Sep 29, 1995Feb 17, 1998Intel CorporationEtching and oxidizing forms a birds beak to reduce current leakage
US5741740Jun 12, 1997Apr 21, 1998Taiwan Semiconductor Manufacturing Company, Ltd.Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer
US5770469Dec 29, 1995Jun 23, 1998Lam Research CorporationAlternately vapor depositing heavily doped and lightly doped glass layers over wafer substrate while reflowing layers in heated chemical reactor
US5776557Oct 10, 1996Jul 7, 1998Kabushiki Kaisha ToshibaMethod for forming a film on a substrate by activating a reactive gas
US5786039May 14, 1996Jul 28, 1998France TelecomDielectrics on conductive or semiconductor region, insulator oxides, tetraalkyl silicate and hydrogen peroxide, coverings and annealing
US5786263Apr 4, 1995Jul 28, 1998Motorola, Inc.Method for forming a trench isolation structure in an integrated circuit
US5801083Oct 20, 1997Sep 1, 1998Chartered Semiconductor Manufacturing, Ltd.Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners
US5863827Jun 3, 1997Jan 26, 1999Texas Instruments IncorporatedOxide deglaze before sidewall oxidation of mesa or trench
US5883006Dec 12, 1997Mar 16, 1999Kabushiki Kaisha ToshibaMethod for making a semiconductor device using a flowable oxide film
US5888880Oct 30, 1996Mar 30, 1999Advanced Micro Devices, Inc.Trench transistor with localized source/drain regions implanted through selectively grown oxide layer
US5895253Aug 22, 1997Apr 20, 1999Micron Technology, Inc.Trench isolation for CMOS devices
US5895255Jun 29, 1995Apr 20, 1999Kabushiki Kaisha ToshibaShallow trench isolation formation with deep trench cap
US5904540Dec 19, 1997May 18, 1999United Microelectronics, Corp.Method for manufacturing shallow trench isolation
US5923073Sep 17, 1997Jul 13, 1999Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device and semiconductor device manufactured according to the method
US5930645Dec 18, 1997Jul 27, 1999Advanced Micro Devices, Inc.Shallow trench isolation formation with reduced polish stop thickness
US5930646Oct 9, 1998Jul 27, 1999Chartered Semiconductor Manufacturing, Ltd.Conversion of polysilicon layer to novel second dielectric layer to compensate for stress caused by densification of first dielectric layer in shallow trench
US5943585Dec 19, 1997Aug 24, 1999Advanced Micro Devices, Inc.Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen
US5950094Feb 18, 1999Sep 7, 1999Taiwan Semiconductor Manufacturing Company, Ltd.Method for fabricating fully dielectric isolated silicon (FDIS)
US5960299Oct 28, 1998Sep 28, 1999United Microelectronics Corp.Method of fabricating a shallow-trench isolation structure in integrated circuit
US5972773Jun 5, 1997Oct 26, 1999Advanced Micro Devices, Inc.High quality isolation for high density and high performance integrated circuits
US5976949May 27, 1997Nov 2, 1999Winbond Electronics Corp.Method for forming shallow trench isolation
US5981354Mar 12, 1997Nov 9, 1999Advanced Micro Devices, Inc.Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process
US5989978Jul 16, 1998Nov 23, 1999Chartered Semiconductor Manufacturing, Ltd.Shallow trench isolation of MOSFETS with reduced corner parasitic currents
US5998280Mar 20, 1998Dec 7, 1999National Semiconductor CorporationModified recessed locos isolation process for deep sub-micron device processes
US6013583Jun 25, 1996Jan 11, 2000International Business Machines CorporationLow temperature BPSG deposition process
US6030881May 5, 1998Feb 29, 2000Novellus Systems, Inc.High throughput chemical vapor deposition process capable of filling high aspect ratio structures
US6033961Apr 30, 1998Mar 7, 2000Hewlett-Packard CompanyIsolation trench fabrication process
US6051477Oct 22, 1996Apr 18, 2000Hyundai Electronics Industries Co., Ltd.Method of fabricating semiconductor device
US6090675Apr 2, 1999Jul 18, 2000Taiwan Semiconductor Manufacturing CompanyFormation of dielectric layer employing high ozone:tetraethyl-ortho-silicate ratios during chemical vapor deposition
US6156674Nov 25, 1998Dec 5, 2000Micron Technology, Inc.Semiconductor processing methods of forming insulative materials
US6171962Dec 18, 1997Jan 9, 2001Advanced Micro Devices, Inc.Shallow trench isolation formation without planarization mask
US6187651May 6, 1999Feb 13, 2001Samsung Electronics Co., Ltd.Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids
US6190979Jul 12, 1999Feb 20, 2001International Business Machines CorporationMethod for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill
US6191002Apr 26, 1999Feb 20, 2001Nec CorporationMethod of forming trench isolation structure
US6300219Aug 30, 1999Oct 9, 2001Micron Technology, Inc.Method of forming trench isolation regions
US6326282Apr 14, 1999Dec 4, 2001Samsung Electronics Co., Ltd.Method of forming trench isolation in a semiconductor device and structure formed thereby
US6329266Jun 1, 1999Dec 11, 2001Samsung Electronics Co., Ltd.Methods of forming isolation trenches including damaging a trench isolation mask
US6355966Mar 6, 2001Mar 12, 2002Micron Technology, Inc.Trench isolation region comprising a material selected from the group consisting of a silicon oxynitride, al2o3 or ta2o5; received at least partially within the semiconductor substrate proximate the trench isolation region.
US6448150Apr 6, 1998Sep 10, 2002Nanya Technology CorporationMethod for forming shallow trench isolation in the integrated circuit
US6455394Mar 13, 1998Sep 24, 2002Micron Technology, Inc.Method for trench isolation by selective deposition of low temperature oxide films
US6534395Mar 6, 2001Mar 18, 2003Asm Microchemistry OyMethod of forming graded thin films using alternating pulses of vapor phase reactants
US6583028Aug 2, 2002Jun 24, 2003Micron Technology, Inc.Methods of forming trench isolation regions
US6583060Jul 13, 2001Jun 24, 2003Micron Technology, Inc.Dual depth trench isolation
US6617251Jun 19, 2001Sep 9, 2003Lsi Logic CorporationMethod of shallow trench isolation formation and planarization
US6930058 *Apr 21, 2003Aug 16, 2005Micron Technology, Inc.Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge
US6933225Sep 23, 2002Aug 23, 2005Asm International N.V.Graded thin films
US7053010Mar 22, 2004May 30, 2006Micron Technology, Inc.Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells
US20010006255Feb 20, 2001Jul 5, 2001Kwon Dong-ChulSemiconductor device having improved metal line structure and manufacturing method therefor
US20010006839Dec 18, 2000Jul 5, 2001In-Seok YeoForming a trench mask pattern on semiconductor; etching; overcoating with dielectric
US20010041250Mar 6, 2001Nov 15, 2001Werkhoven Christian J.Graded thin films
US20010046753Sep 8, 1999Nov 29, 2001Fernando GonzalezMethod for forming a self-aligned isolation trench
US20020000195Apr 10, 2001Jan 3, 2002Won BangConcentration profile on demand gas delivery system (individual divert delivery system)
US20020004284Nov 5, 1998Jan 10, 2002Terry ChenMethod for forming a shallow trench isolation structure including a dummy pattern in the wider trench
US20020018849Jun 29, 2001Feb 14, 2002George Steven M.Vapor deposition using basic catalyst
US20030032281Sep 23, 2002Feb 13, 2003Werkhoven Christiaan J.Graded thin films
US20030129826Dec 23, 2002Jul 10, 2003Werkhoven Christiaan J.Graded thin films
US20040032006Jul 14, 2003Feb 19, 2004Eun-Jung YunFor isolation of a semiconductor device; structures having different constructions in a cell region and a peripheral region of a substrate
US20040082181Oct 16, 2003Apr 29, 2004Doan Trung TriMethods of forming trench isolation regions
US20040209484Apr 21, 2003Oct 21, 2004Hill Chris W.Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge
US20040266153Jun 26, 2003Dec 30, 2004Hu Yongjun JeffMethods of forming metal silicide
US20050009368Jul 7, 2003Jan 13, 2005Vaartstra Brian A.Methods of forming a phosphorus doped silicon dioxide comprising layer, and methods of forming trench isolation in the fabrication of integrated circuitry
US20050079730Oct 10, 2003Apr 14, 2005Infineon Technologies North America Corp.Trench isolation employing a high aspect ratio trench
US20050112282Sep 27, 2004May 26, 2005President And Fellows Of Harvard CollegeVapor deposition of silicon dioxide nanolaminates
US20050124171Jan 7, 2005Jun 9, 2005Vaartstra Brian A.Method of forming trench isolation in the fabrication of integrated circuitry
US20050142799Dec 30, 2004Jun 30, 2005Dongbuanam Semiconductor Inc.Method for forming STI of semiconductor device
EP0817251A1Jun 11, 1997Jan 7, 1998International Business Machines CorporationMethod of forming a doped silicon oxide film
EP0959493A2 *Sep 23, 1998Nov 24, 1999Semiconductor Process Laboratory Co., Ltd.Deposition of insulating films by CVD
JPH02277253A Title not available
JPH05315441A Title not available
JPH06334031A Title not available
JPH08146224A Title not available
WO2002027063A2Sep 28, 2001Apr 4, 2002Harvard CollegeVapor deposition of oxides, silicates and phosphates
WO2005008746A2Jun 30, 2004Jan 27, 2005Micron Technology IncMethods of forming a phosphorus doped silicon dioxide layer
Non-Patent Citations
Reference
1Beekmann et al., Sub-micron Gap Fill and In-Situ Planarisation Using Flowfill(TM) Technology, Electrotech 1-7 ULSI Conference, Portland, OR (Oct. 1995).
2Chen et al., Excimer Laser-Induced Ti Silicidation to Eliminate the Fine-Line Effect for Integrated Circuity Device Fabrication, 149 Journal of Electrochemical Society, No. 11, pp. G609-G612 (2002).
3Curtis, et al., APCVD TEOS: O<SUB>3 </SUB>Advanced Trench Isolation Applications, Semiconductor Fabtech, 9<SUP>th </SUP>Ed., pp. 241-247 (pre-Jul. 2003).
4Disclosed Anonymounsy 32246, Substrate Contact With Closed Bottom Trenches, Research Disclosure, 1 page (Feb. 1991).
5Gasser et al., Quasi-monolayer deposition of silicon dioxide, 250 Thin Solid Films, pp. 213-218 (1994).
6George et al., Atomic layer controlled deposition of SiO<SUB>2 </SUB>and Al<SUB>2</SUB>O<SUB>3 </SUB>using ABAB . . . binary reaction sequence Chemistry, 82/83 Applied Surface Science, pp. 460-467 (1994).
7Hasumann et al., Catalytic vapor deposition of highly conformal silica nanolaminates, Department of Chemistry and Chemical Biology, Harvard University, pp. 1-13 (May 14, 2002).
8Hausmann et al., Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates, 298 Science, pp. 402-406 (Oct. 11, 2002).
9Horie et al., Kinetics and Mechanism of the Reactions of O(<SUP>3</SUP>P) with SiH<SUB>4</SUB>, CH<SUB>3</SUB>SiH<SUB>3</SUB>, (CH<SUB>3</SUB>)<I/><SUB>2</SUB>SiH<SUB>2</SUB>, and (CH<SUB>3</SUB>)<I/><SUB>3</SUB>SiH, 95 J. Phys. Chem., pp. 4393-4400 (1991).
10Joshi et al., Plasma Deposited Organosilicon Hydride Network Polymers as Versatile Resists for Entirely Dry Mid-Deep UV Photolithography, 1925 SPIE, pp. 709-720 (1993).
11Kiermasz et al., Planarisation for Sub-Micron Devices Utilising a New Chemistry, 1-2 Electrotech, Dumic Conference, California (Feb. 1995).
12Klaus et al., Atomic Layer Deposition of SiO<SUB>2 </SUB>Using Catalyzed and Uncatalyzed Self-Limiting Surface Reactions, 6 Surface Review and Letters, Nos. 3 & 4, pp. 435-448 (1999).
13Kojima et al., Planarization Process Using a Multi-Coating of Spin-on-Glass, V-MIC Conference, California, 2 pages (1995).
14Matsuura et al., A Highly Reliable Self-planarazing Low-k Intermetal Dielectric for Sub-quarter Micron Interconnects, IEEE, pp. 785-788 (1997).
15Matsuura et al., Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications, IEEE, pp. 117-120 (1994).
16McClatchie et al., Low Dielectric Constant Flowfill(TM) Technology for IMD Applications, 7 pages (pre-Aug. 1999).
17Miller et al., Self-limiting chemical vapor deposition of an ultra-thin silicon oxide film using tri-(tert-butoxy)silanol, 397 Thin Solid Films, pp. 78-82 (2001).
18Morishita et al., Atomic-layer chemical-vapor-deposition of silicon-nitride, 112 Applied Surface Science, pp. 189-204 (1997).
19Nishiyama et al., Agglomeration Resistant Self-Aligned Silicide Process Using N<SUB>2 </SUB>Implantation Into TiSi<SUB>2</SUB>, 36 Jpn. J.Appl. Phys., Part 1, No. 6A, pp. 3639-3643 (Jun. 1997).
20PCT/US2004/021156; Filed Jun. 30, 2004; Search Report.
21PCT/US2004/021156; Filed Jun. 30, 2004; Written Opinion Issued on Jan. 18, 2005; 6 pps.
22Shareef et al., Subatmospheric chemical vapor deposition ozone/TEOS process for SiO<SUB>2 </SUB>trench filling, J. Vac. Sci. Technol. B 13(4), pp. 1888-1995 (Jul./Aug. 1995).
23U.S. Appl. No. 10/615,051, filed Jul. 2003, Vaartstra.
24U.S. Appl. No. 10/655,699, filed Sep. 2002, Derderian et al.
25U.S. Appl. No. 10/806,923, filed Mar. 2004, Li et al.
26U.S. Appl. No. 10/931,524, filed Aug. 2004, Sandhu.
27Withnall et al., Matrix Reactions of Methylsilanes and Oxygen Atoms, 92 J. Phys. Chem., pp. 594-602 (1988).
28Wolf, Chapter 13: Polycides and Salicides of TiSix, CoSi2, and NiSi, Silicon Processing for the VLSI Era, vol. IV, pp. 603-604 (pre-2003).
29Yokoyama et al., Atomic layer controlled deposition of silicon nitride and in situ growth observation by infrared reflection absorption spectroscopy, 112 Applied Surface Science, pp. 75-81 (1997).
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Classifications
U.S. Classification438/424, 257/E21.547, 257/E21.275, 438/783, 257/E21.545
International ClassificationC23C16/44, H01L21/316, H01L21/762, C23C16/04, C23C16/40, C23C16/455, H01L21/76
Cooperative ClassificationH01L21/76227, C23C16/45531, H01L21/02271, C23C16/402, C23C16/401, H01L21/0228, H01L21/31625, H01L21/02129, H01L21/02216, C23C16/045
European ClassificationH01L21/02K2C7C4B, H01L21/02K2E3B6F, H01L21/02K2E3B6, H01L21/02K2C1L1B, C23C16/40B2, C23C16/40B, C23C16/04D, H01L21/762C2, H01L21/316B4, C23C16/455F2B4
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