|Publication number||US7297955 B2|
|Application number||US 10/874,343|
|Publication date||Nov 20, 2007|
|Filing date||Jun 24, 2004|
|Priority date||Sep 30, 2003|
|Also published as||EP1521100A2, EP1521100A3, EP1643272A2, EP1643273A2, EP1666921A2, US20050067572, US20050167600, US20050178969, US20050178970, US20050199816, US20060243915|
|Publication number||10874343, 874343, US 7297955 B2, US 7297955B2, US-B2-7297955, US7297955 B2, US7297955B2|
|Inventors||Kensuke Amemiya, Yuuichirou Ueno, Hiroshi Kitaguchi, Osamu Yokomizo, Shinichi Kojima, Katsutoshi Tsuchiya, Norihito Yanagita, Kazuma Yokoi|
|Original Assignee||Hitachi, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (31), Referenced by (21), Classifications (16), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application is related to U.S. application Ser. No. 10/874,359, filed on Jun. 24, 2004 and being based on Japanese Patent Application No. 2003-340688, filed on Sep. 30, 2003, the entire contents of which are incorporated herein by reference.
The present invention relates to a nuclear medicine diagnostic apparatus, and more particularly, to a positron emission tomography (hereinafter referred to as “PET”) apparatus, which is a kind of a nuclear medicine diagnostic apparatus using a semiconductor radiation detector, semiconductor radiation detection apparatus or detector unit.
A detector using a NaI scintillator is known as a conventional radiation detector for detecting radiation such as γ-rays. With a gamma camera (a kind of nuclear medicine diagnostic apparatus) provided with a NaI scintillator, radiation (γ-rays) incident on the scintillator at an angle restricted by many collimators interacts with NaI crystals and emits scintillation light. This light travels in such a way as to sandwich a light guide, reaches a photoelectric multiplier and becomes an electrical signal. The electrical signal is shaped by a measuring circuit mounted on a measuring circuit fixing board and transferred from an output connector to an external data collection system. All these scintillator, light guide, photoelectric multiplier and measuring circuit, measuring circuit fixing board, etc., are housed in a light shielding case and shielded from electromagnetic waves other than external radiation.
Since a gamma camera using a scintillator has a structure with a large photoelectric multiplier (also called “photomultiplier”) placed after one large crystal such as NaI, its position resolution remains on the order of 10 mm. Furthermore, since the scintillator detects radiation in multi-stages of conversion from radiation to visible light, from visible light to electrons, it has a problem of having considerably poor energy resolution. For example, there is a PET apparatus (positron emission tomography apparatus) having position resolution of 5 to 6 mm or a high-end PET apparatus having position resolution of 4 mm or so, but since their photoelectric multipliers use vacuum tubes, it is difficult to further improve position resolution.
There are radiation detectors for detecting radiation according to principles different from those of such a scintillator, such as semiconductor radiation detectors provided with a semiconductor radiation detection element using a semiconductor material such as CdTe (cadmium telluride), TlBr (thallium bromide) and GaAs (gallium arsenide).
This semiconductor radiation detector is attracting attention because its semiconductor radiation detection element converts electrical charge produced by interaction between radiation and the semiconductor material to an electrical signal, and therefore it has better efficiency of conversion to an electrical signal than the scintillator and can also be miniaturized.
Meanwhile, when a semiconductor material such as T1 making up a semiconductor radiation detection element interacts with radiation in a semiconductor radiation detector, holes having positive electrical charge and electrons having negative electrical charge are generated. While mobility of electrons is relatively large, mobility of holes is relatively small. That is, electrons move relatively easily and holes move with difficulty. This takes more time for holes to reach an electrode than electrons. Moreover, holes may be annihilated before reaching the electrode. This involves a problem that the detection sensitivity of radiation is worsened. Thus, these problems require solutions.
It is an object of the present invention to provide a semiconductor radiation detector capable of improving detection sensitivity.
In order to solve the above described problems, a first embodiment of the present invention improves detection sensitivity by shortening a distance between electrodes for charge collection of a semiconductor radiation detector. That is, the distance between an anode electrode and cathode electrode or the thickness of a semiconductor area sandwiched between the anode electrode and cathode electrode is 0.2 to 2 mm. In this structure, the distance from positions of electrons and holes generated by interaction between the semiconductor material and radiation to the electrodes is shortened, and therefore the time required for them to reach the electrodes is shortened. Furthermore, shortening the distance up to the electrodes reduces the probability that holes may be annihilated midway the distance.
A second embodiment of the present invention is a nuclear medicine diagnostic apparatus comprising a plurality of unit substrates including a plurality of semiconductor radiation detectors for introducing radiation and an integrated circuit for processing radiation detection signals output from the plurality of semiconductor radiation detectors. This allows the semiconductor radiation detectors and the integrated circuits which process the outputs to be disposed close to one another, with the result that when weak output signals of the semiconductor radiation detectors are transmitted to the integrated circuits, it is possible to reduce influences of noise on the weak output signals.
The semiconductor radiation detector, analog LSI (Large Scale Integrated Circuit), AD converter and digital LSI are preferably arranged on the unit substrate in that order and the respective elements are connected by wiring so that a signal detected by the semiconductor radiation detector is processed by the analog LSI, the signal processed by the analog LSI is processed by the AD converter, and the signal processed by the AD converter is processed by the digital LSI. By shortening the distance between the semiconductor radiation detector and analog LSI in particular, this structure can shorten the wiring distance between the semiconductor radiation detector and analog LSI and thereby reduce noise superimposed on the wiring until the signal detected by the semiconductor radiation detector reaches the analog LSI. In an embodiment which will be described later, the LSI (integrated circuit) corresponds to an ASIC. Also, the semiconductor radiation detection apparatus corresponds to a combined substrate (detector substrate+ASIC substrate) in the embodiment which will be described later.
According to the second embodiment, detection signals when the semiconductor radiation detectors detect radiation are processed by an application-specific IC called “ASIC (Application Specific Integrated Circuit)” and this embodiment is intended to solve an additional problem discovered by the inventor et al. that since the detection signals output from the semiconductor radiation detectors are weak, the ASIC is easily affected by noise. A reduction of the noise leads to substantial improvement of detection sensitivity (count, peak value, time detection accuracy) by the semiconductor radiation detectors.
Different substrates are preferably used as the substrate for mounting the semiconductor radiation detectors and the substrate for mounting the LSI. During ordinary operation, the two substrates are used in combination as a combined substrate (unified substrate) so that in the event of trouble, only the troubled substrate can be replaced to thereby facilitate maintenance and examination, etc.
A third embodiment of the present invention adopts a unit-type construction in which a plurality of unit substrates including semiconductor radiation detectors and an integrated circuit are mounted in a frame in a detachable/attachable manner. Since it is only necessary to mount a detector unit including a plurality of unit substrates on a nuclear medicine diagnostic apparatus, a plurality of semiconductor radiation detectors can be mounted on the nuclear medicine diagnostic apparatus at a time. In this way, the time required to mount the semiconductor radiation detectors on the nuclear medicine diagnostic apparatus can be shortened drastically.
The embodiment is preferably adapted so that these unit substrates can be removed from the detector unit one by one or the whole detector unit can be removed from the nuclear medicine diagnostic apparatus, or more specifically, from the camera, which facilitates maintenance and examination.
Note that many semiconductor radiation detectors are used for a nuclear medicine diagnostic apparatus (radiological diagnostic apparatus) such as PET, SPECT and gamma camera. For example, a PET uses a hundred thousand to several hundreds of thousands of (channels) semiconductor radiation detectors and there is a demand for shortening the time required to mount these many semiconductor radiation detectors on the nuclear medicine diagnostic apparatus. A fourth embodiment of the present invention is implemented to meet such a demand. There is also a demand for facilitating maintenance and examination of semiconductor radiation detectors.
The present invention can prevent or reduce deterioration of the detection sensitivity of radiation using semiconductor radiation detectors. The present invention can also prevent or reduce deterioration of signals detected by the semiconductor radiation detectors. This allows, for example, a nuclear medicine diagnostic apparatus to obtain clear images.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
A nuclear medicine diagnostic apparatus which is a preferred embodiment of the present invention will be explained with reference to attached drawings in detail below as appropriate. The following are explanations of the nuclear medicine diagnostic apparatus according to this embodiment, distance between electrodes of a semiconductor radiation detector, arrangement (layout) of elements such as analog ASIC on a substrate, and elements applicable to this embodiment for construction of substrate units, etc. Note that an analog ASIC refers to an ASIC (Application Specific Integrated Circuit) which is an application-specific IC for processing analog signals and is a kind of LSI.
<<Nuclear Medicine Diagnostic Apparatus>>
First, the nuclear medicine diagnostic apparatus (radiological diagnostic apparatus) according to this embodiment will be explained. As shown in
As shown in
Hereafter, the characteristic parts of this embodiment will be explained.
<<Semiconductor Radiation Detector; Distance between Electrodes>>
First, the detector 21 applied to this embodiment will be explained. As shown in
An overview of the principle of γ-ray detection using the detector 21 will be explained using
As shown in
The thickness (distance between electrodes) t of the detection element 211 is preferably 0.2 mm to 2 mm. This is because a thickness t of not less than 2 mm slows down the rising speed of the peak value and reduces the maximum value of the peak value as well. On the other hand, a thickness t of smaller than 0.2 mm relatively increases the thickness (volume) of the electrodes (anode, cathode) and when installed on a substrate, the proportion of the very semiconductor material S that interacts with radiation decreases. That is, reducing the thickness t of the semiconductor material S relatively increases the thickness of the electrode which does not interact with γ-rays on one hand, and the proportion of the semiconductor material S which interacts with γ-rays relatively decreases on the other, with the result that the sensitivity of detecting γ-rays decreases (γ-rays pass by). Furthermore, a smaller thickness t may cause more leakage current preventing a high voltage from being applied for charge collection.
For the same reason, the thickness t of the semiconductor material S is preferably 0.5 mm to 1.5 mm and such a thickness t allows more reliable detection of γ-rays and more correct measurement of the peak value, etc.
In the case of the PET apparatus 1, since it carries out simultaneous measurement, one of problems to be solved is to correctly measure a γ-ray detection time. For example, in
As shown in
As shown in
Adopting the detector 21 having such a laminated structure can obtain a better peak value rising speed and an accurate peak value and increase the number of γ-rays (count value)(increase the sensitivity) that interact with the semiconductor material S.
An area s of the electrode (anode A, cathode C) is preferably 4 to 120 mm2. An increase of the area s increases the capacity (stray capacitance) of the detector 21 and this increase in the stray capacitance makes noise easier to superimpose, and therefore the area s of the electrode is preferably as small as possible. Furthermore, charge produced when γ-rays are detected is partially accumulated in the stray capacitance, and therefore there is a problem that when the stray capacitance increases, the amount of charge stored in a charge amplifier 24 b of an analog ASIC 24 or further an output voltage (peak value) decreases. When CdTe is used for the detector 21, its dielectric constant is 11 and if the area s of the detector 21 is 120 mm2, thickness t is 1 mm, then the capacity is 12 pF, which is not negligible considering the fact that the stray capacitance of connectors, etc. of the circuit is several pF. Therefore, the area s of the electrode is preferably 120 mm2 or less.
Furthermore, the lower limit of the area s of the electrode is determined by position resolution of the PET apparatus. The position resolution of the PET apparatus is determined by not only the size (array pitch) of the detector 21 but also the positron range, etc., but since the range of positron of 18F is 2 mm, setting the size of the detector 21 to 2 mm or less is meaningless. The method of mounting so that the area of the electrode becomes a minimum is a case where the surface of the electrode is placed perpendicular to the radius direction of the camera 11 and from the above described consideration, the lower limit of one side of the electrode is 2 mm and the lower limit of the area s of the electrode is 4 mm2.
In the above described explanations, CdTe is used as the semiconductor material S which interacts with γ-rays, but it goes without saying that the semiconductor material S may also be TlBr or GaAs, etc. Moreover, the terms “laminated structure”, “upper layer” and “lower layer” have been used, but these terms are based on
<<Combined Substrate; Detector Substrate and ASIC Substrate>>
A detailed structure of the combined substrate (unit substrate) 20 installed in the detector unit 2 (
With reference to
As shown in
In the above described explanations, the 16 horizontal detectors 21 are arranged in the axial direction of the camera 11, but the arrangement is not limited to this. For example, the 16 horizontal detectors 21 may also be arranged in the circumferential direction of the camera 11.
As shown in
Then, the ASIC substrate 20B incorporating the ASIC will be explained. As shown in
These elements 22, 23, 24, 25 and 26 are arranged (on-board wiring) so that a signal supplied from the detector substrate 20A is supplied to the capacitor 22, resistor 23, analog ASIC 24, ADC 25 and digital ASIC 26 in that order.
The ASIC substrate 20B includes a connector (spiral contact) C1 which is connected to the on-board wiring which is connected to each capacitor 22 to make electrical connections to the detector substrate 20A and a substrate connector C2 which makes electrical connections to the data processing apparatus (the unit combination FPGA which will be described later). Note that the above described detector substrate 20A also includes the connector C1 connected to the on-board wiring which is connected to each detector 21.
(Connection Structure between Detector Substrate and ASIC Substrate)
The connection structure between the detector substrate 20A and ASIC substrate 20B will be explained.
The detector substrate 20A and ASIC substrate 20B are connected not with their respective end faces (ends) facing each other but by providing an overlap area where both ends overlap with each other and connecting the connectors C1 in this overlap area as shown in
With consideration given to this aspect, this embodiment connects the detector substrate 20A and ASIC substrate 20B not with the respective end faces facing each other but by providing the overlap area so that the areas close to the ends overlap with each other as described above. This improves toughness against flexure or bending compared to the connection with the end faces facing each other, which is preferable. Moreover, improving toughness against flexure or bending of the combined substrate suppresses dislocation of the detectors 21 and prevents deterioration of accuracy of identifying positions at which γ-rays are generated. As shown in
The detector substrate 20A and ASIC substrate 20B are electrically connected using the aforementioned overlap area. For this purpose, a connector C1 (
Using such an electrical connection structure between the detector substrate 20A and ASIC substrate 20B allows signals to be sent from the detector substrate 20A to the ASIC substrate 20B with low loss. Note that when loss is small, the energy resolution on the part of the detectors 21 improves.
Furthermore, as described above, the detector substrate 20A and ASIC substrate 20B are connected in a freely detachable/attachable manner by means of screws, etc. Thus, even when trouble occurs in the semiconductor radiation detectors 21 or ASICs 24, 26, all that should be done is just to replace the part with trouble. Therefore, this eliminates waste that the entire combined substrate 20 must be replaced due to trouble in that part. Moreover, since electrical connection between the detector substrate 20A and ASIC substrate 20B is made by the connector C1 such as the aforementioned spiral contactor (R), connection or disconnection (combination or dissociation) between the substrates can be done easily.
In the above described construction, one detector substrate 20A is connected to the ASIC substrate 20B, but it is also possible to divide the detector substrate into a plurality of portions. For example, two detector substrates may be connected to the ASIC substrate, each consisting of eight horizontal by four vertical detectors 21. According to this construction, if one detector 21 has trouble, of the two detector substrates, only the one including the faulty detector 21 needs to be replaced and it is therefore possible to reduce waste in maintenance (cost reduction).
Then, the layout of elements such as the detectors 21, ASICs 24, 26 of the combined substrate 20 will be explained with reference to
As shown in
Here, the shorter the length of the circuit and length (distance) of the wiring, the better, because there is less influence of noise or less attenuation of a signal. Furthermore, when simultaneous measurement processing is carried out by the PET apparatus 1, a shorter circuit or wiring is preferred because its time delay is smaller (preferable because the accuracy of detection time is not lost). For this reason, in order of the detector 21, capacitor 22, resistor 23, analog ASIC 24, ADC 25 and digital ASIC 26 from the center axis of the camera 11 outward in the radius direction of the camera 11, that is, the elements 21, 22, 23, 24, 25 and 26 are arranged (layout) in this embodiment as shown in
Since the signal of the analog ASIC 24 is subjected to processing such as amplification, it is less susceptible to influences of noise even if the length of wiring from the analog ASIC 24 onward is long. That is, considering noise, there is no problem even if the wiring length from the analog ASIC 24 onward is long. However, with lengthy wiring, there is a delay in signal transmission and the accuracy of the above described detection time may deteriorate.
In this embodiment, since not only the detector 21 but also the analog ASIC 24 and digital ASIC 26 are included in one combined substrate 20, the detector 21, analog ASIC 24 and digital ASIC 26 can be arranged in the longitudinal direction of the bed 14, that is, the direction perpendicular to the body axis of the examinee subject to an examination, and therefore this eliminates the need to extend the length of the camera (image pickup apparatus) 11 in the longitudinal direction of the bed more than necessary. It is also possible to consider the possibility of arranging the analog ASIC 24 and digital ASIC 26 outside in the radius direction of the annularly arranged detector group, and in the longitudinal direction of the bed 14, but this causes the length of the camera 11 in the longitudinal direction of the bed to become longer than necessary. Furthermore, semiconductor radiation detectors are used as the detectors 21, and analog ASIC 24 and digital ASIC 26 are used as signal processing apparatuses, the length of the combined substrate 20 in the longitudinal direction is shortened and the length of the camera 11 in the orthogonal direction can be shortened significantly compared to the case where a scintillator is used. Furthermore, the combined substrate 20 is provided with the detector 21, analog ASIC 24 and digital ASIC 26 in that order in the longitudinal direction thereof, and therefore it is possible to shorten the length of the wiring connecting them and simplify the wiring on the substrate.
Here, in this embodiment, one analog ASIC 24 is connected to 32 detectors 21 to process signals obtained from the detectors 21. As shown in
The capacitor 22 and resistor 23 can also be provided inside the analog ASIC 24, but this embodiment arranges the capacitor 22 and resistor 23 outside the analog ASIC 24 for reasons such as obtaining an appropriate capacitance and appropriate resistance and reducing the size of the analog ASIC 24. Note that the capacitor 22 and resistor 23 are preferably disposed outside because in this way variations in the individual capacitance and resistance are reduced.
In the analog ASIC 24 shown in
The analog ASIC 24 and each ADC 25 are connected via one wire which sends slow system signals corresponding to 8 channels all together. Furthermore, each analog ASIC 24 and digital ASIC 26 are connected via 32 wires which send 32-channel fast system signals one by one. That is, one digital ASIC 26 is connected to four analog ASICs 24 via a total of 128 wires.
The output signal of the slow system output from the analog ASIC 24 is an analog peak value (maximum value of the graph shown in
The ADC 25 sends the digitized 8-bit peak value information to the digital ASIC 26. For this purpose, each ADC 25 and digital ASIC 26 are connected via a wire. For example, since there are sixteen ADCs 25 on both sides, the digital ASIC 26 is connected to the ADC 25 via a total of sixteen wires. One ADC 25 processes signals corresponding to 8 channels (signals corresponding to eight detection elements). The ADC 25 is connected to the digital ASIC 26 via one wire for transmission of an ADC control signal and one wire for transmission of peak value information.
As shown in
The data transfer circuit 38 sends packet data which is digital information output from the ADC control circuit 36 of each packet data generation apparatus 34 to the integrated circuit (unit combination FPGA (Field Programmable Gate array)) 31 for unit combination provided for the housing 30 of the detector unit 2 (
Since the ADC 25 converts the peak value information output from the peak hold circuit 24 e corresponding to the detector ID information included in a control signal output from the ADC control circuit 36 to a digital signal, one ADC 25 is provided for a plurality of analog signal processing circuits 33 in one analog ASIC 24. Therefore, there is no need to provide one ADC 25 for each of a plurality of analog signal processing circuits 33 and it is possible to thereby significantly simplify the circuit construction of the ASIC substrate 20B. Also one information combination apparatus for generating combination information is enough for a plurality of analog signal processing circuits 33 in one analog ASIC 24, which can simplify the circuit construction of the digital ASIC 26. Moreover, only one ADC control apparatus for identifying detector IDs needs to be provided for a plurality of analog signal processing circuits 33 in one analog ASIC 24, simplifying the circuit construction of the digital ASIC 26.
In this way, packet data output from the digital ASIC 26 and including detector IDs for uniquely identifying (1) peak value information, (2) determined time information and (3) detector 21, one by one is sent to the next data processing apparatus 12 (see
According to the above described explanations, the detector substrate 20A includes the detectors 21 and the ASIC substrate 20B includes the capacitor 22, resistor 23, analog ASIC 24, ADC 25 and digital ASIC 26. However, the detector substrate (first substrate) 20A may include the detector 21, capacitor 22, resistor 23 and analog ASIC 24, etc., and the ASIC substrate (second substrate) 20B may include the ADC 25 and digital ASIC 26, etc. By the detector substrate 20A including the detectors 21 and analog ASIC 24, the distance (wire length) between the detector 21 and analog ASIC 24 can be further shortened. Thus, it is possible to further reduce influences of noise.
Furthermore, the combined substrate 20 may include three substrates (detector substrate 20A, analog ASIC substrate and digital ASIC substrate) and they may be connected in a detachable/attachable manner through their respective connectors.
In this case, of the three substrates, the detector substrate 20A includes the detectors 21, the analog ASIC substrate includes the capacitor 22, resistor 23 and analog ASIC 24 and the digital ASIC substrate includes the ADC 25 and digital ASIC 26. This structure separates the substrate incorporating the analog circuit from the substrate incorporating the digital circuit to thereby prevent noise on the digital circuit side from entering the analog circuit. Furthermore, this structure separates the substrate incorporating the analog ASIC from the substrate incorporating the digital ASIC and connects the two substrates using a detachable/attachable connector, and therefore even when only the digital ASIC malfunctions, only the digital ASIC substrate needs to be replaced. In this way, this structure can further reduce waste.
In the above explanations, the substrate body 20 a (detector substrate 20A) for mounting the detectors 21 is different from the substrate body 20 b (ASIC substrate 20B) for mounting the ASICs 24, 26. Thus, when, for example, both ASICs are soldered to a substrate by means of a BGA (Ball Grid Array) using reflow, only the ASIC substrate can be soldered and this is preferable because the semiconductor radiation detector 21 need not be exposed to a high temperature. Of course, it is also possible to arrange all the elements 21 to 26 on the same substrate and use no connector C1.
<<Detector Unit; Unit Construction through Housing of Combined Substrate>>
Next, a unit construction by housing the above described combined substrate 20 in the housing 30 will be explained. This embodiment constructs a detector unit (twelve substrate units) 2 by housing twelve combined substrates 20 in the housing (frame) 30. The camera 11 of the PET apparatus 1 has a structure in which 60 to 70 detector units 2 are arranged in the circumferential direction in a detachable/attachable manner (see
(Housing in Housing)
As shown in
As shown in
As shown in
Since the detectors 21 using CdTe as the semiconductor material S in this embodiment generate charge in reaction with light, the housing 30 is made of a material having light shielding properties such as aluminum and an alloy of aluminum and designed in such a way as to eliminate gaps through which light enter. That is, the housing 30 is constructed to secure light shielding properties. If, for example, light shielding properties are secured by other means, the housing 30 itself need not be provided with light shielding properties and the housing 30 can be a frame (framework) to hold the detectors 21 in a detachable/attachable manner (e.g., no light shielding plane member (panel), etc., is required).
As shown in
In order to mount the detector units 2 in the unit support member, this embodiment allows many detectors 21 to be mounted in the camera 11 at a time. This can considerably shorten the time of mounting the detectors 21 in the camera 11. Furthermore, packet data (all packet data for all detectors 21 of a combined substrate 20) output from the data transfer apparatus 38 of all the combined substrates 20 in the detection unit 2 is sent from the unit combination FPGA 31 provided in the detection unit 2 to the data processing apparatus 12. In this way, the number of wires through which packet data is transmitted to the data processing apparatus 12 in this embodiment is also significantly reduced compared to the case where packet data is sent from each data transfer apparatus 38 of the combined structure 20 to the data processing apparatus 12.
When the detector units 2 is mounted in the camera 11, a cover 11 a is removed to make the unit support member exposed so that the detector units 2 are inserted until the detector units 2 touch the flange portinos. When the detector units 2 are inserted and fitted, connections between the camera 11 and the detector units 2 are made, and signals and power supply are connected between the camera 11 and the detector units 2.
Then, the high-voltage power supply apparatus PS for supplying a charge collection voltage will be explained. As shown in
Conventionally, a supply voltage of 300 V with extremely small fluctuations is supplied from a precision power supply apparatus in a remote place, but since (1) when the distance from the precision power supply apparatus increases, a wider insulating structure for high voltage wiring is required (the insulating distance increases) and (2) the voltage fluctuates due to a temperature variation of the detectors 21, there is a problem that supplying a precise voltage from the precision power supply apparatus does not necessarily result in a precise voltage in the part of the target detectors 21.
Furthermore, to facilitate maintenance and examination, it is also possible to consider providing the detector unit 2 according to this embodiment with a power connector (not shown) and removing a high-voltage power line extending from the precision power supply apparatus at this power connector. That is, according to this embodiment, it is possible to consider supplying a high-voltage power supply to the detector units 2 from outside the units 2 via power connectors. However, in the case of a high voltage of 300 V, this results in a problem that the size of the power connector increases in addition to the above described problem of insulation.
According to this embodiment, the high-voltage power supply apparatus PS built in the detector unit 2 is connected to an external low voltage (5 to 15 V) DC power supply through the power connector 42 and connector 38 provided on the ceiling plate 30 a via power wiring. A high-voltage terminal of the high-voltage power supply apparatus PS is connected to twelve connectors C3 provided on the ceiling plate 30 a through the connector 43 provided on the ceiling plate 30 a and connected to electrodes C of the respective detectors 21 provided on the substrate body 20 a through the connector C2 of the respective combined substrates 20, power wiring (not shown) in the substrate body 20 b, connector C1 and power wiring (not shown) in the substrate body 20 a. The connectors C1, C2 include not only connectors for transmitting output signals of the detectors 21 but also connectors for power wiring. Since the high-voltage power supply apparatus PS boosts a low voltage applied from the power supply to 300 V using a DC-DC converter, it is possible to reduce the high-voltage section and thereby shorten the insulation distance. That is, this eliminates the necessity for using high-voltage wiring for a portion from the connector 42 to the DC power supply. It also facilitates maintenance, etc. For the problem with voltage fluctuations, this embodiment provides not the high-precision power supply apparatus but the high-voltage power supply apparatus PS having accuracy according to a temperature fluctuation of the voltage. This eliminates the necessity for a high-precision power supply. Furthermore, since it is a low voltage that is received from an external power supply, it is possible to use a small power connector to be provided for the connector 38. Using the small power connector increases the degree of freedom in the layout. Furthermore, since the high-voltage power supply apparatus PS is arranged in a space formed in the housing 30 on the back side of the FPGA 31, the arrangement of the high-voltage power supply apparatus PS in the housing 30 makes the detector unit 2 more compact instead of upsizing. It is also possible to directly connect the high-voltage power supply apparatus PS to the power wiring provided on the substrate body 20 a through the connector, without the ceiling plate 30 a. Furthermore, the power connector can also be separated from the output signal connector of the detector 21. This prevents noise from entering the signal wiring from the power supply system.
Furthermore, by reducing a supply voltage to the detector unit 2, it is possible to supply power to the high-voltage power supply apparatus PS at a low voltage through the unit combination FPGA 31 as with power supplies to the ASICs 24, 26.
Furthermore, supplying power using the high-voltage power supply apparatus PS eliminates the necessity for insulation from the housing (GND).
The voltage supplied from the FPGA 31 to the high-voltage power supply apparatus PS is boosted to 300 V by a DC-DC converter (not shown) in the high-voltage power supply apparatus PS and after boosting, passed through the ceiling plate 30 a of the housing 30 and supplied from ASIC substrate 20B→detector substrate 20A→each detector 21 for each combined substrate 20. That is, the housing 30 (ceiling plate 30 a) is provided with wiring for voltage supply (not shown) for supplying a voltage from the high-voltage power supply apparatus PS to each combined substrate 20. Furthermore, each combined substrate 20 is provided with wiring for voltage supply which supplies a voltage supplied from the high-voltage power supply apparatus PS to each detector 21 via the substrate connector C2.
A nuclear medicine diagnostic apparatus according to another embodiment will be explained. The nuclear medicine diagnostic apparatus of this embodiment is single photon emission computer tomography (SPECT) apparatus.
This SPECT apparatus 51 will be explained using
The combined substrate 53 includes a detector substrate 20A and an ASIC substrate 53B as with the above described combined substrate 20 (
When the bed 14 on which an examinee administered with radiopharmaceuticals is laid is moved, the examinee is moved between the pair of radiation detection blocks 52. When the rotary holder 57 is rotated, the detector units 2A of each radiation detection block 52 revolve around the examinee. γ-rays emitted form an area in the body of the examinee where radiopharmaceuticals are concentrated (e.g., affected area) C pass through the radiation passages of the collimator 55 and are introduced into the corresponding detectors 21. The detectors 21 output γ-rays detection signals. These γ-ray detection signals are processed by analog ASIC 24A and digital ASIC 26A, which will be described later.
The construction of the detector substrate 20A used in this embodiment (Embodiment 2) is the same as that in Embodiment 1 and therefore the explanations will be omitted in this embodiment. The ASIC substrate 53B making up the combined substrate 53 will be explained using
One analog ASIC 24A is provided with 32 sets of analog signal processing circuits (analog signal processing apparatuses) 33A having a slow system and fast system. One analog signal processing circuit 33A is provided for each detector 21. Here, the fast system includes a trigger output circuit 24 f which outputs a trigger signal for specifying detection of γ-rays. As with the analog ASIC 24, the slow system is provided with a charge amplifier 24 b, a polarity amplifier 24 c, a band pass filter 24 d and a peak hold circuit 24 e connected in this order. One analog ASIC 24A integrates 32 sets of analog signal processing circuits 33A into one LSI. A γ-ray detection signal which is output from the detector 21 and has passed through the capacitor 22 and resistor 23 are guided through the charge amplifier 24 b, polarity amplifier 24 c and band pass filter 24 d and input to the peak hold circuit 24 e. The peak hold circuit 24 e holds a peak value of the γ-ray detection signal. The γ-ray detection signal output from the band pass filter 24 d is input to the trigger output circuit 24 f. The trigger output circuit 24 f outputs a trigger signal when a γ-ray detection signal at a set level or higher is input to remove influences of noise.
The digital ASIC 26A includes a packet data generation apparatus 34A and a data transfer circuit 37 and integrates them into one LSI. The above described trigger signal is input to the ADC control circuit 36A of the packet data generation apparatus 34A. All the digital ASICs 26A provided on the SPECT apparatus 51 receive a 64 MHz clock signal from a clock generation apparatus (crystal oscillator) (not shown) and operate synchronously. The clock signal input to each digital ASIC 26A is input to the respective ADC control circuits 36A in all the packet data generation apparatuses 34A. The ADC control circuit 36A identifies the detector ID when the trigger signal is input. That is, the ADC control circuit 36A stores a detector ID for each trigger output circuit 24 f connected to the ADC control circuit 36A and can identify, when a trigger signal is input from a certain trigger output circuit 24 f, the detector ID corresponding to the trigger output circuit 24 f. The ADC control circuit 36A outputs an ADC control signal including the detector ID information to the ADC 25. The ADC 25 converts the peak value information output from the peak hold circuit 24 e of the analog signal processing circuit 33A corresponding to the detector ID to a digital signal and outputs it. This peak value information is input to the ADC control circuit 36. The ADC control circuit 36A adds the peak value information to the detector ID to generate packet data. The packet data (including detector ID and peak value information) which is the digital information output from the ADC control circuit 36A of each packet data generation apparatus 34A is input to the data transfer circuit 37. The data transfer circuit 37 sends the packet data output from each ADC control circuit 36A to the unit combination FPGA 31 of the detector unit 2A periodically. The unit combination FPGA 31 outputs the digital information to the information transmission wiring connected to the connector 38.
Packet data output from the unit combination FPGA 31 is sent to the data processing apparatus 12. A rotation angle detected by an angle gauge (not shown) connected to the rotation shaft of a motor (not shown) for rotating the rotary holder 57 is input to the data processing apparatus. This rotation angle indicates the rotation angle of each radiation detection block 52 and more specifically indicates the rotation angle of each detector 21. Based on this rotation angle, the data processing apparatus 12 determines the position (position coordinates) of each revolving detector 21 on the revolving orbit. In this way, the position (position coordinates) of the detector 21 when γ-rays are detected is calculated. Based on the calculated position of the detector 21, the data processing apparatus 12 counts γ-rays whose peak value information reaches and exceeds a set value. This counting is performed on each area obtained by dividing the revolving circle into 0.5° portions relative to the rotational center of the rotary holder 57. The peak value information is an accumulated value of peak values of respective γ-ray detection signals of a plurality of detectors 21 (four detectors 21 arranged on a straight line in
The foregoing embodiments have described the PET apparatus 1 and SPECT apparatus 51, but the present invention is also applicable to a γ camera. Functional images obtained from the γ camera are two-dimensional and the γ camera is provided with a collimator for regulating angles of incidence of γ-rays. Moreover, it is also possible to adopt a construction of a nuclear medicine diagnostic apparatus combining the PET apparatus 1 and SPECT apparatus 51, and an X-ray CT.
Mounting (housing) of the detector unit 2 in the camera 11 is not limited to the mounting using the above-described unit support member, but any mounting/housing means or method can be used.
It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.
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|U.S. Classification||250/363.05, 250/370.09, 250/370.01, 250/363.04|
|International Classification||G01T1/164, G01J1/00, G01T1/29, G01T1/166, G01T1/24, H01L31/09, H01L27/14, G01T1/161|
|Cooperative Classification||G01T1/2928, G01T1/2985|
|European Classification||G01T1/29D4, G01T1/29D1C|
|Oct 19, 2004||AS||Assignment|
Owner name: HITACHI, LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AMEMIYA, KENSUKE;UENO, YUUICHIROU;KITAGUCHI, HIROSHI;ANDOTHERS;REEL/FRAME:015907/0814;SIGNING DATES FROM 20040607 TO 20040610
|Apr 20, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Jul 2, 2015||REMI||Maintenance fee reminder mailed|
|Nov 20, 2015||LAPS||Lapse for failure to pay maintenance fees|
|Jan 12, 2016||FP||Expired due to failure to pay maintenance fee|
Effective date: 20151120