|Publication number||US7301960 B2|
|Application number||US 09/737,510|
|Publication date||Nov 27, 2007|
|Filing date||Dec 15, 2000|
|Priority date||Dec 15, 2000|
|Also published as||US20020075890|
|Publication number||09737510, 737510, US 7301960 B2, US 7301960B2, US-B2-7301960, US7301960 B2, US7301960B2|
|Inventors||Junius A. Kim, Charles E. Alexander|
|Original Assignee||Harris Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Non-Patent Citations (2), Classifications (13), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to time division multiplexed (TDM) communication systems, and more particularly, to control of such TDM systems via communications channels existing between multiple stations in a TDM network.
TDM systems provide a convenient method of transporting multiple channels of digital data via a single physical link. T1 and E1 are two exemplary TDM protocols well known to those in the art. The simplest form of a TDM communication system is a point to point system 10 with two TDM multiplexors 12 electrically coupled by some physical media 14 (e.g., an electrical cable), as shown in
Control of these access components within such networks is typically accomplished by connecting a personal computer or other terminal device 16 to a control port 18 on each access component via a standard communications link such as Ethernet, RS-232 or RS-485. Further, several co-located access components may be daisy-chained together by electrically coupling the respective control ports, thus providing a single access point for control management access.
One disadvantage to providing control to networked access components in this manner is the associated complication and expense, since each access component must include circuitry necessary to implement the interface to the standard communication link. Further, each terminal device 16 must be coordinated so that the control parameters are consistent throughout the network.
Another disadvantage to providing control to networked access components in this manner is the limited extendibility, since standard protocols such as Ethernet, RS-232 or RS-485 typically specify maximum transmission path lengths. Although implementing “repeater” stations in the control path can mitigate this extendibility problem, such repeaters increase the overall expense of the system.
It is an object of the present invention to substantially overcome the above-identified disadvantages and drawbacks of the prior art.
The foregoing and other objects are achieved by the invention which in one aspect comprises a system for transmitting and receiving control data in a TDM communication network. The system includes a single master control source for providing the control data, and one or more slave TDM multiplexors within the TDM communications network, communicating via a TDM signal. Each of the slave TDM multiplexors includes a transmitter component for accepting the control data from the master control source, and inserting the control data into the TDM signal. Each multiplexor also includes a receiver component for extracting the control data in the TDM signal and passing the control data to a local control processor, and a bridging component for passing control data along to the next TDM multiplexor, independent of the local control processor.
In another embodiment, the transmitter component of each of the one or more slave TDM multiplexors receives the control data from the associated receiver component, inserts the control data into the TDM signal, and transmits the TDM signal to one or more TDM multiplexors.
In another embodiment, the transmitter component of each of the one or more slave TDM multiplexors inserts the control data into one or more time slots of the TDM signal. The associated receiver component extracts the control data from the corresponding one or more time slots of the TDM signal.
In another embodiment, the transmitter component of each of the one or more slave TDM multiplexors inserts the control data into a fraction of a time slot of the TDM signal. The associated receiver component extracts the one or more control signals from the corresponding fraction of the corresponding time slot of the TDM signal.
In another embodiment, the TDM communications network includes one or more T1 communications links.
In another embodiment, the TDM communications network includes one or more E1 communications links.
In another embodiment, the TDM communications network is coupled to a second TDM communications network via a secondary communications link, so as to create a sub-network to the TDM communications network.
In another embodiment, the secondary communications link includes an Ethernet communications link.
In another embodiment, the secondary communications link includes an RS-485 communications link.
In another embodiment, the secondary communications link includes an RS-232 communications link.
In another embodiment, the control data network operates in a half duplex mode.
In another embodiment, the first TDM multiplexor operates as a master station, and the remaining TDM multiplexors operate as slave stations. The slave stations transmit only when stimulated by the master station, and only one slave station transmits at any given time.
In another embodiment, the control port includes an Ethernet communications port for communicating with the master control source via an Ethernet protocol.
In another embodiment, the control port includes an RS-232 communications port for communicating with the master control source via an RS-232 protocol.
In another embodiment, the control port includes an RS-485 communications port for communicating with the master control source via an RS-485 protocol.
In another embodiment, the receiver component performs a serial to parallel conversion of the control data, bit shifts the control data so as to form one or more control data octets, and buffers the control data octets for use by the control processor.
In another embodiment, the transmitter component buffers control data octets from the master control source, performs a parallel to serial conversion of the control data, and inserts the control data into predetermined data positions of the TDM signal.
In another embodiment, the TDM communications network includes terminal multiplexors.
In another embodiment, the TDM communications network includes drop-insert multiplexors.
In another aspect, the invention comprises a method of distributing control data in a TDM communications network, from a master control source to two or more TDM multiplexors within the TDM communications network. The method includes receiving one or more control signals from the master control source. The method further includes inserting the one or more control signals into the TDM signal at the first TDM multiplexor, extracting the control signals from the TDM signal at each of the remaining TDM multiplexors, and providing the control signals to an associated TDM multiplexor control processor.
In another embodiment, the method further includes receiving the one or more control signals from the receive interface device at each of the remaining TDM multiplexors, inserting the one or more control signals into the TDM signal, and transmitting the TDM signal to one or more TDM multiplexors.
The foregoing and other objects of this invention, the various features thereof, as well as the invention itself, may be more fully understood from the following description, when read together with the accompanying drawings in which:
The first TDM multiplexor 106 is electrically coupled to a second TDM multiplexor 110 within the network 104, via a transmission line 112 that is capable of supporting a TDM signal. A TDM signal generator 114 within the first TDM multiplexor receives channel data 116 from local data sources, organizes it and inserts it into appropriate time slots so as to generate a TDM signal. The first TDM multiplexor 106 further includes a transmit interface device 118 in the first TDM multiplexor 106 for receiving the one or more control signals from the control port 108, and inserting the control signals into appropriate time position within the TDM signal. In the embodiment shown in
In one embodiment, the transmit interface device 118 inserts the control data into full DS0 time slot that is dedicated to the control signals. In another embodiment, the transmit interface device 118 inserts the control data into multiple DS0 time slots dedicated to the control signals. In yet another embodiment, the transmit interface device 118 inserts the control data into some fraction of a DS0 time slot. In this case, the remainder of the time not used by the control signals may be shared with another data source
The first TDM multiplexor 106 transmits the TDM signal to the second TDM multiplexor 110. The second TDM multiplexor 110 includes a receive interface device 120 (also referred to herein as a receiver component) for extracting the control signals from the TDM signal. The second TDM multiplexor 110 further includes a TDM receiver 122 for receiving the TDM signal and extracting the channel data 116 from the TDM signal and distributing the channel data 116 to the appropriate local destinations. In the embodiment shown in
The system shown in
In the embodiment of the invention shown in
The invention described herein may also be used to form a communications architecture with one or more sub-networks associated with a main network as described in
In the operation of the transmitter 202, when the transmit processor 206 initiates transmit communication data, it switches a first multiplex element 210 and a second multiplex element 212 to write octet data into the transmit FIFO 214. A transmit timing control circuit 218 is synchronized to the TDM framing of the outgoing TDM stream 225. The timing control circuit 218 clocks data from the FIFO 214 and into a parallel-to-serial converter 220. The timing control circuit 218 controls a third multiplexor 222 to multiplex the communication serial bit stream from the converter 220 into the outgoing T1/E1 data stream. The timing control circuit 218 can multiplex data into any DS0 in the TDM data stream for any number of bits per frame, so that the communication data rate and frame position are flexible. The processor 206 can read the depth of the FIFO 214; when the FIFO 214 is close to being emptied, the processor 206 writes data to the FIFO 214 to prevent an underflow condition. The average data rate must remain constant so as to prevent overflow or underflow in the FIFO 214.
In the operation of the receiver 204, a programmable serial delay circuit 224 receives a received T1/E1 data stream 226. The receive processor 208 controls the amount of delay in the delay circuit 224. The delayed serial bit stream 228 is converted into parallel octet data via a serial-to-parallel converter 230 that is controlled by a receive timing control circuit 232. The timing control circuit 232 can clock any DS0 for any number of bits per frame, so the communication data rate and frame position are flexible. The octet data from the serial to parallel converter 230 is clocked into a receive FIFO 234, and the processor 208 reads the octets from the output of the FIFO 234. The processor 208 reads the depth of the FIFO 234, and will continue to read data when the FIFO 234 is near full to prevent an overflow condition.
The communication data can be on any DS0 for any number of bits. The flexible timing circuits 218, 232 can be programmed by the processors to insert/extract the communication bit stream anywhere in the T1/E1 frame for any number of bits. Since the number of bits per frame can be less than an octet, the receiver may not be in octet-alignment at any given time; thus, the receiver must be capable of acquiring octet alignment. The processor 208 analyzes the communication bit stream to detect the octet boundaries, and programs the serial delay circuit 224 to offset the bit stream 228 to ensure that the converter 230 writes octet-aligned data into the FIFO 234. This reduces the processing load on the processor 208, since the processor does not have to continually shift the octet data from the output of the FIFO 234.
The processors can bridge (connect) the receiver 204 directly to the transmitter 202 using the first multiplexor 210 and the second multiplexor 212. The first multiplexor 210 and the second multiplexor 212 (along with the associated electrical conductors that couple these multiplexors to the receiver 204 and the transmitter 202) are referred to herein collectively as the “bridging component.” When bridging, the incoming communication data stream 226 is regenerated and transmitted back out, while the processor 208 continues to read the incoming communication information. While bridging, the FIFOs provide “elasticity” to the incoming and outgoing T1/E1 data streams, so that the data streams do not need to be synchronized in either frequency or frame position with respect to one another. If the T1/E1 data rates are different (incoming relative to outgoing), then the transmit FIFO 214 will eventually overflow or underflow. An overflow or underflow condition does result in a temporary loss of continuity of the communication data stream, but in practice such an interruption is brief, due to the fact that the data rates differ from one another by a small amount. While in this bridging mode, the path of the data communications runs though hardware only, i.e., neither processor is needed to maintain the bridged data flow. Thus, the delay caused by the bridging is primarily a direct function of FIFO size; a small FIFO produces a small delay, and a large FIFO produces a large delay. From an overall network perspective, the delay should be minimized, so preferably the smallest possible FIFOs that still provide the necessary elasticity should be used.
The combination of the LIU 254 and the framer 256 can also generate an outgoing T1/E1 signal when given data, clock and synchronization information.
To communicate with the slave station 252, the master station 250 turns on the transmit framer 256A, and the slave station 252 receives the transmitted data at receive framer 256B. The slave station 252 waits until the master station 250 has completed transmitting, and subsequently responds to commands within the transmission by turning on the transmitter LIU 254C and transmitting response data. When the slave station 252 is not transmitting, the slave receive framer 256B is bridged to the slave transmit framer 254C, so as to create a “loop-back” condition through the slave station 252. The bridging allows the master station 250 to evaluate link circuit integrity and continuity. The master station 250 transmits messages and expects the same messages to be echoed back. Since the master station 250 is not bridged, the messages are terminated at the master station 250, thus preventing the messages from circulating around the loop more than once.
The slave station 252 can decode the received communication data and regenerate that information to a local port, and thus send the information to a station in a sub-network via a link 258 standard using communications protocol such as Ethernet, RS-232 or RS-485. Information regarding control, status, etc., from the sub-network can be transmitted to the slave station 252 via the same link 258, and the slave station 252 transmits the information to the master station 250 via the T1/E1 link.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of the equivalency of the claims are therefore intended to be embraced therein.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4566094 *||May 11, 1983||Jan 21, 1986||At&T Bell Laboratories||Channel selection in a switching system having clustered remote switching modules|
|US5206857 *||Apr 29, 1991||Apr 27, 1993||At&T Bell Laboratories||Apparatus and method for timing distribution over an asynchronous ring|
|US5241543 *||Mar 20, 1991||Aug 31, 1993||Hitachi, Ltd.||Independent clocking local area network and nodes used for the same|
|US5337306 *||Jul 17, 1992||Aug 9, 1994||Adtran Corporation||Digital tandem channel unit interface for telecommunications network|
|US5602841 *||Mar 15, 1995||Feb 11, 1997||International Business Machines Corporation||Efficient point-to-point and multi-point routing mechanism for programmable packet switching nodes in high speed data transmission networks|
|US5684806 *||Jun 20, 1995||Nov 4, 1997||Sony Corporation||Communication apparatus for TDMA system|
|US5768282 *||Mar 11, 1996||Jun 16, 1998||Fujitsu Limited||Node provided with facility for checking establishment of synchronization|
|US5828670 *||Jun 6, 1995||Oct 27, 1998||Symmetricom, Inc.||Distribution of synchronization in a synchronous optical environment|
|US5878044 *||Apr 25, 1996||Mar 2, 1999||Northern Telecom Limited||Data transfer method and apparatus|
|US5935214 *||Oct 14, 1997||Aug 10, 1999||Silicon Systems Gmbh Multimedia Engineering||Method for transmitting source data and control data in a communication system with a ring structure|
|US6108346 *||Mar 13, 1999||Aug 22, 2000||Xiox Corporation||Combined synchronous and asynchronous message transmission|
|US6188699 *||Dec 11, 1997||Feb 13, 2001||Pmc-Sierra Ltd.||Multi-channel encoder/decoder|
|US6278718 *||Aug 29, 1996||Aug 21, 2001||Excel, Inc.||Distributed network synchronization system|
|US6356559 *||May 25, 2000||Mar 12, 2002||At Comm Corporation||Combined synchronous and asynchronous message transmission|
|US6370159 *||Jul 22, 1998||Apr 9, 2002||Agilent Technologies, Inc.||System application techniques using time synchronization|
|EP1041743A2 *||Mar 27, 2000||Oct 4, 2000||Alps Electric Co., Ltd.||TDMA/TDD data communication system with reduction of waiting time between a standby and an active state|
|1||RFL Electronics, Inc., IMUX 2000E, Revised Jul. 1, 1999, Publication No. PI2000, 38 pages.|
|2||RFL Electronics, Inc., The IMUX 2000E, Revised Dec. 1, 2000, Publication No. PI2000, 55 pages.|
|U.S. Classification||370/458, 370/523, 370/527|
|International Classification||H04J3/06, H04J3/08, H04J3/04, H04L12/43, H04J3/12|
|Cooperative Classification||H04J3/08, H04J3/0638, H04J3/047|
|European Classification||H04J3/04D, H04J3/08|
|Dec 15, 2000||AS||Assignment|
Owner name: HARRIS CORPORATION, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, JUNIUS;ALEXANDER, CHARLES A.;REEL/FRAME:011377/0756
Effective date: 20001212
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|Feb 5, 2013||AS||Assignment|
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