|Publication number||US7319065 B1|
|Application number||US 10/637,406|
|Publication date||Jan 15, 2008|
|Filing date||Aug 8, 2003|
|Priority date||Aug 8, 2003|
|Publication number||10637406, 637406, US 7319065 B1, US 7319065B1, US-B1-7319065, US7319065 B1, US7319065B1|
|Inventors||Wen Yu, Paul Raymond Besser|
|Original Assignee||Advanced Micro Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Referenced by (10), Classifications (17), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates, in general, to semiconductor components and, more particularly, to metallization systems in semiconductor components.
Semiconductor component manufacturers are constantly improving the performance of their components while lowering their cost of manufacture. One way manufacturers have reduced costs has been to increase the device density on a single semiconductor wafer by shrinking the device sizes. Although this increases the number of semiconductor components that can be manufactured from a single semiconductor wafer, it also increases the complexity of the manufacturing processes. For example, the metallization systems used in small geometry semiconductor devices comprise contact openings having high aspect ratios, i.e., the ratio of the height of the contact opening to its width. The contact openings are typically lined with a barrier material prior to being filled with a metal such as tungsten or copper. A drawback of these high aspect ratio contact openings is the difficulty in lining the sidewalls near the bottoms of the contact openings. Because the contact openings are not completely lined with a barrier material, the metal filling them may contact the dielectric material from which the contact openings are made. When the metal is tungsten deposited using tungsten hexafluoride as a precursor, the tungsten hexafluoride corrodes the dielectric material. On the other hand, when the metal is copper, copper atoms are capable of diffusing into the semiconductor device thereby contaminating the semiconductor device and causing it to fail. Another drawback of metallization systems having high aspect ratio contact openings is that they require aggressive Chemical Mechanical Polishing (CMP) techniques in which the CMP slurry comprises a highly reactive component in combination with large abrasive materials. The abrasive materials lodge in the contact openings causing the formation of voids during the metal deposition step. The voids increase the resistance of the metallization system and, if large enough, can create electrical opens in the metallization systems, which in turn result in electrical failure of the semiconductor components.
Accordingly, what is needed is a semiconductor component having high aspect ratio contact openings with sufficient liner coverage to preclude device contamination and a method for manufacturing the semiconductor component that mitigates void formation.
The present invention satisfies the foregoing need by providing a semiconductor component having a composite via structure and methods for manufacturing the semiconductor component. In accordance with one aspect, the present invention includes a method for manufacturing a semiconductor component in which a first layer of dielectric material having a via filled with a first electrically conductive material is provided, wherein the via has a first aspect ratio. A second layer of dielectric material is formed over the first layer of dielectric material. A first extension via is formed in the second layer of dielectric material, wherein the first extension via has a second aspect ratio, and wherein a trench is absent from the second layer of dielectric material. The first and second vias cooperate to form a composite via having an enhanced aspect ratio. The first extension via is filled with a second electrically conductive material. The first and second electrically conductive materials may be the same. One or both of the electrically conductive materials may comprise multiple layers.
In accordance with another aspect, the present invention comprises a method for manufacturing a metallization system suitable for use in a semiconductor component. A first layer of dielectric material is provided. A first via is formed in the first layer of dielectric material, wherein the first via has a first aspect ratio. The first via is filled with an electrically conductive material. A second layer of dielectric material is formed over the first layer of dielectric material and a via having a second aspect ratio is formed in the second layer of dielectric material. The via in the second layer of dielectric material is filled with an electrically conductive material that may be the same as the electrically conductive material filling the first via. The first via cooperates with the second via to form a composite via having an enhanced aspect ratio, wherein the enhanced aspect ratio is greater than the first and second aspect ratios.
In accordance with yet another aspect, the present invention comprises a metallization system suitable for use in a semiconductor component comprising a first layer of dielectric material having a first via filled with a first electrically conductive material, the first via having a first aspect ratio. A second layer of dielectric material is disposed over the first layer of dielectric material, wherein the second layer of dielectric material includes a second via having a second aspect ratio and filled with a second electrically conductive material. The first via cooperates with the second via to form a composite via having an enhanced aspect ratio that is greater than the first and second aspect ratios. The first and second electrically conductive materials may be the same.
The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference numbers designate like elements and in which:
Generally, the present invention provides a semiconductor component having high aspect ratio, small dimension, contact openings and a method for manufacturing the semiconductor component. In accordance with an embodiment of the present invention, contact openings having a predetermined aspect ratio, e.g., three to one, are formed in a semiconductor component. The aspect ratio is a ratio of the height of the contact opening to a dimension of the contact opening such as, for example, the width or diameter of the contact opening. The contact openings are subjected to a plasma clean to remove any native oxide that may have formed on the silicide contact regions. Subsequently, the openings are lined with a barrier material and filled with an electrically conductive material such as, for example, titanium or copper. After planarization of the conductive material, a dielectric material is formed over the planarized surface and extension contact openings having a predetermined aspect ratio are formed in the dielectric material. Preferably, the aspect ratios of the extension contact openings are the same as the aspect ratios of the corresponding contact openings. Even more preferably, the widths and aspect ratios of the extension contact openings and the contact openings are substantially the same. The extension contact openings are lined with a barrier material and filled with an electrically conductive material. Then the electrically conductive material is planarized. Because the height of the composite contact structure is increased while the width is maintained at a substantially constant value, the aspect ratio is effectively increased or enhanced. An advantage of the present invention is that the aspect ratio is increased while ensuring adequate coverage by the liner or liner material. In addition, the planarization steps can be carried out using Chemical Mechanical Polishing slurries that are less aggressive than those used for planarization of contact openings having high aspect ratios that are manufactured in a single step.
Source and drain extension regions 132 and 134, respectively, are formed in the portion of substrate 102 adjacent gate structure 126. A source region 142 is formed in the portion of substrate 102 between source extension region 132 and an isolation structure 108 and a drain region 144 is formed in the portion of semiconductor substrate 102 between drain extension region 134 and an isolation structure 108. Spacers 140 are formed adjacent the sidewalls of gate structure 126. Techniques for forming source and drain extension regions, source and drain regions, and spacers are known to those skilled in the art.
Referring now to
Still referring to
After planarization, a layer of dielectric material 161 having a thickness ranging between approximately 100 Å and approximately 5,000 Å is formed on dielectric layer 160. Preferably, dielectric layer 161 has a thickness ranging between approximately 300 Å and approximately 1,000 Å and comprises a single layer of a dielectric material such as, for example, silicon oxynitride (SiON), silicon nitride (SiXNY), silicon rich nitride (SiRN), silicon carbide (SiC), or hydrogenated oxidized silicon carbon material (SiCOH). It should be noted that dielectric layer 161 is not limited to being a single layer system, but can also be a multi-layer system. A layer of photoresist 164 is patterned on dielectric layer 161 to have openings 166 that expose portions of dielectric layer 160. Because dielectric layer 161 lowers the reflection of light during the photolithography steps used in patterning photoresist layer 164, it may also be referred to as an Anti-Reflective Coating (ARC) layer.
Referring now to
A liner 170 having a thickness ranging between approximately 50 Å and approximately 350 Å is formed on major surface 162, sidewalls 168, and the exposed portions of silicided regions 152 and 154. By way of example, liner 170 is a bilayer structure comprising a titanium contact layer having a titanium nitride layer formed thereon. Suitable techniques for forming liner 170 include Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), or the like. Other suitable materials for liner 170 include tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), a tantalum (Ta) and tantalum nitride (TaN) combination, tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), and refractory metal compounds such as refractory metal nitrides, refractory metal carbides, and refractory metal borides. Although liner 170 is shown as being a conformal layer, it should be understood this is not a limitation of the present invention. In addition, the number of layers for liner 170 is not a limitation of the present invention.
Still referring to
Referring now to
A layer of dielectric material 192 such as, for example, silicon nitride having a thickness ranging between approximately 100 Å and 1,000 Å is formed on dielectric layer 160, source electrode 188, and drain electrode 190. A layer of dielectric material 194 having a major surface 197 is formed on silicon nitride layer 192. By way of example, dielectric layer 194 is oxide having a thickness ranging between approximately 2,000 Å and 10,000 Å. A suitable technique for forming layers 192 and 194 is PECVD. However, the method for forming dielectric layers 192 and 194 is not a limitation of the present invention.
An ARC layer 196, similar to ARC layer 161, is formed on dielectric layer 194 and a layer of photoresist 198, similar to photoresist layer 164, is formed on ARC layer 196. Photoresist layer 198 is patterned to form openings 200.
Referring now to
Still referring to
The electrically conductive material is planarized using, for example, a CMP technique having a high selectivity to dielectric layer 194. Thus, the planarization stops on dielectric layer 194. After planarization, portions 204 and 206 of the liner and portions 208 and 210 of the conductive material remain in the openings formed in layers 192 and 194. Portions 204 and 208 cooperate to form an extension 212 of source electrode 188, and portions 206 and 210 cooperate to form an extension 214 of drain electrode 190. It should be understood the planarization technique is not a limitation of the present invention. For example, other suitable planarization techniques include electropolishing, electrochemical polishing, chemical polishing, and chemical enhanced planarization. Dielectric layers 192 and 194 and extensions 212 and 214 cooperate to form a contact layer 199.
Referring now to
An ARC layer (not shown), similar to ARC layer 161, is formed on dielectric layer 218 and a layer of photoresist (not shown), similar to photoresist layer 164, is patterned on the ARC layer. The ARC layer, dielectric layer 218, and silicon nitride layer 216 are anisotropically etched using a reactive ion etch to form via extensions having sidewalls 221. The via extensions are also referred to as extension vias, extension openings, or openings. Preferably, the extension vias are positioned such that they are aligned to and expose source electrode extension 212 and drain electrode extension 214.
The extension vias undergo a pre-clean which removes native oxide that may have formed on source and drain electrode extensions 212 and 214, respectively. Techniques for performing the pre-clean are described with reference to
A liner (not shown) similar to liner 170 is formed on dielectric material 218, source electrode extension 212, drain electrode extension 214, and sidewalls 221. The liner may be formed using the same techniques as those used for forming liner 170 as described with reference to
The electrically conductive material is planarized using, for example, a CMP technique having a high selectivity to dielectric layer 218. Thus, the planarization stops on dielectric layer 218. After planarization, portions 222 and 226 of the liner and portions 224 and 228 of the conductive material remain in the openings formed in layers 216 and 218. Portions 222 and 224 cooperate to form a further extension 232 of electrode 188, and portions 226 and 228 cooperate to form a further extension 234 of drain electrode 190. Extension 232 is coupled to source electrode 188 through source electrode extension 212 and extension 234 is coupled to drain electrode 190 through drain electrode extension 214. It should be understood the planarization technique is not a limitation of the present invention. For example, other suitable planarization techniques include electropolishing, electrochemical polishing, chemical polishing, and chemical enhanced planarization. Dielectric layers 216 and 218 and extensions 232 and 234 cooperate to form a contact layer 219.
In accordance with the embodiments shown and described with reference to
Referring now to
A metallization structure 330 is formed on interconnect layer 302. Metallization structure 330 comprises a dielectric layer 332 having a metal interconnect 336 formed therein. By way of example, metallization structure 330 is formed using a dual damascene process. Thus, interconnect 336 of metallization structure 330 comprises a via 338 and a trench 340 lined with a barrier layer 342. The barrier lined via and trench are filled with copper metal 344. Interconnect 336 transmits electrical signals laterally in semiconductor component 300. An advantage of the embodiment shown in
By now it should be appreciated that a semiconductor component and a method for manufacturing the semiconductor component have been provided. In accordance with the present invention, the aspect ratio of the contact openings can be tailored to be a specified value. For example, the aspect ratio can be three-to-one, four-to-one, five-to-one, etc. Another advantage of the present invention is that it provides a means for manufacturing semiconductor components having contact openings with high aspect ratios that is readily integrable into manufacturing process flows using existing tool sets. The method increases the yields of the semiconductor components without costly process changes. In addition, the planarization steps can be carried out using lower cost, less aggressive CMP slurries. Because the slurries are less aggressive, abrasive particles from the slurries do not become lodged in the contact openings; therefore, voids are not formed and the resistance of the metallization system is not increased. Moreover, the amount of time to planarize the oxide layers is decreased which decreases the volume and cost of CMP slurries.
Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. For example, the dielectric material through which the contact openings are manufactured may be either low dielectric constant or high dielectric constant dielectric material. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.
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|U.S. Classification||438/622, 438/687, 257/E23.145, 438/643, 438/636|
|Cooperative Classification||H01L23/53266, H01L21/76816, H01L23/53295, H01L23/53238, H01L23/5226, H01L2924/0002|
|European Classification||H01L21/768B2L, H01L23/522E, H01L23/532M1R4, H01L23/532M1C4, H01L23/532N4|
|Aug 8, 2003||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU, WEN;BESSER, PAUL RAYMOND;REEL/FRAME:014388/0971;SIGNING DATES FROM 20030627 TO 20030708
|Jun 22, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Jul 1, 2015||FPAY||Fee payment|
Year of fee payment: 8