|Publication number||US7339217 B2|
|Application number||US 11/643,687|
|Publication date||Mar 4, 2008|
|Filing date||Dec 22, 2006|
|Priority date||Sep 28, 2004|
|Also published as||US7259413, US20060071254, US20070120158|
|Publication number||11643687, 643687, US 7339217 B2, US 7339217B2, US-B2-7339217, US7339217 B2, US7339217B2|
|Inventors||Howard E. Rhodes|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (2), Classifications (19), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application is a divisional of U.S. patent application Ser. No. 10/950,927, filed on Sep. 28, 2004, now U.S. Pat. No. 7,259,413 the disclosure of which is incorporated by reference in its entirety.
The present invention relates to the field of semiconductor devices and, in particular, to a pixel cell transistor that improves dynamic range, and provides anti-blooming properties for the cell.
A CMOS imager circuit includes a focal plane array of pixel cells, each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion region, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion region. The imager may also include a transistor for transferring charge from the photosensor to the floating diffusion region and another transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell, for example a four transistor pixel, perform the necessary functions of (1) photon to charge conversion; (2) transfer of charge to the floating diffusion node; (3) resetting the floating diffusion node to a known state before the transfer of charge to it; (4) selection of a pixel cell for readout; and (5) output and amplification of a signal representing a reset voltage and a pixel signal voltage based on the photo converted charges. The charge at the floating diffusion node is converted to a pixel output voltage by a source follower output transistor.
The CMOS imager 108 is operated by the control circuit 150, which controls address decoders 155, 170 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 145, 160 that apply driving voltage to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal Vrst and a pixel image signal Vsig for each pixel are read by sample and hold circuitry 161 associated with the column driver 160. A differential signal Vrst—Vsig is produced and amplified by amplifier 162 and digitized by analog-to-digital converter 175. The analog-to-digital converter 175 converts the analog pixel signals to digital signals, which are fed to an image processor 180 to form and output a digital image.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
A schematic diagram of an exemplary CMOS three-transistor (3T) pixel cell 10 is illustrated in
A schematic diagram of an exemplary CMOS four-transistor (4T) pixel cell 20 is illustrated in
A capacitor may also be connected to the floating diffusion node in order to increase the storage capacity as shown in
Image sensors, such as an image sensor employing the conventional pixel cells 10, 20, 200 of
The electrical dynamic range for an image sensor is commonly defined as the ratio of its largest non-saturating signal to the standard deviation of the noise under dark conditions. The electrical dynamic range is limited on an upper end by the charge saturation level of the sensor, and on a lower end by noise imposed limitations and/or quantization limits of the analog to digital converter used to produce the digital image. When the light dynamic range of an image sensor is too small to accommodate the variations in light intensities of the imaged scene, e.g. by having a low light saturation level, the full range of the image scene is not reproduced. The illumination-voltage profile of the conventional pixels 10, 20 is typically linear as shown in
When the incident light captured and converted into a charge by the photosensor during an integration period is greater than the capacity of the photosensor, excess charge may overflow and be transferred to adjacent pixels. This undesirable phenomenon is known as blooming, or charge cross talk, and results in a bright spot in the output image.
Another problem of image sensors is that the reset gate adjacent to the photosensor in three-transistor (3T) pixels or the transfer gate adjacent to the photosensor in four-transistor (4T) pixels tend to leak, creating signal loss from the photosensor during the integration period. Independent of the dynamic range problem, a substantial effort is being made in the art of image sensors to reduce or eliminate off-state leakage of adjacent transistors to minimize signal loss.
Thus, there is a desire and need for a pixel cell having improved saturation response and lower potential for blooming while benefiting from the leaky property of transistors.
Exemplary embodiments of the invention provide a pixel cell capable of reaching a higher level of illumination before its maximum output voltage is reached. The pixel cell has controlled photosensor leakage. Exemplary embodiments of the present invention drain some of the charge generated by the photosensor away from the photosensor during an integration period through a transistor adjacent to the photosensor acting as a high dynamic range (HDR) transistor. The HDR transistor may be a “leaky” reset transistor in the case of a 3T pixel, a “leaky” transfer gate in the case of a 4T pixel, or it may be an additional anti-blooming transistor adjacent to the photosensor in the case of a 4T or 5T pixel as described in U.S. patent application Ser. No. 10/881,525 (M4065.0955, filed Jul. 1, 2004) to Rhodes. This prevents the photosensor from becoming over-saturated and excess charges from overflowing to adjacent pixels.
Embodiments employing the novel HDR transistor of the invention alters the pixel output signal characteristic curve and can increase the dynamic range of the pixel cell.
The HDR transistor may also be used as a global shutter gate, which enables independent resetting of the photosensor. The HDR transistor, as an additional anti-blooming transistor, may have the same doping profile as a transfer gate or reset gate of a pixel cell. However, if the transistor is used as a global shutter, it may be desirable that it have a doping profile resembling a transfer gate.
In all embodiments of the invention, the extent to which leakage occurs through the HDR transistor may be controlled by modifying the implant conditions around the transistor, the channel length, the thickness of the gate oxide on the transistor, the off-state voltage of the transistor, any other method of creating leakage through a transistor, modifying the location of the HDR transistor with respect to the photo sensor, and/or any combination of the aforementioned methods of controlling leakage.
These and other features and advantages of the invention will be better understood from the following detailed description, which is provided in connection with the accompanying drawings, in which:
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.
The term “substrate” is to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium arsenide.
The term “pixel” refers to a picture element unit cell containing a photosensor and transistors for converting light radiation to an electrical signal. For purposes of illustration, a representative pixel is illustrated in the figures and description herein and, typically, fabrication of all pixels in an imager will proceed simultaneously in a similar fashion.
Referring now to the drawings, where like elements are designated by like reference numerals,
In one operational aspect, the leaky reset transistor 32′ operates by creating a “knee” in the illumination-voltage profile of the device, increasing the light dynamic range of the pixel.
In another operational aspect, the reset transistor 32′ also acts as a shutter gate or anti-blooming gate. During an integration period of the photosensor 26, the reset transistor 32′ may have a gate voltage above 0.0 V applied to it during an integration period to allow a small amount of charge to leak through to the array pixel supply voltage Vaa-pix. At the end of the integration period (during signal readout), a voltage greater than the threshold voltage Vt of the transistor is applied to it for a short pulse period, allowing any residual charge to be drained out of the photosensor, through the reset transistor 32′, and into a charge collection region.
Prior to integration of charge in the photodiode, the reset transistor 32′ may be turned on by applying a voltage to the reset transistor 32′ which is greater than the Vt of the reset transistor 32′. In this manner charge can be drained out of the photodiode. At the start of the integration period, the reset transistor 32′ is turned off, allowing charge to accumulate in the photodiode. In this manner, the reset 32′ transistor can act as a global shutter, thus each reset transistor in a pixel controlling the integration of its associated photodiodes and this control may be expected globally throughout a pixel array.
The reset transistor 32′ is then turned off to allow integration of the photo-generated charge. If the off-voltage applied to the reset transistor 32′ is at 0.0 V or a positive voltage, typically less than the Vt of the reset transistor 32′, then this transistor also acts as an anti-blooming gate. That is, under high illumination conditions, the photodiode will fill with charge and excess charge will drain through the reset transistor 32′ to the Vaa-pix.
The reset transistor 32′ may have a size and doping profile which is tailored to leak and also operates in a known manner when fully turned on to reset floating diffusion node 28 as described above.
The doping profile of a reset transistor of a conventional pixel may include a “punch-through” protection implant on both sides, which minimizes leakage across the transistor and allows it to maintain better control of its channel. The doping profile of a conventional reset transistor may also include a single lightly doped implant on both sides of the gate. In a conventional pixel cell, the reset transistor may also have a symmetrical channel with either single lightly doped implants or punch-through protection implants on both sides of the gate stack. Alternatively, the reset transistor may have an asymmetrical channel with a single lightly doped implant on one side of the gate stack and a punch-through protection implant on the other side of the gate stack. All of these features are typically provided to prevent leakage from the photosensor 26. A conventional 3T pixel also contain a source follower transistor 34 and a row select transistor 36. The 3T pixel 10′ of the present invention also has a photosensor 26, source follower transistor 34, and a row select 36, which operate in a conventional manner.
However, according to the present invention, a certain amount of charge leakage from the photosensor is permitted since over-saturation of the photosensor is a problem of greater concern. Therefore, at least some of the leakage-prevention features mentioned above and associated with reset transistors are eliminated such that the transistor is capable of draining charge away from the photosensor.
In addition, other features of a typical reset transistor may be altered to enhance leakage across the gate. Additionally, a source terminal of the reset transistor 32′ may be connected to the array pixel voltage. Vaa-pix and is designed to permit leakage from the photosensor 26 when the photosensor 26 is at or near saturation. The degree of leakage can be controlled by tailoring the leakage and/or threshold voltage characteristics of transistor 32′.
In a conventional pixel cell, the transfer gate may also have an asymmetrical channel with either a single lightly doped implant or a punch-through protection implant on one side of the gate stack. All of these features are typically provided to prevent leakage from the photosensor 26. A conventional 4T pixel also contains a reset gate 32, source follower transistor 34 and a row select transistor 36. The 4T pixel 20′ of the present invention also has a photosensor 26, source follower transistor 34, and a row select 36, which operate in a conventional manner. Similarly, the 4T pixel 200′ (
The length of the channel L1 is about 0.3 μm to about 0.7 μm. This channel length is optimized such that it is short enough to allow the converted charge to transfer to the output circuitry at the end of an integration period, but distances the photoconversion device 26 from the floating diffusion region 28 or readout circuitry to minimize the off-state leakage. Another aspect of the channel is the proximity of lightly-doped drain and source/drain implants S/D to the ends of the channel L1. It should be noted that in order to minimize leakage, these lightly-doped drain and source/drain implants S/D are, at closest, outside of the channel.
In the embodiments illustrated in
In another embodiment of the present invention, a transistor performing the specific function of extending the dynamic range of the pixel cell, i.e., a high dynamic range (HDR) transistor, is added instead of being made out of the reset or transfer transistors. Therefore, both a reset gate/transfer gate and a high dynamic range transistor are coupled to the photoconversion device to leak charges away from the photoconversion device. In
Conventional processing steps may be employed to form contacts and wiring to connect transistor gate and source and drain regions of the pixel cell of the present invention. For example, the entire surface may be covered with a passivation layer of, e.g., silicon dioxide, BSG, PSG, or BPSG, which is then planarized by chemical mechanical polishing. The passivation layer may then be etched to provide contact holes which are then metallized to provide contacts to the reset gate, transfer gate, source/drain regions and other pixel structures, as needed. Conventional multiple layers of conductors and insulators to other circuit structures may also be used to interconnect the internal structures of the pixel sensor cell and to connect the pixel cell structures to other circuitry associated with the pixel array.
Four (4T) and five-transistor (5T) pixels of the present invention can be used in a pixel array 100 of the imager device 108 illustrated in
System 2000 includes a central processing unit (CPU) 2002 that communicates with various devices over a bus 2004. Some of the devices connected to the bus 2004 provide communication into and out of the system 2000, illustratively including an input/output (I/O) device 2006 and imager device 108. Other devices connected to the bus 2004 provide memory, illustratively including a random access memory system (RAM) 2010, FLASH memory or hard drive 2012, and one or more peripheral memory devices such as a floppy disk drive 2014 and compact disk (CD) drive 2016. Any of the memory devices, such as the FLASH memory or hard drive 2012, floppy disk drive 2014, and CD drive 2016 may be removable. The imager device 108 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, in a single integrated circuit. The imager device 108 may be a CCD imager or CMOS imager constructed in accordance with any of the illustrated embodiments.
The above description and drawings are only to be considered illustrative of exemplary embodiments which achieve the features and advantages of the invention. Modification of, and substitutions to, specific process conditions and structures can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6040570||May 29, 1998||Mar 21, 2000||Sarnoff Corporation||Extended dynamic range image sensor system|
|US6101294||Jun 2, 1997||Aug 8, 2000||Sarnoff Corporation||Extended dynamic imaging system and method|
|US6441852||Feb 4, 2000||Aug 27, 2002||Sarnoff Corporation||Extended dynamic range image sensor system|
|US6472653||Mar 20, 2000||Oct 29, 2002||Sarnoff Corporation||Method and apparatus to extend dynamic range of time delay and integrate charge coupled devices|
|US7102184||Oct 29, 2003||Sep 5, 2006||Micron Technology, Inc.||Image device and photodiode structure|
|US20050179072||Apr 11, 2005||Aug 18, 2005||Rhodes Howard E.||Isolation region implant permitting improved photodiode structure|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8184188||Mar 12, 2009||May 22, 2012||Micron Technology, Inc.||Methods and apparatus for high dynamic operation of a pixel cell|
|US20100231771 *||Mar 12, 2009||Sep 16, 2010||Micron Technology, Inc.||Methods and apparatus for high dynamic operation of a pixel cell|
|U.S. Classification||257/292, 257/E27.131, 257/E27.132, 257/291, 257/E31.037|
|Cooperative Classification||H04N5/3559, H01L27/14603, H01L27/14609, H04N5/35527, H04N5/37452, H04N5/374, H04N5/3591, H01L31/035272|
|European Classification||H01L27/146A4, H04N5/355A2, H04N5/3745A, H04N5/359A, H04N5/355C|
|Aug 3, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Aug 25, 2015||FPAY||Fee payment|
Year of fee payment: 8
|Nov 16, 2016||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RHODES, HOWARD E.;REEL/FRAME:040346/0118
Effective date: 20040920
|Dec 6, 2016||AS||Assignment|
Owner name: APTINA IMAGING CORPORATION, CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:040823/0001
Effective date: 20080926