|Publication number||US7351660 B2|
|Application number||US 10/256,334|
|Publication date||Apr 1, 2008|
|Filing date||Sep 26, 2002|
|Priority date||Sep 28, 2001|
|Also published as||US20030112576|
|Publication number||10256334, 256334, US 7351660 B2, US 7351660B2, US-B2-7351660, US7351660 B2, US7351660B2|
|Inventors||Peter D. Brewer, Carl W. Pobanz|
|Original Assignee||Hrl Laboratories, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (43), Non-Patent Citations (24), Referenced by (49), Classifications (37), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present document is related to the copending and commonly assigned patent application documents entitled: “Process for Producing High Performance Interconnects,” Ser. No. 60/326,054; “Process for Assembling Three-Dimensional Systems on a Chip and Structure Thus Obtained,” Ser. No. 60/326,076; “Method For Assembly Of Complementary-Shaped Receptacle Site And Device Microstructures,” Ser. No. 60/326,055; and “Method of Self-Latching for Adhesion During Self-Assembly of Electronic or Optical Circuits,” Ser. No. 60/326,056, all of which were filed on Sep. 28, 2001. The contents of these related applications are hereby incorporated by reference herein.
The present invention relates to processes for producing electrical interconnects, and, more particularly, processes for producing high performance transmission lines and interconnects between integrated circuits, discrete devices, and passive components in highly integrated three-dimensional structures.
2. Description of Related Art
Increasingly complex electronic systems require increasingly denser structures of integrated circuits, passive components, and other discrete elements. Typical two-dimensional structures, where the elements are laid out on a printed circuit board or similar structure, no longer meet the size, weight, and performance requirements of advanced electronic systems. Hence, three-dimensional structures are being used to provide the needed levels of electronic circuit integration. These three-dimensional structures generally comprise multiple layers of devices along with multiple layers of interconnects to provide electrical connections between the devices.
One approach for providing interconnects in a multiple layer structure is that used in high-density multilayer interconnect (HDMI) techniques. J. L. Licari and D. J. Smith in U.S. Pat. No. 5,485,038, issued Jan. 16, 1996, describe an HDMI structure using alternating conductor metallization and insulating layers. Licari, et al. disclose dielectric layers formed by curtain coating of ultraviolet photoimageable epoxy material and conductor layers formed on the dielectric layers by thin film printing, sputtering or plating. Vertical interconnects (vias) are formed through the dielectric layers to interconnect the metallization pattern on adjacent conductor layers.
The conventional polyimide materials used for RF packaging are not photoimageable. Thus, the metallization patterns and interlayer vias must be formed by photolithography, which typically involves applying, imaging, developing and removing a photoresist layer for each metallization and dielectric layer. Many process steps are thereby required for each layer. Plasma etching using photoresist is generally used to form the interconnect structures.
Plasma etching methods are limited in their ability to produce complex structures and are also restricted by practical considerations in the vertical depth of the features (a few microns). The depth restriction is due to the low etch rates of most plasma etching schemes for etching polymers (<3000 Å/min) and the lack of robust material masking. Complex structures such as via holes with tapered sidewalls, terraced structures or asymmetrically shaped features are also difficult to produce using plasma etching. Some laboratories have reported forming via holes in polyimide polymer films with sloped sidewalls. The method employed uses tapered erosion masks to obtain sloped etch features, but is limited in the range of sidewall angles and the depth of the etched features. Producing asymmetric structures (i.e., different sidewall profiles) is beyond the capability of current plasma etching technology.
S. Y. Chou in U.S. Pat. No. 5,772,905, “Nanoimprint Lithography,” issued Jun. 30, 1998, describes a process for molding structures in thermoplastic polymer film to create ultra-fine structures on or in a substrate. Chou discloses a nanoimprint process that presses a mold into the polymer film to form holes and trenches with high aspect ratios in structures less than 25 nanometers. The mold may consist of a thick layer of silicon dioxide on a silicon substrate and is patterned using electron beam lithography, reactive ion etching (RIE), and other methods. To form the vias and trenches, the mold is pressed into polymethylmethacrylate (PMMA) film spun on a silicon wafer. RIE is used to remove PMMA residue from the bottom of the molded via and trench regions. The vias and trenches are then metalized by using an evaporation technique. Alternatively, the molded and etched film may be used as a mask to support the formation of recesses in the substrate by an etching process. The recesses in the substrate can then be used to support further processing steps.
The techniques disclosed by Chou address the creation of two-dimensional ultra-fine structures on or in a substrate. However, there exists a need in the art for the creation of three-dimensional structures in multiple layers at or above a substrate. There also exists a need in the art for creating interconnection structures in dielectric materials to provide for connections between layers in a multiple layer structure using a minimum number of steps for the process. Furthermore, there exists a need in the art for a process that provides for the creation of complex interconnection structures such as tapered sidewalls, terraced structures, or asymmetrically shaped features in multiple layer structures.
It is an object of the present invention to provide a method for forming high performance interconnections in a three-dimensional structure. It is a further object of the present invention to provide a method for the creation of complex interconnection structures such as tapered sidewalls, terraced structures, or asymmetrically shaped features in multiple layer structures. The term “high performance interconnection” is used herein to refer to any electrical interconnection that supports the connection of high speed signals, such as radio frequency signals or digital signals with fast rise and fall times, among components without detrimentally affecting the quality of the signal.
One embodiment of the present invention provides a method for producing high performance electrical interconnections in a three-dimensional semiconductor structure, comprising the steps of: applying a dielectric film to a top portion of the three dimensional semiconductor structure; providing a stamp substrate; etching the stamp substrate to create a stamp pattern with raised areas; aligning the stamp substrate to the dielectric film; imprinting the dielectric film with the stamp pattern on the stamp substrate so as to create via regions and trench regions in the dielectric film; removing residual film from the via and trench regions of the dielectric film; and metallizing the via and trench regions of the dielectric film.
Another embodiment of the present invention provides a method for producing high performance electrical interconnections in a three dimensional semiconductor structure, comprising the steps of: providing a stamp substrate; etching the stamp substrate to create a stamp pattern with raised areas; providing a dielectric film; aligning the stamp substrate to the dielectric film; imprinting the dielectric film with the stamp pattern on the stamp substrate so as to create via regions and trench regions in the dielectric film; aligning the dielectric film to a top portion of the three dimensional semiconductor structure; bonding the dielectric film to the three dimensional semiconductor structure; removing residual film from the via and trench regions of the dielectric film; and metallizing the via and trench regions of the dielectric film.
Other embodiments of the present invention provide methods for forming high performance interconnects such as coplanar interconnects, coaxial waveguides, shielded, horizontal transmission lines, or electrical structures such as external resonators or spiral inductors. These interconnects and structures may be formed by stamping dielectric layers and metallizing those layers as described herein. Those skilled in the art would understand that structures other than those specifically described herein may also be fabricated using methods according to the present invention.
The purpose of the present invention is to provide a process for producing vertical and horizontal electrical interconnects to be utilized in a three-dimensional structure, such as the three-dimensional structure shown in
The process of the present invention is provided by stamping uniquely shaped through-layer via holes and recesses that serve as structural pre-forms for metallization of complex interconnect structures. The method uses master stamps fabricated from semiconductor materials that provide a low cost means to produce arrays of precisely shaped recesses in polymer films. The stamp pattern is fabricated using standard IC processes, including photolithography, wet chemical etching and/or dry etching techniques. A wide variety of sidewall shapes and angles can be obtained by employing different etching procedures and/or by selecting different crystallographic orientations and masking procedures on the stamp face. The stamping process is capable of forming micron-size structures with high aspect ratios (˜100:1) and can produce features down to 10 nanometers. The present invention represents a major departure from conventional methods for fabricating multiple layer interconnects, which are limited in the complexity and size of possible pre-form structures. Embodiments of the present invention provide an entirely new class of RF and high-speed digital interconnects for highly integrated 3-D systems-on-a-chip, offering improved performance, simplified fabrication, and reduced cost.
One embodiment of the process for producing high performance interconnects is illustrated in
Stamp patterns may be formed on any material that is harder than the material that is to be imprinted with the stamp. Accordingly, a stamp pattern may be formed in a silicon dioxide layer deposited on a substrate by using semiconductor fabrication techniques. A stamp pattern may also be formed by recasting a formed exotic material into a metal stamp. However, non-crystalline materials such as silicon dioxide cannot be crystallographically etched and may be limited in the range of available patterns that can be shaped in such non-crystalline materials. Therefore, formation of a stamp pattern directly on single crystal silicon is preferred.
As shown in
In a first embodiment of the present invention, a dielectric film is applied to a substrate before the film is stamped.
After the dielectric layer 210 is applied to the substrate 290, the stamp wafer 200 containing the stamp pattern 201 is aligned to the substrate 290 with the dielectric layer 210. The stamp wafer 200 and the substrate wafer 290 are preferably registered to one another using a commercially available alignment tool with front-to-back alignment capability. The tool should have 0.5-1.0 μm accuracy for wafer-to-wafer alignment. The wafers are preferably fixed in position to one another using a bonding tool, such as the one used with the EV501 wafer bonding machine from EV Group, Inc. of Schaerding, Austria. The bond tool with the wafers is next transferred into a hot embossing machine to produce imprinted structures.
After the imprinting process, the stamp wafer 200 and the host substrate 290 with the now-stamped dielectric layer 210 are separated. If curing of the layer 210 is required, the host substrate 290 with the dielectric layer 210 may then be baked at a temperature sufficient to harden the material or the dielectric layer 210 may be exposed to Ultra-Violet light if photo-curing is needed. Alternatively, the dielectric layer 210 may be left to cool and harden.
The molding process will generally leave a portion of residual film at the bottom of the imprinted via and trench regions as shown at the bottom of the via regions 211 in
The interconnect regions are then metallized as shown in
Formation of multiple interconnect layers according to this first embodiment of the present invention is accomplished by repeating the steps described above and shown in
Removal of the second stamp wafer 250 exposes via regions 231 and interconnect trench regions 233 in the second dielectric layer 230 as shown in
In an alternative embodiment of the process described above, commercially available sheets of polymer dielectric film may be used to provide the dielectric layers to be molded by stamp wafers. Rather than using a spin-on process to form each dielectric layer, a sheet of polymer dielectric film is positioned and bonded to a host substrate (or an underlying dielectric layer). The dielectric film is then molded as described above. Using sheets of polymer dielectric film with decreasing glass transition temperatures, i.e., temperatures at which the film can be molded, allows the upper layers to be molded without affecting the lower layers.
Another embodiment of the process for producing high performance interconnects according to the present invention is illustrated in
As shown in
The embossing machine performs the required molding process for the separate dielectric film 310 using temperatures and pressures similar to those used for molding the dielectric layer on the substrate described above. After stamping and separation of the stamp wafer 300 from the dielectric film 310, the dielectric film 310 is allowed to cool and harden into its final form. Since the dielectric film 310 is fully polymerized, a curing step may not be required. The thermoplastic properties of the materials used for the dielectric film 310 allows the film 310 to be reversibly softened and hardened by heating above and cooling below the glass transition temperature of the materials.
After the polymer residue 313 is removed, metallization of the interconnect regions 311, 312 occurs.
High-performance interconnections are essential for horizontal transport of DC and RF signals among embedded circuits within a layer and for vertical connectivity between layers in a multiple layer structure. The multiple layers of metallized dielectrics of the present invention enable the creation of a wide variety of transmission lines and interconnects. Such structures include conductors with one or two ground planes (microstrip and stripline, respectively), coplanar strips (CPS) and three-conductor coplanar waveguide (CPW). These transmission lines are used extensively in MMICs and conventional RF printed circuits. Using low-loss dielectrics and mode suppression techniques developed for millimeter-wave MMICs and subsystems, operation at frequencies up to 100 GHz will be practical. The vertical dimension adds another degree of freedom through which shielded structures such as coaxial lines and transmission line vias can be formed, as illustrated in
The present invention can be used to provide complex interconnects of various shapes and functions.
For example, as illustrated in
Coaxial connections can also be provided by the present invention as shown in
Metal, such as gold, titanium/gold, or other such conductors, is then deposited into the center conductor recess 552 and the coaxial ground shield recess 551 to form the lower layer portion of the center conductor vertical interconnect 512 and the ground shield 511, as shown in
Shielded horizontal transmission lines can be provided by the present invention as shown in
One method for forming the shielded horizontal transmission line structure depicted in
A middle polymer layer 655 is then deposited on top of the lower ground shield 620 and a stamp 900 is prepared for stamping the required structures in the middle polymer layer 655, as shown in
The vertical shield recesses 631 and the horizontal interconnect recesses 611 are then metalized as shown in
Etching is then used to remove the polymer material above the horizontal interconnects 610 to provide upper interconnect recesses 609, as shown in
Due to the lossy nature of silicon substrates, external resonators are needed for improving the RF performance of Si circuits.
Similarly, the present invention provides the capability to produce a horizontal spiral inductor, as shown in
From the foregoing description, it will be apparent that the present invention has a number of advantages, some of which have been described above, and others of which are inherent in the embodiments of the invention described herein. Also, it will be understood that modifications can be made to the process for producing high performance interconnects described herein without departing from the teachings of subject matter described herein. As such, the invention is not to be limited to the described embodiments except as required by the appended claims.
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|US20130161831 *||Feb 20, 2013||Jun 27, 2013||Samsung Electronics Co., Ltd.||Three-dimensional semiconductor devices|
|U.S. Classification||438/689, 438/700, 438/703, 216/44, 216/52|
|International Classification||H02H1/00, H01L21/302|
|Cooperative Classification||H01L2924/14, H01L2924/12042, B82Y40/00, B82Y10/00, G03F7/0002, H01L23/552, H01L2924/01078, H01L2924/01033, H01L2924/01006, H01L2924/01024, H01L2924/10329, H01L2924/19104, H01L2924/10335, H01L24/82, H01L25/50, H01L2924/10253, H01L2924/01079, H01L25/18, H01L2924/01049, H01L2924/13064, H01L2924/09701, H01L2924/01013, H01L2224/24145, H01L2924/01005, H01L24/24, H01L2924/1423, H01L2924/10271, H01L2224/82047|
|European Classification||H01L24/82, H01L24/24|
|Apr 8, 2003||AS||Assignment|
Owner name: HRL LABORATORIES, LLC, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BREWER, PETER D.;POBANZ, CARL W.;REEL/FRAME:013947/0669
Effective date: 20021206
|Sep 20, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Sep 23, 2015||FPAY||Fee payment|
Year of fee payment: 8