|Publication number||US7354837 B2|
|Application number||US 11/217,369|
|Publication date||Apr 8, 2008|
|Filing date||Sep 2, 2005|
|Priority date||Jul 12, 2005|
|Also published as||US20070015324|
|Publication number||11217369, 217369, US 7354837 B2, US 7354837B2, US-B2-7354837, US7354837 B2, US7354837B2|
|Inventors||Chao-Hsi Chung, Chu-Chun Hu, Chih-Cheng Wang|
|Original Assignee||Promos Technologies Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (4), Referenced by (2), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates in general to a fabrication method for a semiconductor device. More particularly, it relates to forming gate spacers in an array area and a peripheral area.
2. Brief Discussion of the Related Art
MOSFETs have been continuously scaled down to gain improved device density, operating performance, and reduced fabrication cost for integrated circuits (ICs). With MOSFET channel length decreased, the gate of the MOSFET is barely able to switch off the conductive channel thereunder. This phenomenon is known as the short channel effect, which is especially significant when a MOSFET has a channel length less than 0.13 um.
In a dynamic random access memory (DRAM), for example, shrinkage of memory cells in array areas yields higher device density, better production efficiency, and lower product cost. This shrinkage, however, also enlarges the short channel effect on the transistors in peripheral areas, easily causing peripheral circuit to malfunction.
Therefore, novel technologies are needed for accommodating cells both in array and periphery areas to downsized memories.
A fabrication method for a semiconductor device is provided. A substrate has an array area and a peripheral area. The array area comprises a first gate and the peripheral area comprises a second gate. A first isolation layer is formed to cover the first gate, the second gate and the substrate. A second isolation layer is formed to cover the first isolation layer. The second isolation layer is made of a material different from the first isolation layer. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer at the sidewalls of the first gate are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
The present invention will become more fully understood from the following detailed description and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present application, and in which:
The substrate 100 has an array area 102 and a peripheral area 104. Generally, memory cells are positioned in the array area 102 while logic control circuits are positioned in the peripheral area 104. Gates 106 are in array area 102 and gates 108 are in peripheral area 104. A gate is a major part of a MOSFET and can have a stacked structure comprising a gate dielectric layer 110, a gate electrode 112 and a gate cap layer 114. The gate dielectric layer 110 can be silicon oxide, silicon nitride, high-k isolation material, or the like. The gate electrode 112 can be polysilicon, silicide, metal, or the like. The gate cap layer 114 can be silicon nitride, or other dielectric material.
As shown in
Accordingly, following the sequence from
In this embodiment, the isolation layers 116 and 118 comprise different materials, such that, by way of an etching process with a high etching selectivity, the remaining isolation layer 116 a, i.e. the single spacers on the sidewalls of the gate 106 in the array area 102, can be thin, thus the memory dimensions can be scaled down and device density in the array area 102 can be increased. Furthermore, dual spacers 122, each thicker than a single spacer, are formed on the sidewalls of the gate 108 in the peripheral area 104, solving problems arising from the short channel effect.
While the invention has been described by way of an example and in terms of preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6197632 *||Nov 16, 1999||Mar 6, 2001||International Business Machines Corporation||Method for dual sidewall oxidation in high density, high performance DRAMS|
|US6500765 *||Mar 23, 2001||Dec 31, 2002||United Microelectronics Corp.||Method for manufacturing dual-spacer structure|
|US6727543 *||Oct 31, 2002||Apr 27, 2004||Yung-Chang Lin||Method for fabricating a memory structure having required scale spacers|
|US6737308 *||Jun 14, 2002||May 18, 2004||Samsung Electronics Co., Ltd.||Semiconductor device having LDD-type source/drain regions and fabrication method thereof|
|1||Chung, "Dual GC Spacer Process Flow", ProMOS DIT 1-T3, Nov. 12, 2004, pp. 1-6.|
|2||*||Williams, K.R., Gupta, K.; "Etch Rates for Micromachining Processing", Journal of Microelectromechanical Systems, vol. 5, No. 4, Dec. 1996.|
|3||*||Williams, K.R., Gupta, K.; "Etch Rates for Micromachining Processing-Part II", Journal of Microelectromechanical Systems, vol. 12, No. 6, Dec. 2003.|
|4||*||Wolf. S., Tauber, R.N.; Silicon Processing for the VLSI Era vol. 1-Process Technology; Lattice Press; 2000.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20100062592 *||Sep 9, 2008||Mar 11, 2010||Tokyo Electron Limited||Method for forming gate spacers for semiconductor devices|
|US20140353729 *||May 29, 2013||Dec 4, 2014||United Microelectronics Corp.||Semiconductor structure and method for forming the same|
|U.S. Classification||438/303, 257/E29.255, 438/595, 257/E21.626|
|Cooperative Classification||H01L29/6656, H01L21/823468, H01L29/6653, H01L29/78|
|European Classification||H01L29/66M6T6F6, H01L29/66M6T6F10, H01L21/8234S|
|Sep 2, 2005||AS||Assignment|
Owner name: PROMOS TECHNOLOGIES INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUNG, CHAO-HSI;HU, CHU-CHUN;WANG, CHIH-CHENG;REEL/FRAME:016952/0902
Effective date: 20050801
|Aug 10, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Aug 31, 2015||FPAY||Fee payment|
Year of fee payment: 8