|Publication number||US7362905 B2|
|Application number||US 10/930,875|
|Publication date||Apr 22, 2008|
|Filing date||Aug 31, 2004|
|Priority date||Aug 31, 2004|
|Also published as||CN1744715A, CN100405849C, US20060045359|
|Publication number||10930875, 930875, US 7362905 B2, US 7362905B2, US-B2-7362905, US7362905 B2, US7362905B2|
|Inventors||Hong-Hui Chen, Chung-Yen Lu, Chi-Hui Huang|
|Original Assignee||Mediatek Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (1), Classifications (24), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to digital video (DV), and more specifically, to methods and systems for DV encoding and decoding.
Digital video (DV) has became a popular technology, and as with most developing technologies, products thereof are now affordable to average consumers. DV markets have expanded exponentially, and digital cameras are one of the most popular products. One inherent impasse of the digital camera is conversion and reconversion of a mass amount of video data that represents the recorded digital images to a computer system such that the user of the computer system can manipulate, transfer, or store the digital images. The process of transferring video data into a digital format for online distribution or recording to disc is called encoding, and the recovery operation decoding. Sophisticated encoding techniques have been developed to encode and compress digital information into ever smaller space for convenience. Common digital image encoding techniques include JPEG, MPEG, and DV encoding technique. DV encoding is a more efficient method since it generates variable length coding (VLC) to encode as much data into as little space as possible without losing detailed information.
Variable length coding (VLC) distributes coded data throughout a fixed encoded data structure. In the context of the DV specification, a PAL system employs a video frame containing 1620 macro blocks, whereas an NTSC system employs a video frame containing 1350 macro blocks. Each macro block comprises four luminance (Y) discrete cosine transformation (DCT) blocks, and two chrominance (Cr and Cb) DCT blocks. The total picture elements in a video frame are divided into 60 super blocks for PAL, and 50 super blocks for NTSC. Each super block consists of 27 macro blocks. Furthermore, a video segment comprises 5 macro blocks from various areas within the video frame. The macro blocks in the video frame are shuffled by forming video segments. On average, each macro block is compressed from 384 to 77 bytes. This shuffling process averages out the frequency characteristics of the data and hence reduces the degree of difficulty of compression.
Three well known DV formats, MiniDV, DVCAM, and DVCPRO all utilize DV encoding (or DV compression). The compression ratio is 5:1, and the data rate is fixed at 25 Mbps, such that DV compression is consistent and file size does not vary as a file is recorded or played back. DV compression uses intraframe discrete cosine transform (DCT) compression to reduce the size of the file being recorded. Each individual frame is compressed and there is no reliance on adjacent frames for color or other data.
The VLD decoding procedure performed in the VLD module 42 is illustrated by the flowchart of
In an embodiment of the invention, an encoding method for a DV encoder acquires DV data, skipping a next or remaining pass encoding stage(s) if necessary. In the 3-stage (or 3-pass) encoding process, where the bandwidth of shared DRAM is carefully monitored, a skip command can be issued by a microprocessor, a dynamic random access memory (DRAM) controller via a physical link. To inform the DV encoder of shared resource insufficiency, in mode 0, the status of the DRAM controller is monitored by or reported to the microprocessor, and the microprocessor issues a skip command if the system resources of the DRAM are occupied, for example, when the DRAM bandwidth utilized by the system exceeds a critical level. Mode 1 further reduces loading on the microprocessor, wherein a physical link exists between the DRAM controller and the DV encoder for reporting of DRAM bandwidth status by passing a skip command. The microprocessor issues a skip command when detecting a fast forward or fast rewind operation in an external DV device connected to the system via a 1394 port. If the DV data is encoded into Internet streaming, a skip command may be issued to the DV encoder when an expected channel error rate exceeds a predetermined value.
In an embodiment of the invention, an encoding system comprises a DV encoder, a microprocessor, a DRAM, and a DRAM controller. The DV encoder includes a buffer, a variable length coding (VLC) device, and a control mechanism. The buffer temporarily stores the data required for DV encoding, and the VLC device acquires the data from the buffer for multi-stage encoding. The control mechanism drives the VLC device to skip the next or remaining pass encoding stage(s) and commands the buffer to provide a subsequent video segment to the VLC device when receiving a skip command. Operation of the DV encoder can be in any of the described modes, such that the skip command can be issued by the microprocessor or the DRAM controller via a physical link when resources of the DRAM are overtaxed. The encoding system further comprises a 1394 port, which connects to an external DV device. The microprocessor may issue a skip command when detecting the external DV device operation in fast forward or fast rewind. If the DV data is transmitted to an error-prone environment, such as the Internet, a skip command is issued to the DV encoder when a channel error rate exceeds a predetermined value. The DV encoder further comprises a transformation device analyzing the data using a discrete cosine transformation (DCT) algorithm, a quantization device weighting and quantizing the output of the transformation device, a scan device scanning the output of the quantization device, and a run-length coding (RLC) device performing RLC encoding for output, finally providing the RLC encoded data to the VLC device.
The corresponding decoding method for a DV decoder according to an embodiment of the invention comprises acquiring the DV data for a multi-stage decoding process, and skipping the next or remaining pass decoding stage(s) when receiving a skip command. A multi-stage decoding process corresponds to the 3-pass encoding process at the DV encoder end. Similar to the encoding method, the skip command can be issued by a microprocessor, or a DRAM controller via a physical link, with DRAM bandwidth assumed to be the critical shared resource. In mode 0, the status of the DRAM controller is monitored by or reported to the microprocessor, and the microprocessor issues a skip command if the system resources of the DRAM are occupied. Mode 1 further reduces loading on the microprocessor, wherein a physical link between the DRAM controller and the DV decoder informs the DV decoder of DRAM bandwidth status by passing a skip command to the DV decoder. The microcontroller issues a skip command when detecting a fast forward or fast rewind operation in an external DV device connected to the DV decoder via the 1394 port. If the DV data is transmitted by Internet streaming, a skip command may be issued to the DV decoder when a channel error rate exceeds a predetermined value.
The corresponding decoding system comprises a DV decoder, a microprocessor, a DRAM, and a DRAM controller. The DV decoder includes a storage means, a variable length decoding (VLD) device, and a control mechanism. The storage means stores data required for DV decoding, and the VLD device acquires the data from the storage means for execution of multi-stage decoding. When receiving a skip command, the control mechanism drives the VLD device to skip the next or remaining pass decoding stage(s), and commands the storage means to provide a subsequent video segment to the VLD device for the pass not skipped. The operation of the DV decoder can be in one of two modes, such that the skip command is issued by the microprocessor or the DRAM controller via a physical link when resources of the DRAM are overtaxed. The skip command can also be issued when an external DV device on a 1394 port is fast forwarding or fast rewinding the video. If the DV data originates in an error-prone environment, such as the Internet with narrow bandwidth, a skip command is issued to the DV decoder when a channel error rate exceeds a predetermined value. The DV decoder further comprises a run-length decoding (RLD) device performing RLD decoding for the output of the VLD device, an inverse scan device, an inverse quantization device, and an inverse transformation device. Each device corresponds to a device in the DV encoder, and performs the inverse operation of DV encoding.
The invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:
In a system on chip (SOC) design, many functional blocks share storage and computation resources, such as dynamic random access memory (DRAM) and central processing unit (CPU). If the shared resource is insufficient to complete a certain operation inside a functional block, the computation result will be incorrect, causing abnormal output that is hardly tolerable in a consumer-oriented design. A compromise scheme is provided to reduce the risk of failures due to insufficient shared resources.
As shown in
A DV decoder based on the same technical features disclosed in the DV encoder 7 is also provided.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
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|U.S. Classification||382/232, 375/E07.145, 375/E07.094, 386/E09.015, 375/E07.184, 375/E07.168, 375/E07.177, 375/E07.211|
|Cooperative Classification||H04N9/8047, H04N19/156, H04N19/184, H04N9/8063, H04N19/423, H04N19/132, H04N19/61, H04N19/18|
|European Classification||H04N7/26A8T, H04N7/26A8C, H04N7/26L2, H04N7/26A4Z, H04N9/804B3, H04N7/26A6R, H04N7/50|
|Aug 31, 2004||AS||Assignment|
Owner name: MEDIATEK INCORPORATION, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, HONG-HUI;LU, CHUNG-YEN;HUANG, CHI-HUI;REEL/FRAME:015763/0086
Effective date: 20040812
|Oct 24, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Oct 22, 2015||FPAY||Fee payment|
Year of fee payment: 8