|Publication number||US7366946 B2|
|Application number||US 11/702,809|
|Publication date||Apr 29, 2008|
|Filing date||Feb 6, 2007|
|Priority date||Feb 4, 2003|
|Also published as||US7174477, US20040153725, US20070168783|
|Publication number||11702809, 702809, US 7366946 B2, US 7366946B2, US-B2-7366946, US7366946 B2, US7366946B2|
|Inventors||Scott Derner, Casey Kurth, Phillip G. Wald|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (36), Referenced by (11), Classifications (10), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. patent application Ser. No. 10/357,779, filed Feb. 4, 2003 now U.S. Pat. No. 7,174,477 and titled, “ROM REDUNDANCY IN ROM EMBEDDED DRAM,” which is commonly assigned and incorporated by reference in its entirety herein.
The present invention relates generally to memory devices, and more specifically to a read only memory (ROM) embedded in a dynamic random access memory (DRAM).
DRAM technology builds redundancy into DRAM arrays. Such redundancy allows for reassigning data storage to another redundant row/column/block of a memory array to compensate for inevitable defects in processing. Since modem DRAM arrays are so vastly large in number of cells, and so vastly small in terms of actual size per cell, even small errors in processing can affect cells. By building redundancy into DRAM arrays, yield is improved since reprogramming of some portion of a DRAM array is far superior to wasting the entire part due to a few small defects. Since the defect rate is actually not very large, a single redundancy array is sufficient to compensate for most errors in processing of a modem DRAM array.
In redundancy in DRAM arrays, spare elements such as rows or columns are used as logical substitutes for a defective element or elements. The substitution of redundant rows or columns for defective rows or columns is controlled by a physical encoding scheme. As memory density and size increase, redundancy becomes more and more important. Row and column redundancy are commonplace in modem DRAMs. Further, some DRAM manufacturers have begun to experiment with entire subarray redundancy.
Row redundancy replaces bad word lines with good word lines. Any number of problems could exist on word lines, including shorted or open word lines, word line to digit line shorts, bad transistors or storage capacitors, and the like.
A ROM embedded DRAM is a DRAM array that has been modified slightly to allow for a portion of the DRAM array cells to be converted into ROM cells. Such a ROM embedded DRAM is described in greater detail in U.S. Pat. No. 6,134,137 issued Oct. 17, 2000 entitled “ROM-Embedded-DRAM”, incorporated herein by reference. U.S. Pat. No. 6,134,137 teaches that slight modifications in fabrication masks allow DRAM cells to be hard programmed to Vcc or Vss by shorting the cell to word lines. The memory reads the ROM cells in a manner that is identical to reading the DRAM cells.
In a ROM embedded DRAM, problems with DRAM cells that have been converted to ROM cells can contribute to ROM defects. For example, if a DRAM cell on a portion of the ROM embedded DRAM is to be programmed by hard shorting to a 0 logic, but it is open and stuck at a 1 logic, there would be an error.
In row redundancy, when a row address is strobed into a DRAM, the address is compared to a known bad address bank. If a bad address is requested, a replacement word line is fired in place of the defective or bad word line. The replacement word line can appear anywhere on the DRAM array. Repair of rows is termed either global or local. If the replacement word line is in the same subarray as the bad word line, the repair is termed a local repair. If the bad word line is in a different subarray than the replacement word line, the repair is termed a global repair. Global repair is more desirable because the amount of repair is limited in each subarray. If one particular subarray has a large number of defects, and all the repairs are local, the subarray could run out of available replacement rows, and the entire chip becomes scrap. Global repair is very effective for cluster type failures, and is especially helpful for larger DRAMs.
There are many different redundancy repair schemes, which are beyond the scope of this application, but which are readily known to those of skill in the art. For example only and not by way of limitation, repair schemes include antifuses, dynamic logic, and the like. Redundant word lines are often capable of pretesting to determine whether they are good or bad before actual selection of the replacement word line. This allows for selection of a good replacement word line and the concordant lack of necessity to change many replacement word lines to second replacement word lines.
Column redundancy schemes are also available on most modem DRAMs. Column redundancy differs from row redundancy in that it is often the case that column addresses can be accessed multiple times per row address strobe cycle. Each column is held open until a subsequent column appears. Typical column fuse blocks for column redundancy are built using static logic gates rather than dynamic logic gates. Dynamic gates require a precharge and evaluation (P&E) and sufficient time to perform the P&E may not be present with unpredictable column addressing. In some modem DRAMs, such P&E will work, and in that case, the schemes for column redundancy are very close to that of row redundancy. However, in some other DRAM architectures, static redundancy is used.
It would be desirable to implement redundancy in the ROM portion of a ROM embedded DRAM.
In the following detailed description of the embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention.
The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
A ROM embedded DRAM is a DRAM array having a portion of the array utilized as a ROM array, and another portion of the array used as a normal DRAM array. Referring to
Dynamic memories are well known, and those skilled in the art will appreciate that the above-described ROM embedded DRAM has been simplified to provide a basic understanding of DRAM technology and is not intended to describe all of the features of a DRAM. The present invention uses the basic architecture and fabrication techniques of a DRAM and provides an embedded ROM array for non-volatile storage of data. This data can be used to store boot-type data for a system, a non-volatile look-up table, or other data that does not require a dedicated ROM memory device. Embedding ROM storage in a DRAM is most economically beneficial if the DRAM is not substantially altered during fabrication or operation. That is, small fabrication changes allow the embedded memory to be fabricated using known techniques. Further, it is desired to maintain operation of the memory in a manner that is externally transparent. As such, an external processor, or system, does not need special protocol to interface with the embedded memory. As described below, the present invention provides an improved ROM embedded DRAM having ROM portion redundancy.
ROM bits are hard programmed in a ROM embedded DRAM by any number of programming techniques, including by way of example only and not by way of limitation, hard programming by eliminating cell dielectric to short cell plates to a program voltage, or by fabricating an electrical plug between the cell plates and shorted to a program voltage, programming using an anti-fuse programming technique, or by providing a high leakage path (not full short) such as through an active area to the substrate.
There is an advantage in building in redundancy in a ROM when it is fabricated as a ROM embedded DRAM. Since there are so many possible small defects that can crop up among the many millions of devices on a typical sized ROM embedded DRAM or DRAM chip, it is beneficial to allow for some repair. Typically, this is done through redundancy. The repair embodiments of the present invention range from repair of everything from a single bit up to an entire array.
Instead of testing to determine errors as in DRAM technology, it is necessary to check to see if the ROM bit of the ROM embedded DRAM contains data to which it has been programmed, that is either a 1 or a 0, statically.
In order to accomplish this, several different embodiments are shown. Repairs on ROM embedded DRAM can be performed in the various embodiments on any number of bits from a single bit repair to an entire subarray repair.
A ROM embedded DRAM 200 having ROM portion redundancy is shown in one embodiment in
Upon checking of the ROM portion after the programming of the ROM portion is completed, any ROM bits which are not properly programmed are identified by row address and column address. The bad or defective row and column addresses are stored in a register, bank of antifuses, or the like, and when a row and address for reading is presented to the ROM portion of the ROM embedded DRAM via the address circuitry, the received addresses are checked against the table, register, or bank of known bad addresses. If a match is found between the received addresses and the bad address lookup, the request for the data at the bad address is rerouted to the lookup table 202 containing the proper ROM bit for the received address. This ROM bit is read out as the requested ROM bit. In one embodiment, the lookup table 202 includes not only the row, address, and polarity information, but also the bad row and address information. In another embodiment, the lookup table and the bad address register are separate.
In operation, the lookup table or redundancy register contains all the normal circuitry of a redundancy array, but also contains an extra bit to store correct ROM bit polarity. During testing, bad addresses are determined, and stored in the lookup table along with the correct ROM bit polarity that is supposed to be stored in the cell at the received row and column address. The ROM bit is simply an extra bit which is programmed along with the row and column address when a particular ROM bit is determined during testing to be defective. Redundancy circuitry in another embodiment comprises a defective ROM bit address register and a defective ROM bit address bank.
The bits of such a redundancy compare circuit are typically programmed using antifuses. When the address circuitry determines that a defective row and column address has been received, the address circuitry looks up the address in the lookup table, and uses the programmed correct polarity bit in the lookup table as the data to be read out from the ROM. It should be understood that the size of the redundancy compare circuit or lookup table can be varied without departing from the scope of the invention. For example, the redundancy compare circuit or lookup table is made larger in another embodiment. The only factor limiting size of the redundancy compare circuit or lookup table is real estate available.
Various redundancy schemes are appropriate for the rerouting of bad addresses once the bad addresses are known. The provision in a lookup table such as lookup table 202 of the appropriate ROM bits allows redundancy in the live array ROM portion of the ROM embedded DRAM without the need for actually having redundant cells. Instead, the table contains the pertinent correct ROM bit information, which is read out when there is an error or defect in the live array ROM portion of the ROM embedded DRAM. In an alternative embodiment, correcting the ROM bit data is accomplished by inverting the read ROM bit polarity for a known defective ROM bit prior to sending the data to an output pin of the memory device.
In another embodiment, only ROM bits which are to be hard shorted to a specific polarity are checked, with the remaining ROM bits assumed by address to be the opposite polarity. In other words, the ROM portion of the ROM embedded DRAM is programmed so that all of the bits to be hard shorted to a certain polarity, say 0, are hard shorted to zero logic, and then checked to see if any errors occurred on those bits. The remaining ROM bits of the ROM embedded DRAM, namely those bits which are to be 1 polarity bits, are assumed by software, hardware, or firmware to be 1 bits. This reduces the size of the lookup table needed for the ROM portion of the ROM embedded DRAM, but may increase the complexity of software, hardware or firmware used in decoding the ROM bits.
In another embodiment, a ROM embedded DRAM array has an array of antifuses that are used for redundancy in the array as described above. Upon testing in a DRAM, for example, if a row or column of the DRAM is found to be bad, that row or column is routed to a redundant set of elements for execution of the memory storage desired. This is done, as described above, by programming antifuses or the like to replace a designated row address with a new destination row address. In one embodiment of the present invention, an array of antifuses is used similarly to the use in a typical DRAM. However, in the case of a ROM embedded DRAM, the necessary information for each bit includes not only a row and a column address, but also a polarity of the ROM bit to be decoded. In other words, each ROM bit is identified by a row address and a column address, and also by a polarity of the ROM bit, that is a 1 or a 0 value. This information is stored in a register or the like so as to be readily available when a bad row and column address is received.
On a ROM embedded DRAM, a test is run to check the encoding of the ROM section. When testing is complete, the necessary rerouting of rows, columns, bits and the like is known, and is then performed. This is accomplished in various embodiments following typical DRAM redundancy reprogramming for defective rows and columns or addresses, with the added process of encoding or pointing to information pertaining to the sections containing the correct ROM data as well as the row and column address of the ROM bit.
In a normal DRAM, the programming of an antifuse leads to the rerouting of a row or column to a redundant row or column of memory bits. In this embodiment, it is not necessary to reroute to a redundant column or row of memory bits. Instead, what is done by blowing the antifuse in an antifuse redundancy scheme is to reroute to a lookup table, register, bank of antifuses, or the like, such as lookup table 202, that is programmed to look up or is encoded with the row and column address of the ROM bits, as well as the polarity of the ROM bits.
In one embodiment, the lookup is made in a bank of antifuses. The bank of antifuses has a register, wherein each of the antifuses corresponds to a particular row and column address, and is registered at each row and column address, that is at each and every defective ROM bit, with the polarity of the specific ROM bit that matches the row and column address that is desired to be accessed.
In this embodiment, the ROM has been described as if it were programmed at a manufacturing facility, that is not field programmed. For example, a mask for making the ROM is coded with the desired ROM hard wiring information, and is encoded in the manufacturing process. Once the ROM is encoded, it is tested. If errors occur, they are repaired using one of the redundancy techniques discussed above. The repair is performed in one embodiment by blowing the antifuse in the redundancy part of the ROM that corresponds to the bit which has an error so that it reads correctly.
In this embodiment, the ROM has been discussed with hard coded ROM programming, that is programming done at the manufacturing location. However, it should be understood that field programmable ROMs (PROMs) are used in another embodiment. In that embodiment, the field programmer field programs a ROM as PROMs are typically programmed. Then, testing is performed. At that point, the customer or field programmer must know the redundancy scheme in order to effect repairs on the ROM embedded DRAM ROM portion.
In another embodiment 300 shown in block diagram in
The redundancy scheme of
In this manner, individual bit errors are repaired in redundant array fashion. It should be seen that not only are individual bit errors repairable using the redundancy configuration of
In another example of operation of such a redundancy configuration, the ROM embedded DRAM 300 has enough memory bits to make at least two images of a desired ROM portion of the ROM embedded DRAM. For example, a customer desires 64 MB of DRAM and 32 MB of ROM on the same chip. In this instance, a 128 MB ROM embedded DRAM can be programmed to have 64 MB of DRAM, and two arrays of 32 MB of ROM. Each of the two arrays of ROM in this embodiment are identical images of one another. The ROM sections are programmed with the desired information that the customer wishes to have programmed in the ROM section. Then, once the programming is performed, the ROM arrays are tested to determine if any errors exist. If an error is found in the primary ROM section, the bad section, be it a single bit, a row, a column, a subarray, a block, or even the entire array, is mapped to the secondary array. Identification of bad bits, segments, and the like is accomplished in various ways, for example only and not by way of limitation, using fuse banks, antifuse banks, or registers. When blown, an antifuse reroutes a specific row and column location, or an entire subarray or the like, of the primary ROM array to the same location on the secondary ROM array.
In yet another embodiment, blocks of any size from an individual bit on up to an entire ROM section of a ROM embedded DRAM are redundantly repairable. If ever increasing amounts of reliability are required, the number of redundant blocks is in other embodiments increased. For example, in a 256 MB DRAM chip, perhaps the customer only wishes to have 64 MB of RAM, and the rest of the chip is available for ROM embedded in the DRAM, then 192 MB is available for ROM. In many cases, the amount of ROM desired is actually quite low, for example 32 MB. In this instance, six 32 MB arrays are formed to allow for greatly increased multiple redundancy for the ROM portion of the ROM embedded DRAM. It should be seen that the actual configuration of the amount of redundancy will vary depending upon the desired yield of DRAM versus ROM for the ROM embedded DRAM, and for the level of redundancy desired in the configuration.
In another embodiment, a combination of other embodiments comprises first and second identical arrays as in
However, in a situation in which there is enough room for redundancy but not enough for an entire second array, such a combination provides an extra measure of reparability to the chip. For example, if a ROM embedded DRAM chip has enough room for the customer's desired DRAM/ROM configuration, with enough leftover room for a redundant ROM array image, and for a redundancy scheme of antifuses for one of the ROM subarrays but not both, such a combination provides extra reparability without sacrificing usability.
In another embodiment, testing of the ROM portion of the ROM embedded DRAM identifies the predominant type of error in the ROM portion of the ROM embedded DRAM. The redundant array is broken into segments or chunks according to the predominant type of error. For example, if the predominant error type is single bit errors, the redundant array is subdivided into individual bits. If the predominant error type is blocks, the redundant array is subdivided into blocks of a determined size, and reprogramming is of blocks instead of individual bits.
In yet another embodiment, the specific fabrication process may lend itself to have predominantly a specific type of error. A redundant ROM array is divided in this embodiment into subarrays according to the likely type of errors. Software built into ROM programming in another embodiment allows the redundant array to be subdivided after testing according to a predominant type of error found during testing.
A ROM embedded DRAM having a section of ROM programmed bits and a section of DRAM bits is advantageously used in certain situations in which non-volatile memory is desired or required, but where speed is also a factor. In such a situation, a ROM embedded DRAM has the contents of the ROM section read into RAM on startup or trigger. The ROM portion is then no longer needed, as all operations are performed using the ROM copied into RAM. That is, a ROM to RAM copy, allowing the ROM to be modified while maintaining the integrity of the ROM encoding for later use. Such an embodiment is especially useful in situations where the ROM read is a long process, or the ROM consumes more power than is desired to be consumed if read multiple times. Such an embodiment is useful in configurations where real estate is a primary concern. In such situations, a single chip having both ROM and DRAM sections is employed, thereby using only one chip instead of the usual two chips. For example, hearing aids, cellular telephones, and other size constrained apparatuses, are amenable to the embodiments of the present invention.
In yet another embodiment, ROM embedded in DRAM is read into RAM on startup to allow for faster operation of the ROM portion of the DRAM. For example, it may be desirable in one embodiment to program certain startup options which will always remain the same into ROM. However, ROM typically runs slower than RAM. In this instance, during startup, the contents of the ROM portion of the ROM embedded DRAM are read into RAM so that they can be executed with greater speed. This also allows for the possibility of changing the ROM parameters temporarily, knowing that upon another restart, the original ROM encoding will again be available.
A method 400 of redundancy testing in a ROM embedded DRAM is shown in flow chart diagram in
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4575819||Aug 1, 1983||Mar 11, 1986||Motorola, Inc.||Memory with RAM cells and ROM cells|
|US4744060 *||Oct 17, 1985||May 10, 1988||Fujitsu Limited||Bipolar-transistor type random access memory having redundancy configuration|
|US4855803||Jul 26, 1988||Aug 8, 1989||Ricoh Company, Ltd.||Selectively definable semiconductor device|
|US5053648||May 10, 1990||Oct 1, 1991||U.S. Philips Corporation||Master slice cmos array having complementary columns|
|US5148391||Feb 14, 1992||Sep 15, 1992||Micron Technology, Inc.||Nonvolatile, zero-power memory cell constructed with capacitor-like antifuses operable at less than power supply voltage|
|US5270241||Nov 6, 1992||Dec 14, 1993||Micron Technology, Inc.||Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing|
|US5351213||Feb 28, 1992||Sep 27, 1994||Samsung Electronics Co., Ltd.||Integrated semiconductor memory device utilizing a test circuit|
|US5388076||Jul 2, 1993||Feb 7, 1995||Sharp Kabushiki Kaisha||Semiconductor memory device|
|US5418739||Jan 25, 1994||May 23, 1995||Oki Electric Industry Co., Ltd.||Semiconductor memory device|
|US5657280 *||Dec 29, 1995||Aug 12, 1997||Samsung Electronics Co., Ltd.||Defective cell repairing circuit and method of semiconductor memory device|
|US5732013||Jan 8, 1997||Mar 24, 1998||Siemens Aktiengesellschaft||Matrix memory (virtual ground)|
|US5757690||Apr 23, 1997||May 26, 1998||Exponential Technology, Inc.||Embedded ROM with RAM valid bits for fetching ROM-code updates from external memory|
|US5831892||Aug 1, 1997||Nov 3, 1998||Siemens Aktiengesellschaft||Matrix memory in virtual ground architecture|
|US5883903 *||Nov 13, 1996||Mar 16, 1999||Fujitsu Limited||Semiconductor memory of XN type having parity corresponding to n×m bits|
|US5900008||Dec 18, 1996||May 4, 1999||Hitachi, Ltd.||Semiconductor integrated circuit device|
|US5913928 *||May 9, 1997||Jun 22, 1999||Micron Technology, Inc.||Data compression test mode independent of redundancy|
|US5917744||Dec 18, 1997||Jun 29, 1999||Siemens Aktiengesellschaft||Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines|
|US5923672 *||Jun 4, 1997||Jul 13, 1999||Micron Technology, Inc.||Multipath antifuse circuit|
|US5961653||Feb 19, 1997||Oct 5, 1999||International Business Machines Corporation||Processor based BIST for an embedded memory|
|US5966315||Sep 30, 1997||Oct 12, 1999||Siemens Aktiengesellschaft||Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines|
|US5982682||Mar 12, 1998||Nov 9, 1999||Micron Technology, Inc.||Self-test circuit for memory integrated circuits|
|US5986952 *||Dec 3, 1998||Nov 16, 1999||Siemens Aktiengesellschaft||Redundancy concept for memory circuits having ROM memory cells|
|US5995409||Mar 20, 1998||Nov 30, 1999||Silicon Aquarius, Inc.||Electrically-programmable read-only memory fabricated using a dynamic random access memory fabrication process and methods for programming same|
|US6052798 *||Jul 1, 1998||Apr 18, 2000||Micron Electronics, Inc.||System and method for remapping defective memory locations|
|US6065141 *||Jul 26, 1993||May 16, 2000||Fujitsu Limited||Self-diagnosable semiconductor memory device having a redundant circuit and semiconductor apparatus having the same in which the memory device cannot be accessed from outside the semiconductor apparatus|
|US6097649||Jun 1, 1998||Aug 1, 2000||Silicon Magic Corporation||Method and structure for refresh operation with a low voltage of logic high in a memory device|
|US6128225||Jun 18, 1997||Oct 3, 2000||Stmicroelectronics S.R.L.||Method and circuit for reading low-supply-voltage nonvolatile memory cells|
|US6134137||Jul 31, 1998||Oct 17, 2000||Micron Technology Inc.||Rom-embedded-DRAM|
|US6154864||May 19, 1998||Nov 28, 2000||Micron Technology, Inc.||Read only memory embedded in a dynamic random access memory|
|US6243285||Apr 28, 2000||Jun 5, 2001||Micron Technology, Inc.||ROM-embedded-DRAM|
|US6657878 *||Feb 27, 2002||Dec 2, 2003||Integrated Device Technology, Inc.||Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same|
|US6735727 *||Jun 2, 2000||May 11, 2004||Samsung Electronics Co., Ltd.||Flash memory device with a novel redundancy selection circuit and method of using the same|
|US7028234 *||Sep 27, 2002||Apr 11, 2006||Infineon Technologies Ag||Method of self-repairing dynamic random access memory|
|US7043672 *||Apr 30, 2003||May 9, 2006||Micron Technology, Inc.||Layout for a semiconductor memory device having redundant elements|
|US7159141 *||Jul 1, 2002||Jan 2, 2007||Micron Technology, Inc.||Repairable block redundancy scheme|
|US20020141254 *||Mar 28, 2001||Oct 3, 2002||Ladner Brian J.||Memory device having programmable column segmentation to increase flexibility in bit repair|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7958439 *||May 26, 2010||Jun 7, 2011||Micron Technology, Inc.||Defective memory block remapping method and system, and memory device and processor-based system using same|
|US8560891 *||Oct 18, 2012||Oct 15, 2013||International Business Machines Corporation||EDRAM macro disablement in cache memory|
|US8601331||May 20, 2011||Dec 3, 2013||Micron Technology, Inc.||Defective memory block remapping method and system, and memory device and processor-based system using same|
|US8839054||Apr 12, 2012||Sep 16, 2014||International Business Machines Corporation||Read only memory (ROM) with redundancy|
|US8848437 *||Aug 28, 2013||Sep 30, 2014||Intel Mobile Communications GmbH||Magnetic random access memory|
|US9269457||Feb 26, 2013||Feb 23, 2016||Samsung Electronics Co., Ltd.||Semiconductor device capable of rescuing defective characteristics occurring after packaging|
|US9460811||Aug 7, 2014||Oct 4, 2016||Globalfoundries Inc.||Read only memory (ROM) with redundancy|
|US9466393||Jan 15, 2016||Oct 11, 2016||Jeong-Kyoum Kim||Semiconductor device capable of rescuing defective characteristics occurring after packaging|
|US20100235679 *||May 26, 2010||Sep 16, 2010||Micron Technology, Inc.||Defective memory block remapping method and system, and memory device and processor-based system using same|
|US20110219260 *||May 20, 2011||Sep 8, 2011||Micron Technology, Inc.|
|US20130042144 *||Oct 18, 2012||Feb 14, 2013||International Business Machines Corporation||Edram macro disablement in cache memory|
|International Classification||H02H3/05, G11C29/00, G06F11/00|
|Cooperative Classification||G11C29/822, G11C29/74, G11C17/14, G11C11/401|
|European Classification||G11C29/822, G11C29/74|
|Sep 14, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Oct 14, 2015||FPAY||Fee payment|
Year of fee payment: 8
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426
|Jun 8, 2017||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001
Effective date: 20160426