|Publication number||US7372763 B2|
|Application number||US 11/321,366|
|Publication date||May 13, 2008|
|Filing date||Dec 28, 2005|
|Priority date||Dec 28, 2005|
|Also published as||CN101009132A, DE102006061877A1, DE102006061877B4, US20070147158|
|Publication number||11321366, 321366, US 7372763 B2, US 7372763B2, US-B2-7372763, US7372763 B2, US7372763B2|
|Inventors||Steven K. Hsu, Atul Maheshwari, Ram K. Krishnamurthy|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (2), Referenced by (2), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Active and leakage power dissipation are important issues in modern large scale integrated circuit chips such as microprocessors. Single ended memories like register file circuits, read only memory (ROM) circuits and dynamic random access memory (DRAM) circuits are a significant component of the total active and leakage power dissipation in such chips. With technology scaling, such power consumption from memory circuits is increasing and proving to be a serious limitation, for example, in mobile application chips. Accordingly, improved circuits for reducing power in memory is desired.
In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written to a portion of the memory circuit. The majority voter circuit determines if the data bits are to be inverted prior to being written into the memory circuit portion.
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Disclosed herein are embodiments for reducing both active and leakage power. For example, up to 50% reduction in worst case power dissipation may be achieved. Spatially encoded data storage can result in at least half of the bit cells in a memory array being in a reduced power state.
In operation, When a word (or column) is to be read, a word line (WL[i]) for a particular column is asserted (High), which causes the cell values in that column to be coupled through to their associated bit line, where they are read or driven through an output driver (not shown). The depicted register file 100 is implemented using dynamic logic and thus has a keeper 102 coupled to each bit line to mitigate against the effects of leakage.
The amount of both active and leakage power consumed depends on the distribution of stored values in the cells 104. With the depicted configuration, if more ‘1s are stored, there is higher leakage (due to the M3 transistors being turned on thereby reducing the impedance in their stack). The active power consumption will also be higher due to more bit line nodes over time being discharged. Accordingly, embodiments disclosed herein address these problems and reduce active and/or leakage power consumption.
As used herein, “spatial encoding” refers to encoding data that is stored in a memory array to reduce (or reasonably minimize) the number of higher power consuming states in the memory. With the depicted array 200, for example, a stored ‘1 results in higher power consumption than a stored ‘0. This is so because in this depicted embodiment, NMOS transistors are used in the cell access stacks. Thus, depending on the configuration (e.g., with PMOS stack transistors) of the memory circuit, a ‘0 could be the higher power consuming state. With the depicted embodiment, data values in a given word (column) are inverted if more than half are ‘1s and then inverted again when read if they were inverted when stored. However, other schemes could be used to reduce the number of higher power consuming states in the array.
(The term “NMOS transistor” refers to an N-type metal oxide semiconductor field effect transistor. Likewise, “PMOS transistor” refers to a P-type metal oxide semiconductor field effect transistor. It should be appreciated that whenever the terms: “transistor”, “MOS transistor”, “NMOS transistor”, or “PMOS transistor” are used, unless otherwise expressly indicated or dictated by the nature of their use, they are being used in an exemplary manner. They encompass the different varieties of MOS devices including devices with different VTs and oxide thicknesses to mention just a few. Moreover, unless specifically referred to as MOS or the like, the term transistor can include other suitable transistor types, e.g., junction-field-effect transistors, bipolar-junction transistors, and various types of three dimensional transistors, known today or not yet developed.)
With the register file of
The technique used to determine if more than half the bits in a word to be stored (written) are “1” may be performed using any suitable approach. For example, it may be implemented using appropriate circuitry (analog and/or digital logic) ahead of the register file cells 104. In some embodiments, delay threshold logic such as the circuit of
The first delay element has N equally weighted inputs to receive the N data bits of a word to be written into a register file. It delays the input clock (CLK) based on how many of these input bits are at ‘1. For example, the delay may be reduced by a fixed amount for each data input that is at ‘1. On the other hand, the second delay element 302B is configured to delay the CLK signal by a fixed amount equivalent to the first delay circuit delay if half of its bits are ‘1 and half are ‘0. For example, it may be implemented with the same type of delay element with half of its N data inputs at ‘1 and the other half at ‘0. For additional information regarding such a majority voter circuit, reference may be made to commonly owned U.S. patent application Ser. No. 11/094,811 entitled “DATA CONVERTER AND A DELAY THRESHOLD COMPARATOR” filed on Mar. 31, 2005.
The latch 304 compares the clock delay from the first delay element 302A to that from the second delay element 302B. Its output is determined by which delay element's clock pulse reaches the latch first. For example, it may be a ‘1 if the clock signal from the first delay element 302A arrives first, indicating that more of the data bits are ‘1s. On the other hand, it may be a ‘0 if the second delay element's clock arrives first, indicating that less than half of the data bits are ‘1s. The output could then be used as a control signal to cause data to be written into a register file word to be inverted or not to be inverted. For example, it could be used to control multiplexers, with inverting and non-inverting paths, in front of a register file write port to cause an inverted or non-inverted form of the data to be written into the register file.
It should be appreciated that disclosed spatially encoded memory storage techniques can be applied to any suitable (e.g., single ended) memory. For example, it could be used in dynamic random access memory (DRAM) and read only memory (ROM). Accordingly,
With reference to
It should be noted that the depicted system could be implemented in different forms. That is, it could be implemented in a single chip module, a circuit board, or a chassis having multiple circuit boards. Similarly, it could constitute one or more complete computers or alternatively, it could constitute a component useful within a computing system.
The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chip set components, programmable logic arrays (PLA), memory chips, network chips, and the like.
Moreover, it should be appreciated that example sizes/models/values/ranges may have been given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the FIGS. for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
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|U.S. Classification||365/227, 365/189.08, 365/194|
|International Classification||G11C7/10, G11C7/00|
|Cooperative Classification||G11C2207/2227, G11C7/1006, G11C7/22, G11C7/222|
|European Classification||G11C7/22A, G11C7/22, G11C7/10L|
|Mar 6, 2008||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, STEVEN K.;MAHESHWARI, ATUL;KRISHNAMURTHY, RAM K.;REEL/FRAME:020611/0953;SIGNING DATES FROM 20060223 TO 20060302
|Sep 21, 2011||FPAY||Fee payment|
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