|Publication number||US7383464 B2|
|Application number||US 10/730,815|
|Publication date||Jun 3, 2008|
|Filing date||Dec 8, 2003|
|Priority date||Dec 8, 2003|
|Also published as||US7827449, US20050125695, US20080141078|
|Publication number||10730815, 730815, US 7383464 B2, US 7383464B2, US-B2-7383464, US7383464 B2, US7383464B2|
|Inventors||Bruce M. Gilbert, Donald R. DeSota, Robert Joersz|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (19), Referenced by (2), Classifications (16), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
This invention relates generally to processing transactions within a pipeline, and more particularly to correcting errors within such transactions.
2. Description of the Prior Art
Pipelining is a technique that is used to speed up the processing of transactions. Transactions include read commands, which read data from memory, and write commands, which write data to memory. Typically, only one transaction can be processed at a time. Inserting register points within transaction-processing logic is referred to as pipelining. The logic between two sets of register points is referred to as a pipeline stage. Pipelining allows a different transaction to be within each stage of the pipeline, thus increasing processing throughput. Pipelining also allows the frequency of the processor to be increased, because the levels of processing logic between register points are reduced. However, the overall time to process a transaction may be increased only slightly, due to the delay of the registers that are inserted in the logic. Pipelining also can increase complexity if there are dependencies between transactions.
If errors are detected within the pipeline, they usually are corrected in-line, within the pipeline stage where they occur, before the transactions can be properly processed and the resulting actions performed. An implementation for error correction may include additional hardware circuitry to correct the error when and where it is detected. However, such an implementation adds latency to the processing of both transactions with errors and transactions without errors. For this and other reasons, therefore, there is a need for the present invention.
The invention relates to non-inline transaction error correction. A method for the invention determines whether a transaction includes a correctable error while the transaction is being processed in a pipeline. Where the transaction includes an error, it is output from the pipeline into an error queue. A correction command is processed within the pipeline to correct the error within the transaction, and then the transaction is reprocessed within the pipeline.
A system of the invention includes a number of nodes interconnected to one another. Each node includes processors, local random-access memory (RAM) for the processors, and at least one controller. The controllers process transactions relating to the local RAM of the node, including correcting correctable errors within the transactions in a non-inline manner in a separate correction mode.
A controller for a node of a system includes a pipeline, a mode controller, and an error queue. Transactions are processed in the pipeline. The mode controller controls the mode in which the pipeline is operable. Examples are modes in which the pipeline is operable include normal mode, correction mode, and restart mode. Those of the transactions including correctable errors are routed to the error queue for correction of the errors, and reprocessing of the transactions.
Other features and advantages of the invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
The controller 100 normally operates as follows. The mode controller 108 switches, or operates, the pipeline 102 in a normal mode of operation, by selecting the input 104 appropriately, as indicated by the arrow 112. In the normal mode of operation, transactions are processed within the pipeline 102, where none of the transactions have been detected as including errors. Transactions are input into the input 104 of the pipeline 102, as indicated by the arrow 114. The transactions are transferred from the input 104 into the pipeline 102, as indicated by the arrow 116. The pipeline 102 may be a single- or multiple-stage pipeline, and processes the transactions such that they are converted into actions that when performed effect the transactions. Thus, the pipeline 102 outputs the processed transactions into the output 106, as indicated by the arrow 118, from which they are output, as indicated by the arrow 120, as actions that can then be performed.
When transactions do not contain correctable errors, the pipeline 102 processes them normally, in a normal mode of operation, without adding latency that may otherwise result from in-line error correction processing that would have to be performed even on error-free transactions. When transactions contain errors, however, they are drained and corrected in a separate correction mode, and reprocessed in a separate restart mode, and a non-inline manner. Such transactions are drained into the error queue 110, and the mode controller 108 first switches the pipeline 102 to the correction mode to correct the errors, and then switches the pipeline 102 to the restart mode to reprocess the error-corrected transactions.
However, a transaction may include one or more correctable errors. In such instance, the errors are detected in the pipeline 102, and the pipeline 102 notifies the mode controller 108, as indicated by the arrow 122. The mode controller 108 controls the output 106, as indicated by the arrow 124, so that the transaction is output from the output 106 into the error queue 110, as indicated by the arrow 126. Any other transactions that are present in the pipeline 102 are likewise drained into the error queue 110, even those transactions not having any errors. When such errors are detected, and the transactions in the pipeline 102 are drained into the error queue 110, the pipeline 102 is said to be operating in a correction mode, as controlled by the mode controller 108.
The mode controller 108 thereafter controls the input 104, as indicated by the arrow 112, while the pipeline 102 operates in the correction mode. The mode controller 108 issues a correction command to correct the error, as indicated by the arrow 130. The pipeline 102 thus corrects the error per the correction command. When the pipeline 102 has corrected the error, confirmation of the error correction is sent to the mode controller 108, as indicated by the arrow 132. If the transaction contained more than one error, this process is performed repeatedly, until there are no more errors. That is, the pipeline 102 preferably can correct one error at a time. In other embodiments, all errors could be corrected with a single correction command.
Once the transaction has had its errors corrected, the mode controller 108 controls the error queue 110, as indicated by the arrow 128, to reinsert the transactions therein into the input 104 of the pipeline 102, as indicated by the arrow 134. The mode controller 108 controls the input 104, as indicated by the arrow 112, so that the pipeline 102 operates in a restart mode. In the restart mode, the transactions output by the error queue 110 are reprocessed in the pipeline 102, where the transactions have already had their errors corrected. Once all the transactions have been processed within the pipeline 102, and have been output from the output 106 as performable actions, as indicated by the arrow 120, the mode controller 108 controls the input 104, as indicated by the arrow 112, so that the pipeline 102 again operates in the normal mode. If a transaction cycles through the error queue multiple times an uncorrectable error may be signaled. If an uncorrectable error is signaled, it can be flushed from the pipeline 102, and not performed due to its having an uncorrectable error.
The node 300 includes a portion of system memory, referred to as the memory bank 308. The memory bank 308 represents an amount of random-access memory (RAM) local to the node. The node 300 may have more than a single bank of memory, however. The memory controller 314 manages requests to and responses from the memory bank 308. The coherency controller 310 maintains coherency for the memory bank 308. The coherency controller 310 may be an application-specific integrated circuit (ASIC) in one embodiment, as well as another combination of software and hardware. The coherency controller 310 also may have a remote cache memory 312 for managing requests and responses that relate to remote memory, which is the local memory of nodes other than the node 300 is a part. Stated another way, the memory bank 308 is local to the node 300, and is remote to nodes other than the node 300. The coherency controller 310 is preferably directly connected to the interconnection network that connects all the nodes, such as the interconnection network 204 of
The coherency controller 310 interfaces with tag memory 350 via the tag busses 354. The tag memory 350 includes the directory maintaining coherency information regarding the lines of memory of the remote cache memory 312, and information relating to remote references to the memory lines of the memory bank 308. The remote caching information regarding the memory lines of the memory bank 308 may include whether any other nodes are also caching the memory lines of memory bank 308, and whether any of the other nodes have modified the memory lines of the memory bank 308. The tag memory 350, as well as the remote cache memory 312, may be external to the controller 310 or implemented in embedded dynamic random-access memory (DRAM) or embedded static random-access memory (SRAM).
In a normal mode of operation, the pipeline 102 operates as follows. Transactions are input to the input 104, as indicated by the arrow 114, from which they are transferred to the first pipeline stage 402, as indicated by the arrow 418. The pipeline stage 402 inputs transactions to a first logic stage 404, as indicated by the arrow 416, and which are output therefrom, as indicated by the arrow 426. The first logic stage 404 performs a first stage of processing on the transactions. This processing may include the conversion of the transactions into performable actions that when performed effect the transactions.
The second pipeline stage 406 similarly inputs transactions to second logic stage 408, as indicated by the arrow 428, and which are output therefrom, as indicated by the arrow 436. The second logic stage 408 performs a second stage of processing on the transactions. The transactions then exit the pipeline from the pipeline output 410, to the output 106, as indicated by the arrow 118. Where the transactions do not include any correctable errors, they exit the output 106, as indicated by the arrow 120. The transactions move through the pipeline 102 preferably as synchronized by clock cycles. In each clock cycle, a new transaction enters the first pipeline stage 402, the transaction in the first pipeline stage 402 enters the second pipeline stage 406, and the transaction in the second pipeline stage 406 exits the pipeline.
As has been noted, a transaction may include one or more correctable errors. If in the normal mode of operation the logic stage 404 detects the error in the first pipeline stage 402, the first error logger stage 412 is notified, as indicated by the arrow 422. If in the normal mode of operation the logic stage 408 detects the error in the second pipeline stage 406, the second error logger stage 414 is notified, as indicated by the arrow 432. The error logger stages 412 and 414 are preferably part of the pipeline 102, but are not inline with the pipeline stages 402 and 406. Thus, where the transaction does not include any errors, the logger stages 412 and 414 are not involved in the processing of the transaction, avoiding an increase in latency in the processing of the transaction.
The logger stages 412 and 414, when notified by the logic stages 404 and 408 that a correctable error has been found, indicate the presence of the error to the mode controller 108, as indicated by the arrows 122A and 122B, respectively. The mode controller 108 in turn causes the pipeline 102 to switch to a correction mode of operation. The transactions already in the pipeline 102, including the transaction that includes the correctable error or errors, are drained from the pipeline 102 into the error queue 110, as indicated by the arrow 126. While draining the pipeline 102, the mode controller 108 causes the input 104 not to input any new transactions into the pipeline 102, by appropriately selecting the input 104 as indicated by the arrow 112. The mode controller 108 then inserts a correction command into the pipeline 102, as indicated by the arrow 130.
The correction command is processed through the pipeline 102 as if it were a transaction, and corrects the first, or only, correctable error that was detected. If the logic stage 404 had detected the error, the error logger stage 412 in the correction mode can provide information to properly correct the error, as indicated by the arrow 424, where the first pipeline stage 402 provides the correction command to the error logger stage 412, as indicated by the arrow 420. Conversely, if the logic stage 408 had detected the error, the error logger stage 414 in the correction mode can provide information to properly correct the error, as indicated by the arrow 434, where the second pipeline stage 406 provides the correction command to the error logger stage 414, as indicated by the arrow 430.
At the end of the processing of the correction command, the pipeline 102 outputs confirmation of the correction of the error, as indicated by the arrow 132. If there were more than one correctable error, the process that has been described is repeated for each additional error. It is noted that once a first correction command has exited the first pipeline stage 402, a second correction command may enter the first pipeline stage 402, so that, in a two-stage pipeline, up to two correction commands can be in the pipeline 102 at any given time, as can be appreciated by those of ordinary skill within the art.
Once the errors have been corrected, the mode controller 108 causes the pipeline 102 to switch to a restart mode of operation. The restart mode of operation is similar to the normal mode of operation, except that rather than causing the input 104 to accept new transactions in the pipeline 102, as indicated by the arrow 114, the mode controller 108 controls the input 104 to accept the transactions from the error queue 110, as indicated by the arrow 134. The error queue 110 may include a first in, first out (FIFO) queue. Thus, in the restart mode of operation, the transactions that had been drained to the error queue 110 reenter the pipeline 102 for normal processing. The transactions are now processed correctly, since any errors have been corrected. Once the error queue 110 is empty, such that all of its transactions have entered the pipeline 102, the mode controller 108 sets the mode of the pipeline 102 to normal mode and causes it to again process new transactions, by selecting the input 104, as indicated by the arrow 112, so that new transactions enter the input 104, as indicated by the arrow 114.
The pipeline is initially operated in a normal mode of operation (502). A transaction is input into the pipeline (504), and processed within the pipeline (506). Preferably within the pipeline, it is determined whether correctable errors are present within the transaction (507). If no errors are detected (508), then the transaction is output from the pipeline normally (510), and the method 500 is finished. However, if an error is detected (508), then the pipeline is operated in a correction mode (512). The transaction is output, or drained, from the pipeline to an error queue and input into the pipeline is disabled (514), instead of being normally output from the pipeline as before.
A correction command is inserted into the pipeline (516) to correct the error that has been detected. The correction command is processed within the pipeline (518) to actually effect correction of the error. The pipeline is then operated in a restart mode of operation (520), and the transaction is input back into the pipeline from the error queue (522). The transaction is reprocessed within the pipeline (524), where the transaction has had its error corrected. The transaction is output from the pipeline (525), and the pipeline is operated in the normal mode of operation as before (526).
Embodiments of the invention allow for advantages over the prior art. The error correction process that has been described does not add latency to the normal processing of transactions within a pipeline. Rather than correcting errors upon finding them, which can also add latency to the processing of transactions without errors, the pipeline instead notifies a mode controller, which drains the pipeline of the transactions, and causes the pipeline to switch to a correction mode to correct the errors, and then to switch to a restart mode to reprocess the transactions. The correction and restart modes, however, are only entered when errors have actually been detected, and therefore do not add latency to the normal processing of transactions without errors.
It will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. For instance, whereas the invention has been described in conjunction with transaction processing that occurs within a pipeline, some embodiments of the invention can apply to transaction processing that occurs without a pipeline. Where a pipeline is used, it may be a single-stage or a multiple-stage pipeline. Furthermore, embodiments of the invention may be implemented in conjunction with pipelines in any logic flow. Accordingly, the scope of protection of this invention is limited only by the following claims and their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4566103 *||Sep 20, 1983||Jan 21, 1986||Fujitsu Limited||Method for recovering from error in a microprogram-controlled unit|
|US4604750 *||Nov 7, 1983||Aug 5, 1986||Digital Equipment Corporation||Pipeline error correction|
|US4701915 *||Aug 7, 1985||Oct 20, 1987||Fujitsu Limited||Error recovery system in a data processor having a control storage|
|US4875160 *||Jul 20, 1988||Oct 17, 1989||Digital Equipment Corporation||Method for implementing synchronous pipeline exception recovery|
|US5283891 *||Aug 7, 1992||Feb 1, 1994||Kabushiki Kaisha Toshiba||Error information saving apparatus of computer|
|US5438577 *||Apr 15, 1992||Aug 1, 1995||Hitachi, Ltd.||Error correcting system|
|US5564014 *||Aug 25, 1994||Oct 8, 1996||Fujitsu Limited||Apparatus/method for error detecting and retrying individual operands of an instruction|
|US6247118 *||Jun 5, 1998||Jun 12, 2001||Mcdonnell Douglas Corporation||Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry|
|US6457119 *||Jul 23, 1999||Sep 24, 2002||Intel Corporation||Processor instruction pipeline with error detection scheme|
|US6543028 *||Mar 31, 2000||Apr 1, 2003||Intel Corporation||Silent data corruption prevention due to instruction corruption by soft errors|
|US6631448 *||Mar 12, 1998||Oct 7, 2003||Fujitsu Limited||Cache coherence unit for interconnecting multiprocessor nodes having pipelined snoopy protocol|
|US6678860 *||Aug 7, 2000||Jan 13, 2004||Samsung Electronics Co., Ltd.||Integrated circuit memory devices having error checking and correction circuits therein and methods of operating same|
|US6986095 *||May 4, 2001||Jan 10, 2006||Matsushita Electric Industrial Co., Ltd.||Error correction device|
|US6996665 *||Dec 30, 2002||Feb 7, 2006||International Business Machines Corporation||Hazard queue for transaction pipeline|
|US7043679 *||Jun 27, 2002||May 9, 2006||Advanced Micro Devices, Inc.||Piggybacking of ECC corrections behind loads|
|US7093190 *||Jul 12, 2002||Aug 15, 2006||Unisys Corporation||System and method for handling parity errors in a data processing system|
|US7124331 *||May 14, 2002||Oct 17, 2006||Sun Microsystems, Inc.||Method and apparatus for providing fault-tolerance for temporary results within a CPU|
|US7272775 *||Jun 3, 2003||Sep 18, 2007||Stmicroelectronics Sa||Memory circuit comprising an error correcting code|
|US20020087842 *||Dec 29, 2000||Jul 4, 2002||Smith Ronald D.||Method and apparatus for performing architectural comparisons|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7664994 *||Feb 16, 2010||Hewlett-Packard Development Company, L.P.||High-availability cluster node removal and communication|
|US20060053336 *||Sep 8, 2004||Mar 9, 2006||Pomaranski Ken G||High-availability cluster node removal and communication|
|U.S. Classification||714/10, 714/752, 714/757, 714/E11.131|
|International Classification||G06F11/10, H04L9/32, H04L9/00, G06F11/00|
|Cooperative Classification||G06F11/0793, G06F11/0724, G06F11/141, G06F11/1407, G06F11/0712|
|European Classification||G06F11/07P1B, G06F11/07P1E1, G06F11/14A14|
|Dec 23, 2003||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GILBERT, BRUCE M.;DESOTA, DONALD R.;JOERSZ, ROBERT;REEL/FRAME:014893/0891;SIGNING DATES FROM 20031119 TO 20031123
|Jan 16, 2012||REMI||Maintenance fee reminder mailed|
|Apr 4, 2012||AS||Assignment|
Owner name: FACEBOOK, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:027991/0454
Effective date: 20120327
|May 25, 2012||FPAY||Fee payment|
Year of fee payment: 4
|May 25, 2012||SULP||Surcharge for late payment|
|Nov 19, 2015||FPAY||Fee payment|
Year of fee payment: 8