|Publication number||US7383629 B2|
|Application number||US 10/991,532|
|Publication date||Jun 10, 2008|
|Filing date||Nov 19, 2004|
|Priority date||Nov 19, 2004|
|Also published as||CN1805125A, US7838776, US8242376, US20060110898, US20080259581, US20100328868|
|Publication number||10991532, 991532, US 7383629 B2, US 7383629B2, US-B2-7383629, US7383629 B2, US7383629B2|
|Inventors||John M. Lauffer, Voya R. Markovich, Michael Wozniak|
|Original Assignee||Endicott Interconnect Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Non-Patent Citations (2), Referenced by (3), Classifications (36), Legal Events (12)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to circuitized substrates utilizing conductive sheets as part thereof, methods for making such substrates, and to electrical assemblies and information handling systems utilizing such substrates. One primary example of such a circuitized substrate is a printed circuit (or wiring) board (or card) and another is a chip carrier substrate, both of which are produced by the assignee of the present invention.
In Ser. No. 10/354,000, filed Jan. 30, 2003 and entitled “High Speed Circuit Board And Method For Fabrication” (inventors B. Chan et al), there is defined a multilayered circuitized substrate including two multilayered portions, one of these able to electrically connect electronic components mounted on the substrate to assure high frequency connections there-between. The substrate may further include a “conventional” substrate portion of known materials so as to reduce costs while assuring a structure having an overall thickness deemed satisfactory for use in the respective product field. Ser. No. 10/354,000 is now U.S. Pat. No. 6,828,514, having issued Dec. 7, 2004.
As evidenced below from the descriptions of the several cited patents, there are many different approaches to manufacturing printed circuit boards and cards (hereinafter also simply referred to as PCBs), chip carriers and the like substrates. This is true with respect to substrates used in high speed and other final structures. With operational requirements increasing for complex electronic components such as semiconductor chips which mount on circuitized substrates of the types cited above, so too must the host substrate be capable of handling these increased requirements. One particular increased requirement has been the need for higher frequency (high speed) connections between two or more such mounted components, which connections, as stated, occur through the underlying host substrate. By the term “high speed” as used herein is understood to mean signals within a frequency range of from about 3.0 to about 10.0 gigabits per second (GPS) and even higher.
Such high speed connections are subjected to various detrimental effects, e.g., signal deterioration (also referred to as signal attenuation), caused by the inherent characteristics of such known substrate circuitry wiring. In the particular case of signal deterioration, this effect is expressed in terms of either the “rise time” or the “fall time” of the signal's response to a step change. The deterioration of the signal can be quantified with the formula (Z0 *C)/2, where Z0 is the transmission line characteristic impedance, and C is the amount of the connecting “via” capacitance (the “via” being a known plated hole within the substrate to couple different conductive layers). In a signal line (also referred to in the industry as a wire or trace) having a typical 50 ohm transmission line impedance, a plated thru-hole “via” having a capacitance of 4 pico-farads (pf) would represent a 100 pico-second (ps) rise-time (or fall time) degradation. This compares to a 12.5 ps degradation with a 0.5 pf buried “via” of the various embodiments taught in the patent application cited above. This difference is significant in systems which operate at 800 MHz or faster (becoming the “norm” in today's technical world), where there are associated signal transition rates of 200 ps or faster.
One factor that can contribute to signal attenuation is surface roughness of the conductive layer through which the signals pass. PCB manufacturers who laminate several dielectric and conductive layers to form the final board structure desire some level of roughness to promote adhesion between the two materials. Unfortunately, such roughness may also adversely affect signal passage if too excessive. As understood from the teachings herein, the instant invention is able to provide conductive layers with optimal roughness for sound adhesion to corresponding dielectric layers during bonding of such layers but also layers that are smooth enough that the surface irregularities of such layers do not significantly impede signal passage.
It is to be understood that the teachings of the present invention are not limited to the manufacture of high speed substrates such as PCBs and the like, but are also applicable to the manufacture of substrates used for other purposes than high speed signal connections. Generally speaking, the teachings herein are applicable to any such substrates in which one or more conductive layers such as copper are bonded (e.g., laminated) to an adjacent dielectric layer and the resulting composite then used as the substrate, typically when combined with other dielectric and conductive layers to form a much thicker, built-up structure. The invention is able to provide a final structure in which signal attenuation is reduced while still assuring effective conductive layer and dielectric layer adhesion.
With respect to the circuit (wiring) patterns being formed on substrates of many types of PCBs, including high speed boards as well as others, line widths may now be as small as ten-odd microns. Accordingly, the conductive layers (some also referred to as metal “foils” in the art) are becoming much thinner than those which produced wider lines in previous substrates. By way of example, when the designated thickness of metal foil for use in the formation of the conventional wiring pattern of about 100 micron line width has ranged from about 15 to 35 microns, the thickness of metal foil utilized in the formation of ten-odd micron wiring patterns must be reduced correspondingly. To accomplish this, an aluminum or copper foil may be used. Preferably, copper is used, especially an electrodeposited copper foil, produced by electrodepositing copper on a drum surface. With respect to such electrodeposited copper foil, the surface at which copper deposition is initiated (the surface at which formation of copper deposits brought into contact with the drum is initiated) is referred to as “shiny side”, and the surface at which copper deposition is completed is referred to as “matte side”. The surface condition of the shiny side is substantially the same as that of the drum. That is, the RMS surface roughness value (a conventional measurement of metal surface roughness for layers used in PCBs; see more below) of the drum is from about 0.1 to 0.5 microns with a maximum peak to valley roughness value from about 1.0 to 2.0 microns. (Maximum peak to valley roughness is another means of characterizing surface roughness of a metal layer such as copper foil used in PCBs) As a result, the “shiny” side of the electrodeposited copper formed on this drum (and against the drum's outer surface) has a similar roughness. On the other hand, with respect to the outer matte side of the formed copper layer, its surface roughness is greater than the surface roughness of the shiny side, typically having an RMS value of from about 1.0 to about 2.0 microns with a maximum peak to valley roughness in the range of about 3.0 to 10 microns.
There are various different methods of characterizing surface roughness in the industry including Ra (average roughness or the arithmetic average above and below the center line in a segment), Rq (or RMS, which is the square root of the average of the squared absolute distances of the surface profile from the mean line), Rt (maximum peak to valley or the height difference between the highest and lowest points in a segment) and Rz (the 10 point average surface roughness). RMS (Rq) values will be used herein and simply referred to as “RMS roughness” for ease of explanation purposes.
In the case of conventional electrodeposited copper foils, it is known to subject these foils to various treatments prior to inclusion thereof as part of a dielectric-conductive layer composite (or, more likely, a sub-composite if used in combination with other sub-composites to form a multi-layered built-up final board), including treating the foil for the purpose of increasing adhesion between the foil and dielectric layer(s) in the final structure. For example, mechanical polishing is a method of smoothing the surface of the copper foil with the use of mechanical means, usually in the form of a buffer. Unfortunately, if the foil is too thin, it may be damaged, e.g., severed or torn in sections, from the relatively high stresses exerted on the copper foil during this processing. Thus, mechanical polishing is considered suitable for preparing the surface of relatively thick copper foils only. In comparison, chemical and electrolytic polishing processes exert virtually no relatively high stresses on copper foils so it is believed that relatively thin foils may be successfully treated using one or both of these processes. However, such processes are typically expensive to operate, often requiring relatively expensive equipment, costly chemical baths, as well as prolonged periods during which the foil is so treated, thereby extending the total time of manufacture of the end product.
In U.S. Pat. No. 6,475,638 (Mitsuhashi et al), there is described a process for producing an electrodeposited copper foil with its surface prepared which includes the steps of subjecting the foil having a shiny side and a matte side to at least one mechanical polishing so that the average surface roughness (Rz) of the matte side becomes in the range of 1.5 to 3.0 microns. The matte side is then subjected to a selective chemical polishing so that the average surface roughness (Rz) of the matte side becomes in the range of 0.8 to 2.5 microns. The mechanical polishing followed by chemical polishing of the matte side enables the foil to exhibit excellent properties, according to the authors.
In U.S. Pat. No. 6,291,081 (Kurabe et al), there is described a process for producing an electrodeposited copper foil including the steps of subjecting an electrodeposited copper foil having a shiny side and a matte side to a first mechanical polishing and then subjecting the matte side having undergone the first mechanical polishing to a further mechanical polishing. A planar, highly polished face with excellent surface properties is allegedly obtained. Moreover, depressed parts are not polished, so that the amount of copper lost by the polishing steps is extremely minute.
In U.S. Pat. No. 5,897,761 (Tagusari et al), there is described an electrodeposited copper foil for use in the manufacture of printed wiring boards in which the original profile of the matte surface has been completely removed, preferably by buffing, leaving a surface having linear streaks and a certain roughness. The new surface is then given a nodule forming treatment which produces a second surface roughness, which may be followed by a corrosion resisting treatment. U.S. Pat. No. 5,858,517 (also Tagusari et al) also describes a similar process with what are considered minor modifications.
In U.S. Pat. No. 5,545,466 (Saida et al), there is described a copper-clad laminate characterized in that an electrolytic copper foil on the glossy (shiny) surface side of which a copper electrodeposit is formed, is bonded at its glossy surface side to one side or each of both sides of a substrate, which has a fine-pitch wiring (circuit) pattern and exhibits a high etching factor. This patent is a continuation-in-part of U.S. Pat. No. 5,437,914 (Saida et al), below.
In U.S. Pat. No. 5,482,784 (Ohara et al), there is described a printed circuit inner-layer copper foil having inverted tear drop-shaped fine nodules formed on both surfaces of the copper foil, the nodules each having a specific length and maximum diameter.
In U.S. Pat. No. 5,437,914 (Saida et al), there is described a copper-clad laminate characterized in that an electrolytic copper foil on the glossy surface side of which a copper electrodeposit is formed is bonded at its glossy surface side to one side or each of both sides of a substrate.
In U.S. Pat. No. 5,096,522 (Kawachi et al), there is described a process for producing a copper-clad laminate which includes the steps of contacting the surface of a conductive carrier with a catalyst liquid containing a noble metal selected from the group consisting of Pd, Pt, Ru, Au, and Ag, subsequently forming a copper foil layer on the treated surface by copper electroplating, laminating an insulating base on the copper foil layer by hot-press bonding, and then separating the conductive carrier from the resulting laminate. The copper foil layer in the resulting copper-clad laminate is claimed to have fewer pinholes and allegedly exhibits isotropic mechanical characteristics.
In four U.S. Patents cited below with respect to the definition of what is meant by a “fluid treatment device”, there are described various embodiments of fluid treatment apparatus/assemblies which are specifically designed for applying precisely directly pressurized jets of fluid onto designated locations on the surface of a nearby material. As defined in these patents, such materials are typically passed through the apparatus/assembly with the fluid directed onto opposite sides thereof from the oppositely positioned sprayers, but may only be directed onto one of the sides, if desired. The various pressures attainable using these structures are defined in detail in many of these patents.
In Japanese Patent Unexamined Publication Hei 5-160208, there is disclosed a tape carrier having a lead pattern formed from an electrodeposited copper foil wherein the overall surface of the foil's matte side has been polished. This publication describes the use of an electrodeposited copper foil whose 1-2 micron matte side surface profile has been chemically polished. It is mentioned that a highly reliable carrier tape with desired lead strength can be provided by the use of the copper foil whose matte side overall surface has been so chemically polished.
According to the teachings of the present invention, there is defined a circuitized substrate in which a conductive layer (e.g., electroplated copper foil) is mated with another and bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric is smooth while the outer surfaces of both foils, albeit rougher than the facing sides, are also smooth. One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. The signal lines may be extremely thin and also extremely narrow in width, in which case these are still able to enable the passage of high speed signals there-through. As stated, however, the invention is not limited to substrates with extremely thin and narrow signal lines, as it is clear from the teachings herein that substrates having thicker and wider lines than defined herein may be successfully produced.
It is believed that such a substrate and method of making same, as well as resulting electrical assemblies and information handling systems utilizing same, will represent significant advancements in the art.
It is, therefore, a primary object of the present invention to enhance the circuitized substrate art by providing a circuitized substrate having the advantageous features taught herein.
It is another object of the invention to provide a method of making such a circuitized substrate which can be accomplished in a relatively facile manner and at relatively low costs.
It is still another object of the invention to provide an electrical assembly capable of using such a circuitized substrate and thus benefiting from the several advantageous features thereof,
It is yet another object of the invention to provide an information handling system capable of utilizing a circuitized substrate as part thereof to thus also benefit from the several advantageous features thereof.
According to one aspect of the invention, there is provided a method of making a circuitized substrate comprising providing at least one dielectric layer, providing first and second electrically conductive layers each having a first side of a first, relatively low roughness and a second side of a roughness greater than that of the first sides, treating these first sides of the first and second electrically conductive layers with a chemical treatment so as to minimally increase the roughness of the first sides, bonding the first sides of the first and second electrically conductive layers following the treating of these first sides to the dielectric layer such that the dielectric layer is positioned substantially between the first and second electrically conductive layers, treating the second sides of the first and second electrically conductive layers having the roughness greater than that of the first sides with a chemical treatment so as to reduce both the roughness of the second sides and the thickness of the first and second electrically conductive layers, and then forming a circuit pattern within at least one of the electrically conductive layers.
According to another aspect of the invention, there is provided a circuitized substrate comprising at least one dielectric layer having first and second opposite sides, first and second electrically conductive layers each having a first smooth side having a thin organic layer thereon bonded to the first and second opposite sides of the at least one dielectric layer, respectively, and a second etched smooth side opposite the first smooth side, and a circuit pattern formed within at least one of the electrically conductive layers having the first smooth side and second etched smooth side.
According to still another aspect of the invention, there is provided an electrical assembly comprising a circuitized substrate having at least one dielectric layer having first and second opposite sides, first and second electrically conductive layers each having a first smooth side having a thin organic layer thereon bonded to the first and second opposite sides of the at least one dielectric layer, respectively, and a second etched smooth side opposite the first smooth side, and a circuit pattern formed within at least one of the electrically conductive layers having the first smooth side and second etched smooth side, and at least one electrical component positioned on and electrically coupled to the circuitized substrate.
According to yet another aspect of the invention, there is provided an information handling system comprising a housing, a circuitized substrate positioned within the housing and including at least one dielectric layer having first and second opposite sides, first and second electrically conductive layers each having a first smooth side having a thin organic layer thereon bonded to the first and second opposite sides of the at least one dielectric layer, respectively, and a second etched smooth side opposite the first smooth side, and a circuit pattern formed within at least one of the electrically conductive layers having the first smooth side and second etched smooth side, and at least one electrical component positioned on and electrically coupled to the circuitized substrate.
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. Like figure numbers will be used from FIG. to FIG. to identify like elements in these drawings.
By the term “circuitized substrate” as used herein is meant to include substrates having at least one dielectric layer and at least two metallurgical conductive layers. Examples include structures made of dielectric materials such as fiberglass-reinforced epoxy resins (some referred to as “FR-4” dielectric materials in the art), polytetrafluoroethylene (Teflon), polyimides, polyamides, cyanate resins, polyphenylene ether resins, photoimageable materials, and other like materials wherein the conductive layers are each a metal layer (e.g., power, signal and/or ground) comprised of suitable metallurgical materials such as copper (preferably electrodeposited copper foil as defined herein-above), but in the broader aspects may also include additional metals (e.g., nickel, aluminum, etc.) or alloys thereof. Further examples will be described in greater detail herein-below. If the dielectric materials for the structure are of a photoimageable material, it is photoimaged or photopatterned, and developed to reveal the desired circuit pattern, including the desired opening(s) as defined herein, if required. The dielectric material may be curtain-coated or screen- applied, or it may be supplied as dry film. Final cure of the photoimageable material provides a toughened base of dielectric on which the desired electrical circuitry is formed. An example of a specific photoimageable dielectric composition includes a solids content of from about 86.5 to about 89%, such solids comprising: about 27.44% PKHC, a phenoxy resin; 41.16% of Epirez 5183, a tetrabromobisphenol A; 22.88% of Epirez SU-8, an octafunctional epoxy bisphenol A formaldehyde novolac resin; 4.85% UVE 1014 photoinitiator; 0.07% ethylviolet dye; 0.03% FC 430, a fluorinated polyether nonionic surfactant from 3M Company; 3.85% Aerosil 380, an amorphous silicon dioxide from Degussa to provide the solid content. A solvent is present from about 11 to about 13.5% of the total photoimageable dielectric composition. The dielectric layers taught herein may be typically about 2 mils to about 4 mils thick, but also thicker if desired. Examples of circuitized substrates include printed circuit boards (or cards), hereinafter referred to also as PCBs, and chip carriers. It is believed that the teachings of the instant invention are also applicable to what are known as “flex” circuits (which use dielectric materials such as polyimide).
By the term “electrical component” as used herein is meant components such as semiconductor chips, resistors, capacitors and the like, which are adapted for being positioned on the external conductive surfaces of such substrates as PCBs and chip carriers, and possibly electrically coupled to other components, as well as to each other, using, for example the PCB's or chip carrier's internal and/or external circuitry.
By the term “electrical assembly” is meant at least one circuitized substrate as defined herein in combination with at least one electrical component electrically coupled thereto and forming part of the assembly. Examples of known such assemblies include chip carriers which include a semiconductor chip as the electrical component, the chip usually positioned on the substrate and coupled to wiring (e.g., pads) on the substrate's outer surface or to internal conductors using one or more thru-holes. Perhaps the most well known such assembly is the conventional PCB having several external components such as resistors, capacitors, modules (including one or more chip carriers) etc. mounted thereon and coupled to the internal circuitry of the PCB.
By the term “information handling system” as used herein shall mean any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as servers, mainframes, etc. Such systems typically include one or more PCBs, chip carriers, etc. as integral parts thereof. For example, a PCB typically used includes a plurality of various components such as chip carriers, capacitors, resistors, modules, etc. mounted thereon. One such PCB can be referred to as a “motherboard” while various other boards (or cards) may be mounted thereon using suitable electrical connectors.
By the term “smooth” as used herein to define the surface roughness of a side of an electrically conductive layer such as an electrodeposited copper foil is meant a layer side having an RMS surface roughness of from about 0.1 to about 0.6 microns.
By the term “fluid treatment device” as used herein is meant a pressurized fluid spray apparatus/assembly adapted for precisely directing pressurized jets of fluid onto the surface of a material, typically as the material is passed there-through in the situation where such jets impinge from opposite sides of the material or, in its simplest form, where such apparatus/assembly utilizes such jets only on one side of the material and thus fluid is impinged on only said side. Apparatus/assemblies of this type are defined in U.S. Pat. No. 5,512,335 (Miller et al), U.S. Pat. No. 5,378,307 (Bard et al), U.S. Pat. No. 5,289,639 (Bard et al) and U.S. Pat. No. 5,063,951 (Bard et al), the teachings of these patents being incorporated herein by reference. In its simplest form, such as shown in U.S. Pat. Nos. 5,063,951 and 5,289,639, the device will include a plurality of such jets oriented in rows under or over which the material being treated will pass and receive pressurized fluid, e.g., etchants, water rinse, etc. thereon. Additional structure, such as vibration means may be utilized, as defined in U.S. Pat. No. 5,512,335, as well as an overflow sump arrangement with a plurality of such devices spacedly positioned there-along. An example of this latter apparatus/assembly is defined in U.S. Pat. No. 5,378,307.
As stated, a key aspect of this invention is the provision of smooth surfaced conductive layers in a final product which serve to substantially prevent signal attenuation when signals are passed there-through, but which are also “rough” enough to promote secure adhesion to corresponding dielectric layers when bonded thereto including such relatively harsh PCB production processes as lamination. This requisite laminate adhesion value is deemed to be at least three pounds per linear inch of the copper surface. To accomplish this using the new and unique teachings herein, side 13 of layer 11 is subjected to a chemical treatment in which the side is exposed to a solution containing acid, peroxide and a metal (preferably, copper). One preferred process involves processing the invention's foils through what is referred to as a “BondFilm” solution currently available on the marketplace under this name from Atotech Deutschland GmbH, an international company having a U.S.A. business address at 1750 Overview Drive, Rock Hill, S.C. The term “BondFilm” is a trademark of Atotech Deutschland GmbH. This BondFilm solution is comprised primarily of three components: (1) sulfuric acid; (2) hydrogen peroxide; and (3) copper, as well as additional Atotech Deutschland GmbH proprietary constituents. This process is also referred to as an oxide alternative process, meaning that it does not result in the formation of oxide layers on the treated material.
The copper conductive layers (a minimum of two, foils 11, as shown in
In the simplest embodiment of the invention, as indicated above, two foils 11 are required, as shown in
Although it is shown in
It is understood that in its simplest form, the structure depicted in
In one embodiment of the invention, the lower conductive layer may serve as a power or ground plane for the substrate and is thus spaced from the upper signal plane by the thickness of dielectric 17. If such a plane, it is desirable to provide a plurality of clearance openings 18 (shown hidden in
Thus there has been shown and described a circuitized substrate which utilizes at least one dielectric layer with at least one conductive plane on opposite sides thereof which is formed in a new and unique manner so as to enhance the passage of high speed and other signals there-through. The conductive foils rendered substantially “smooth” on each surface in accordance with the teachings herein exhibited significantly lower signal (attenuation) losses at the 1.5 GHz (gigahertz) range. Additionally, as frequencies increased (e.g., from about 1 to about 10 GHz), the rate of loss (in decibels per inch) dropped significantly in comparison to the copper layers of greater roughness. In one example of the invention, two separate substrates were prepared. One was prepared having 1.4 mil thick circuit lines with corresponding widths of 5 mils each. The copper surface RMS roughness was 0.3 microns on one side and 1.5 microns on the other side for this one substrate. Polyclad LD-621 (a glass cloth reinforced polyphenylene ether resin dielectric material available from Cookson Electronics having an office at 144 Harvey Road, Londonderry, N.H.) was used as the dielectric material. Measured signal attenuation for a 20 centimeter signal line length at a frequency of about 1.5 GHz was 1.5 dBs (decibels). In sharp comparison, the second substrate prepared of the same dielectric and copper materials and thicknesses according to the teachings of this invention used copper foils with an RMS surface roughness of 0.3 microns on both sides of the foil. The measured signal attenuation for the signal lines of this second substrate was significantly lower, at about only 1.2 dBs.
The various structures which may utilize one or more circuitized substrates taught herein thus also inherit the several advantageous features of this structure. The circuitized substrate as defined may be produced using known PCB and/or chip carrier or the like manufacturing processes and are thus producible at relatively low cost, enabling the passage of such low costs on to assemblies utilizing these substrates.
While there have been shown and described what are at present the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.
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|U.S. Classification||29/846, 428/687, 428/901, 216/105, 216/38, 428/624, 29/847, 29/830|
|International Classification||H05K3/06, H05K3/46, H05K3/38|
|Cooperative Classification||Y10T29/49155, H01L2224/73253, H05K3/4641, H01L2224/16, H05K2201/0355, Y10T428/12993, H05K2201/09318, H01L2924/01079, Y10T29/49156, H01L2924/3011, Y10T29/49126, H05K3/383, H01L21/4857, H01L2924/16195, H05K2203/0353, H01L2924/01078, H01L2924/01087, Y10T428/12556, H01L2924/01046, H01L2924/15311, H01L2924/01021, Y10S428/901|
|European Classification||H01L21/48C4D, H05K3/38C2, H05K3/46B8|
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|May 6, 2013||AS||Assignment|
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