Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7390712 B2
Publication typeGrant
Application numberUS 11/796,773
Publication dateJun 24, 2008
Filing dateApr 30, 2007
Priority dateJun 21, 2000
Fee statusPaid
Also published asUS7009240, US7232721, US20050032299, US20060131615, US20070207588
Publication number11796773, 796773, US 7390712 B2, US 7390712B2, US-B2-7390712, US7390712 B2, US7390712B2
InventorsCem Basceri, Vishnu K. Agarwal, Dan Gealy
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods of enhancing capacitors in integrated circuits
US 7390712 B2
Abstract
Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.
Images(18)
Previous page
Next page
Claims(26)
1. A method comprising:
forming a layer of a conductive compound;
crystallizing the layer to form ruthenium dioxide and ruthenium; and
forming a dielectric over the layer.
2. The method of claim 1, wherein the conductive compound includes RuOx, wherein the x is indicative of a number of atoms.
3. The method of claim 1, wherein the dielectric includes ditantalum pentaoxide.
4. The method of claim 1, wherein the layer is formed at about 210 degrees Celsius.
5. The method of claim 1, wherein the layer is formed with about 200 standard cubic centimeters per minute (sccm) of Ru-HEC.
6. The method of claim 5, wherein the layer is formed with about 250 standard cubic centimeters per minute (sccm) of O2.
7. The method of claim 6, wherein the layer is formed at a pressure of about 2.5 torrs.
8. A method comprising:
forming a conductive layer of ruthenium and oxygen;
crystallizing the conductive layer to form RuO2 and Ru;
forming a layer of Ta2O5 over the conductive layer; and
crystallizing the layer of Ta2O5 to form crystallized Ta2O5.
9. The method of claim 8, wherein forming the conductive layer includes a chemical vapor deposition.
10. The method of claim 8, wherein crystallizing the conductive layer includes crystallizing at a temperature greater than about 750 degrees Celsius and less than about 800 degrees Celsius.
11. The method of claim 8, wherein crystallizing the conductive layer includes crystallizing in an ambient of nitrogen.
12. The method of claim 8, wherein crystallizing to form crystallized Ta2O5 layer includes crystallizing at a temperature of about 800 degrees Celsius.
13. The method of claim 8, wherein crystallizing to form crystallized Ta2O5 includes crystallizing in an ambient of oxygen.
14. The method of claim 8, wherein the crystallized Ta2O5 includes permittivity greater than about 25.
15. A method comprising:
forming a transistor; and
forming a capacitor coupled to the transistor, wherein forming the capacitor includes forming a capacitor plate having a conductive compound, crystallizing the capacitor plate to form ruthenium dioxide and ruthenium, and forming a dielectric over the capacitor plate.
16. The method of claim 15, wherein the dielectric directly contacts the capacitor plate.
17. The method of claim 16 comprising:
forming an additional capacitor plate, wherein the additional capacitor plate directly contacts the dielectric.
18. The method of claim 17, wherein the dielectric includes ditantalum pentaoxide.
19. The method of claim 17, wherein the additional capacitor plate includes one of TIN, TiON, WNx, TaN, Ta, Pt, Pt-Rh, Pt-RhOx, Ru, RuOx, Ir, IrOx, Pt-Ru, Pt-RuOx, Pt-Ir, Pt-IrOx, SrRuO3, Au, Pd, Al, Mo, Ag, and Poly-Si.
20. A method comprising:
forming a transistor; and
forming a capacitor coupled to the transistor, wherein forming the capacitor includes forming a conductive layer of ruthenium and oxygen, crystallizing the conductive layer to form RuO2 and Ru, and forming a crystallized layer of Ta2O5 over the conductive layer.
21. The method of claim 20, wherein the crystallized Ta2O5 includes substantially a (001) lattice plane.
22. The method of claim 20, wherein the crystallized layer of Ta2O5 directly contacts the conductive layer.
23. The method of claim 22 comprising:
forming an additional conductive layer, wherein the additional conductive layer directly contacts the crystallized layer of Ta2O5.
24. The method of claim 20, wherein crystallizing the conductive layer includes crystallizing at a temperature greater than about 750 degrees Celsius.
25. The method of claim 20, wherein forming the crystallized Ta2O5 includes crystallizing a layer of Ta2O5 to form the crystallized Ta2O5 after the conductive layer is crystallized.
26. The method of claim 25, wherein crystallizing the layer of Ta2O5 includes crystallizing in an ambient of dinitrogen oxide.
Description

This application is a Continuation of U.S. application Ser. No. 10/931,396, filed Aug. 31, 2004, now U.S. Pat. No. 7,232,721 which is divisional of U.S. application Ser. No. 09/598,355, filed Jun. 21, 2000, now U.S. Pat. No. 7,009,240, which are incorporated herein by reference.

TECHNICAL FIELD

The technical field relates generally to semiconductor integrated circuits. More particularly, it pertains to capacitors in semiconductor integrated circuits.

BACKGROUND

A capacitor is composed of two layers of a material that is electrically conductive (hereinafter, electrode) brought near to one another and separated by a material that is electrically nonconductive. Suppose the capacitor is connected to a battery with a certain voltage level (hereinafter, energy level). Charges will flow from the battery to be stored in the capacitor until the capacitor exhibits the energy level of the battery. Then, suppose further that the capacitor is disconnected from the battery. The capacitor will indefinitely exhibit the energy level of the battery until the charges stored in the capacitor are removed either by design or by accident.

This ability of the capacitor to “remember” an energy level is valuable to the operation of semiconductor integrated circuits. Often, the operation of such circuits may require that data be stored and retrieved as desired. Because of its ability to remember, the capacitor is a major component of a semiconductor memory cell. One memory cell may store one bit of data. A system of memory cells is a semiconductor memory array where information can be randomly stored or retrieved from each memory cell. Such a system is also known as a random-access memory.

One type of random-access memory is dynamic random-access memory (DRAM). The charges stored in DRAM tend to leak away over a short time. It is thus necessary to periodically refresh the charges stored in the DRAM by the use of additional circuitry. Even with the refresh burden, DRAM is a popular type of memory because it can occupy a very small space on a semiconductor surface. This is desirable because of the need to maximize storage capacity on the limited surface area of an integrated circuit

One type of capacitor that supports an increase in storage capacity uses a metal substance as a bottom electrode and an electrically nonconductive material that has a high dielectric constant. The metal substance tends to create undesired atomic diffusion in an environment with a high temperature. Such a high temperature, however, is needed to further process the electrically nonconductive material. The undesired atomic diffusion may act to degrade the electrically nonconductive material. That act compromises the ability of the capacitor to maintain the charges. This is detrimental to the storage ability of the capacitor and would render such a memory cell defective.

Thus, what is needed are systems, devices, structures, and methods to inhibit the described effect so as to enhance capacitors with a high dielectric constant in manufacturing environments exhibiting high temperatures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention.

FIG. 2 is an elevation view of a semiconductor memory array according to one embodiment of the present invention.

FIGS. 3A-3K are cross-sectional views of a semiconductor structure during processing according to one embodiment of the present invention.

FIG. 4 is a block diagram of a device according to one embodiment of the present invention.

FIG. 5 is an elevation view of a semiconductor wafer according to one embodiment of the present invention.

FIG. 6 is a block diagram of a circuit module according to one embodiment of the present invention.

FIG. 7 is a block diagram of a memory module according to one embodiment of the present invention.

FIG. 8 is a block diagram of a system according to one embodiment of the present invention.

FIG. 9 is a block diagram of a system according to one embodiment of the present invention.

FIG. 10 is a block diagram of a system according to one embodiment of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the embodiments of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the embodiments of the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the embodiments of the present invention.

The terms wafer and substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure and layer formed above, and the terms wafer or substrate include the underlying layers containing such regions/junctions and any layer that may have been formed above. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the embodiments of the present invention is defined only by the appended claims.

FIG. 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention. The semiconductor structure 100 may illustrate an example of a single DRAM cell. The semiconductor structure 100 includes a substrate 102, field isolators 104, transistor 134, insulation layers 120, another semiconductor structure such as a capacitor 136, and a metallization layer 140. In one embodiment, the metallization layer 140 may be considered a conductive plug. In another embodiment, the conductive plug includes polysilicon. The transistor 134 includes source/drain regions 106 0 and 106 1, silicide region 108, spacers 112, gate oxide 114, and gate 116. The source/drain regions 106 0 and 106 1 include lightly doped source/drain regions 110. The capacitor 136 includes an electrode 124, a dielectric layer 126, and another electrode 128. The dielectric layer 126 is coupled to the electrodes 124 and 128.

Charges can be transferred into or removed from the capacitor 136 by turning on the transistor 134. The transistor 134 is turned on by an appropriate voltage level and polarity placed at the gate 116 so that a depletion region and conducting channel are formed between the source/drain regions 106 0 and 106 1. If charges are to be transferred into the capacitor 136, these charges are introduced at the source/drain region 106 0 by a buried bit line 141, so that they may travel across the conducting channel into the source/drain region 106 1, conduct through the metallization layer 140, and enter the electrode 124. The charges cannot go any further because the dielectric layer 126 is electrically nonconductive. However, these charges will attract opposite polarity charges to appear at electrode 128. Hence, an electric field is set up between the electrodes 124 and 128. Energy is stored in this electric field. This electric field is the phenomenon that allows the capacitor to “remember.”

There exists an industry-wide drive to smaller memory cells to increase storage density on the limited surface area of an integrated circuit. This has motivated the use of a thin film nonconductive material for use as a dielectric 126 of the capacitor 136. High temperatures may be used in the processing of the semiconductor structure 100. Such high temperatures may cause the bottom electrode 124 to undesirably act with a portion of the semiconductor structure 100, such as the dielectric 126 of the capacitor 136. Such action may degrade the properties of the dielectric 126 to cause the capacitor 136 to become defective over time.

One example of the degradation of the dielectric 126 includes the use of a metal substance for the bottom electrode 124. A high temperature (about 750 degrees Celsius or greater) is used to crystallize the dielectric 126. At such a high temperature, thermal vibration in the crystal structure of the metal substance increases, thereby increasing the likelihood of structural disruption. Such a structural disruption introduces point defects, such as vacancies in the crystal structure of the metal substance. Suppose that the dielectric 126 includes a compound comprising another metal substance and nonmetal atoms. Under the environment as described above, nonmetal atoms of the dielectric 126 may diffuse to fill the point defects in the crystal structure of the metal substance of the bottom electrode 124. Such a diffusion may short-circuit the capacitor 136. This may occur because the metal substance of the dielectric 126 in the absence of the nonmetal atoms may conductively couple the electrode 124 to the electrode 128.

One solution includes using lower temperatures (750 degrees Celsius or lower) to crystallize the dielectric 126. However, at such temperatures, the dielectric 126 tends to exhibit high leakage values. This may be attributed to insufficient incorporation of the nonmetal atoms with the metal atoms in the crystal structure of the dielectric 126 at low temperatures. Thus, this solution is inadequate.

The embodiments of the present invention solve the above-discussed problem while enhancing the dielectric 126. In one embodiment, a semiconductor structure for storing charges includes an insulator layer having a first compound that includes substances, and a conductive layer having a second compound that includes a first substance and a second substance. The second compound in an as-deposited state includes a substantial amount of the second substance so as to inhibit undesired diffusion of at least one substance of the first compound from the insulator layer.

In another embodiment, the semiconductor structure includes an insulator layer and a conductive layer having a compound formed from a first substance and a second substance; the conductive layer includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the insulator layer.

In another embodiment, the semiconductor structure includes an insulator layer having a permittivity value greater than about 25, and a conductive layer having a compound. The compound remains stable when the insulator layer is crystallized at a high temperature so as to decrease the charge leakage of the insulator layer. In one embodiment, the insulator layer passivates the conductive layer from undesired oxidation.

In another embodiment, the semiconductor structure includes an insulator layer having a permittivity value, and a conductive layer abuttingly coupled to the insulator layer. The crystalline structure of the insulator layer describes a desired lattice plane such that the permittivity value of the insulator layer is greater than about 25. The desired lattice plane includes substantially a (001) plane. In another embodiment, the desired lattice plane is described by three axes; the desired plane is parallel to two of the three axes and intersects one of the three axes.

In another embodiment, the capacitor 136 includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound that includes a first substance and a second substance. The compound in an as-deposited state includes a substantial amount of the second substance so as to inhibit undesired diffusion at a high temperature. The compound includes ruthenium oxide (RuOx). The x is indicative of a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound that includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. The compound includes RuOx. The x is indicative of a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The crystalline structure of the dielectric describes a (001) lattice plane. The compound includes RuOx. The x is indicative of a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, a dielectric having a first compound that includes a first substance and a second substance, and a second electrode having a second compound that includes a third and a fourth substance. The first compound includes ditantalum pentaoxide. The second electrode includes a trace amount of the third substance. The second compound in an as-deposited state includes a substantial amount of the fourth substance. The trace amount of the third substance is oxidized during the crystallization of the dielectric such that a diffusion of at least one of the first substance and the second substance is inhibited. The crystalline structure of the dielectric describes substantially a (001) lattice plane. The compound includes RuOx. The x is indicative of a desired number of atoms.

In another embodiment, the capacitor 136 includes a first electrode, a dielectric having a first compound that includes a first substance and a second substance, and a second electrode having a second compound that includes a third substance and a fourth substance. The first electrode has a substance that is selected from a group consisting of TiN, TiON, WNx, TaN, Ta, Pt, Pt—Rh, Pt—RhOx, Ru, RuOx, Ir, IrOx, Pt—Ru, Pt—RuOx, Pt—Ir, Pt—IrOx, SrRuO3, Au, Pd, Al, Mo, Ag, and Poly-Si. The first compound includes ditantalum pentaoxide. The second electrode includes a trace amount of the third substance. The second compound in an as-deposited state includes a substantial amount of the fourth substance. The trace amount of the third substance is oxidized during the crystallization of the dielectric such that a diffusion of at least one of the first substance and the second substance is inhibited. The crystalline structure of the dielectric describes substantially a (001) lattice plane. The second compound includes RuOx, wherein the x is indicative of a desired number of atoms.

FIG. 2 is an elevation view of a semiconductor memory array according to one embodiment of the present invention. The memory array 200 includes memory cell regions 242 formed overlying active areas 250. Active areas 250 are separated by field isolation regions 252. Active areas 250 and field isolation regions 252 are formed overlying a semiconductor substrate.

The memory cell regions 242 are arrayed substantially in rows and columns. Shown in FIG. 2 are portions of three rows 201A, 201B and 201C. Separate digit lines (not shown) would be formed overlying each row 201 and coupled to active areas 250 through digit line contact regions 248. Word line regions 244 and 246 are further coupled to active areas 250, with word line regions 244 coupled to active areas 250 in row 201B and word line regions 246 coupled to active areas 250 in rows 201A and 201C. The word line regions 244 and 246, coupled to memory cells in this alternating fashion, generally define the columns of the memory array. This folded bit-line architecture is well known in the art for permitting higher densification of memory cell regions 242.

FIGS. 3A-3K are cross-sectional views of a semiconductor structure during processing according to one embodiment of the present invention. FIGS. 3A-3K are cross-sectional views taken along line A-AN of FIG. 2 during various processing stages.

Semiconductor structure 300 includes a substrate 302. The substrate 302 may be a silicon substrate, such as a p-type silicon substrate. Field isolators 304 are formed over field isolation regions 352 of the substrate 302. Field isolators 304 are generally formed of an insulator material, such as silicon oxides, silicon nitrides, or silicon oxynitrides. In this embodiment, field isolators 304 are formed of silicon dioxide such as by conventional local oxidation of silicon which creates substantially planar regions of oxide on the substrate surface. Active area 350 is an area not covered by the field isolators 304 on the substrate 302. The creation of the field isolators 304 is preceded or followed by the formation of a gate dielectric layer 314. In this embodiment, gate dielectric layer 314 is a thermally grown silicon dioxide, but other insulator materials may be used as described herein.

The creation of the field isolators 304 and gate dielectric layer 314 is followed by the formation of a conductively doped gate layer 316, silicide layer 308, and gate spacers 312. These layers and spacers are formed by methods well known in the art. The foregoing layers are patterned to form word lines in word line regions 344 and 346. A portion of these word lines is illustratively represented by gates 338 0, 338 1, 338 2, and 338 3. In one embodiment, the silicide layer 308 includes a refractory metal layer over the conductively doped gate layer 316, such as a polysilicon layer.

Source/drain regions 306 are formed on the substrate 302 such as by conductive doping of the substrate. Source/drain regions 306 have a conductivity opposite the substrate 302. For a p-type substrate, source/drain regions 306 would have an n-type conductivity. The source/drain regions 306 include lightly doped source/drain regions 310 that are formed by implanting a low-dose substance, such as an n-type or p-type material. Such lightly doped source/drain regions 310 help to reduce high field in the source/drain junctions of a small-geometry semiconductor structure, such as semiconductor structure 300. In one embodiment, each of the gates 338 0, 338 1, 338 2, and 338 3 is enclosed by a nitride compound layer. The nitride compound layer includes a molecular formula of SixNy. The variables x and y are indicative of a desired number of atoms. The portion of the word lines that are illustratively represented by gates 338 0, 338 1, 338 2, and 338 3 is adapted to be coupled to periphery contacts (not shown). The periphery contacts are located at the end of a memory array and are adapted for electrical communication with external circuitry.

The foregoing discussion is illustrative of one example of a portion of a fabrication process to be used in conjunction with the various embodiments of the invention. Other methods of fabrication are also feasible and perhaps equally viable. For clarity purposes, many of the reference numbers are eliminated from subsequent drawings so as to focus on the portion of interest of the semiconductor structure 300.

FIG. 3B shows the semiconductor structure following the next sequence of processing. A thick insulation layer 320 is deposited overlying substrate 302 as well as field isolation regions 352 and active regions 350. Insulation layer 320 is an insulator material such as silicon oxide, silicon nitride, and silicon oxynitride. In one embodiment, insulation layer 320 is a doped insulator material such as borophosphosilicate glass (BPSG), a boron and phosphorous-doped silicon oxide. The insulation layer 320 is planarized, such as by chemical-mechanical planarization (CMP), in order to provide a uniform height.

FIG. 3C shows the semiconductor structure following the next sequence of processing. The first inhibiting layer 330 0 is optionally formed on or abutting the insulation layer 320. The first inhibiting layer 330 0 includes a nitride compound. In one embodiment, the first inhibiting layer 330 0 includes a metal nitride compound. The nitride compound includes a substance with a molecular formula of SixNy. The variables x and y are indicative of the desired number of atoms.

The first inhibiting layer 330 0 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD), or other deposition techniques. In this embodiment, the first inhibiting layer 330 0 is patterned to form the first inhibiting layer of a semiconductor structure of interest, such as a capacitor.

FIG. 3D shows the semiconductor structure following the next sequence of processing. The semiconductor structure 300 is patterned using photolithography with appropriately placed masks to define future locations of memory cells. Then portions of the first inhibiting layer 330 0 and the insulation layer 320 are exposed and removed along with the masks. These portions of the first inhibiting layer 330 0 and the insulation layer 320 may be removed by etching or other suitable removal techniques known in the art. Removal techniques are generally dependent on the material of construction of the layer to be removed as well as the surrounding layers to be retained. Patterning of the first inhibiting layer 330 0 and the insulation layer 320 creates openings having bottom portions exposed to portions of the silicide region 308 and sidewalls defined by the insulation layer 320. A metallization layer 340 is formed on the silicide region 308 using a suitable deposition technique. In one embodiment, the metallization layer 340 may be considered a conductive plug. In another embodiment, the conductive plug includes conductive polysilicon.

FIG. 3E shows the semiconductor structure following the next sequence of processing. A second inhibiting layer 330 1 is optionally formed on the first inhibiting layer 330 0, the insulation layer 320, and the metallization layer 340. The second inhibiting layer 330 1 includes a nitride compound. In one embodiment, the second inhibiting layer 330 1 includes a metal nitride compound. The nitride compound includes a substance with a molecular formula of SixNy. The variables x and y are indicative of the desired number of atoms. The second inhibiting layer 330 1 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD), or other deposition techniques.

FIG. 3F shows the semiconductor structure following the next sequence of processing. In one embodiment, the second inhibiting layer 330 1 is etched to define a chamber with an aperture that adjoins the metallization layer 340 and two sidewalls extending outwardly from the aperture. In one embodiment, the etching technique is selected from a group consisting of a spacer etching technique and an etch-back technique.

FIG. 3G shows the semiconductor structure following the next sequence of processing. A conductive layer 324 is formed on or adjoining to the inhibiting layer 330 0, the insulation layer 320 and the metallization layer 340. The conductive layer 324 includes a conductive material. In one embodiment, the conductive material includes an as-deposited film of a conductive compound. The conductive compound includes a first substance and a substantial amount of a second substance. The first substance includes ruthenium. The second substance includes oxygen. The conductive compound includes RuOx. The x is indicative of a desired number of atoms.

The conductive layer 324 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD), or other deposition techniques. In this embodiment, the conductive layer 324 forms the bottom conductive layer, or bottom electrode, or bottom plate of a semiconductor structure of interest, such as a capacitor.

In one embodiment, the conductive layer 324 is formed in about 210 degrees Celsius. In another embodiment, the first substance includes about 200 sccm of Ru-HEC. In another embodiment, the second substance includes about 250 sccm of O2. In another embodiment, the conductive layer 324 is formed in about 2.5 torrs.

After the formation of the conductive layer 324, in one embodiment, the conductive layer 324 undergoes an act of crystallizing to form a crystallized film. In one embodiment, the act of crystallizing occurs at a temperature that is greater than about 750 degrees Celsius and less than about 800 degrees Celsius. In another embodiment, the act of crystallizing occurs in an ambient of nitrogen. In another embodiment, the act of crystallizing results in compounds and substances that include ruthenium dioxide and a trace amount of ruthenium.

The conductive layer 324 may undergo a localizing or a polishing process such as by a chemical mechanical planarization technique or other suitable techniques. Such a localizing technique disposes the conductive layer 324 to adjoin the metallization layer 340. In another embodiment, the conductive layer 324 undergoes an etching process such as by a wet etch technique or a dry etch technique. The result is as shown in FIG. 3G.

FIG. 3H shows the semiconductor structure following the next sequence of processing. An insulator layer (or dielectric layer) 326 is formed on or adjoining the first inhibiting layer 330 0, the second inhibiting layer 330 1, and the conductive layer 324. The dielectric layer 326 includes an oxide compound. In one embodiment, the dielectric layer 326 is a thin film dielectric. In one embodiment, the oxide compound includes ditantalum pentaoxide. In another embodiment, the dielectric layer 326 includes a thin film of a high permittivity insulator material. In another embodiment, the dielectric layer 326 includes an amorphous insulator layer. The dielectric layer 326 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD), or other deposition techniques.

After the formation of the dielectric layer 326, in one embodiment, the dielectric layer 326 undergoes an act of crystallizing to form crystallized Ta2O5. The act of crystallizing to form crystallized Ta2O5 converts a trace amount of ruthenium that may remain from the formation of the conductive layer 324. Such conversion includes converting the trace amount of ruthenium into ruthenium dioxide. In one embodiment, the act of crystallizing occurs at a temperature of about 800 degrees Celsius. In another embodiment, the act of crystallizing occurs in an ambient of dinitrogen oxide. In another embodiment, the act of crystallizing occurs in an ambient of oxygen.

In one embodiment, the act of crystallizing forms a crystallized Ta2O5 with a desired lattice plane such that the permittivity of the crystallized Ta2O5 is greater than about 25. The desired lattice plane includes substantially a (001) lattice plane.

FIG. 31 shows the semiconductor structure following the next sequence of processing. A conductive layer 328 is formed on the dielectric layer 326. The conductive layer 328 includes a conductive material. The conductive layer 328 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD), or other deposition techniques. In this embodiment, the conductive layer 328 forms the top conductive layer, or top electrode, or top plate of a semiconductor structure of interest, such as a capacitor.

A third inhibiting layer 330 2 is optionally formed on the conductive layer 328. The third inhibiting layer 330 2 includes a nitride compound. In one embodiment, the third inhibiting layer 330 2 includes a metal nitride compound. The nitride compound includes a substance with a molecular formula of SixNy. The variables x and y are indicative of the desired number of atoms. The third inhibiting layer 330 2 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD), or other deposition techniques.

FIG. 3J shows the semiconductor structure following the next sequence of processing. The semiconductor structure 300 is patterned using photolithography with appropriately placed masks to define a number of capacitors to be used in memory cells. Then portions of the first inhibiting layer 330 0, the dielectric layer 326, the conductive layer 328, and the second inhibiting layer 330 2 are exposed and removed along with the masks. Those of the first inhibiting layer 330 0, the dielectric layer 326, the conductive layer 328, and the second inhibiting layer 330 2 may be removed by etching or other suitable removal techniques known in the art. Removal techniques are generally dependent on the material of construction of the layer to be removed as well as the surrounding layers to be retained. Patterning of the first inhibiting layer 330 0, the dielectric layer 326, the conductive layer 328, and the second inhibiting layer 330 2 defines two edges or terminals for each capacitor 336 0 and 336 1. These edges are the result of etching the various portions of the semiconductor structure 300 down to the insulation layer 320.

FIG. 3K shows the semiconductor structure following the next sequence of processing. A fourth inhibiting layer 330 3 is optionally formed on the insulator layer 320 and the capacitors 336 0 and 336 1. The fourth inhibiting layer 330 3 includes a nitride compound. In one embodiment, the fourth inhibiting layer 330 3 includes a metal nitride compound. The nitride compound includes a substance with a molecular formula of SixNy. The variables x and y are indicative of the desired number of atoms. The fourth inhibiting layer 330 3 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD), or other deposition techniques. Once the fourth inhibiting layer 330 3 is formed, a portion of the fourth inhibiting layer 330 3 is removed using a suitable technique, such as reactive ion etching. Such etching defines sidewall spacers as shown in FIG. 3J.

A digit line contact 341 is formed over the digit line contact regions 348. The formation of the digit line contact 341 and the completion of the semiconductor structure 300 do not limit the embodiments of the present invention and as such will not be discussed here in detail.

FIG. 4 is a block diagram of a device according to one embodiment of the present invention. The memory device 400 includes an array of memory cells 402, address decoder 404, row access circuitry 406, column access circuitry 408, control circuitry 410, and input/output circuit 412. The memory device 400 can be coupled to an external microprocessor 414, or memory controller for memory accessing. The memory device 400 receives control signals from the processor 414, such as WE*, RAS*, and CAS* signals. The memory device 400 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device 400 has been simplified to help focus on the embodiments of the invention. At least one of the memory cells includes a semiconductor structure in accordance with the aforementioned embodiments.

It will be understood that the above description of a DRAM (Dynamic Random Access Memory) is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a DRAM. Further, the embodiments of the invention is equally applicable to any size and type of memory circuit and is not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging memory technologies.

As recognized by those skilled in the art, memory devices of the type described herein are generally fabricated as an integrated circuit containing a variety of semiconductor devices. The integrated circuit is supported by a substrate. Integrated circuits are typically repeated multiple times on each substrate. The substrate is further processed to separate the integrated circuits into dies as is well known in the art.

FIG. 5 is an elevation view of a semiconductor wafer according to one embodiment of the present invention. In one embodiment, a semiconductor die 510 is produced from a wafer 500. A die is an individual pattern, typically rectangular, on a substrate that contains circuitry, or integrated circuit devices, to perform a specific function. At least one of the integrated circuit devices includes a memory cell that includes a semiconductor structure as discussed in the various embodiments heretofore in accordance with the embodiments of the invention. A semiconductor wafer will typically contain a repeated pattern of such dies containing the same functionality. Die 510 may contain circuitry for the inventive memory device, as discussed above. Die 510 may further contain additional circuitry to extend to such complex devices as a monolithic processor with multiple functionality. Die 510 is typically packaged in a protective casing (not shown) with leads extending therefrom (not shown) providing access to the circuitry of the die for unilateral or bilateral communication and control.

FIG. 6 is a block diagram of a circuit module according to one embodiment of the present invention. Two or more dies 610 may be combined, with or without protective casing, into a circuit module 600 to enhance or extend the functionality of an individual die 610. Circuit module 600 may be a combination of dies 610 representing a variety of functions, or a combination of dies 610 containing the same functionality. One or more dies 610 of circuit module 600 contain at least one semiconductor structure in accordance with the embodiments of the present invention.

Some examples of a circuit module include memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Circuit module 600 may be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others. Circuit module 600 will have a variety of leads 612 extending therefrom and coupled to the dies 610 providing unilateral or bilateral communication and control.

FIG. 7 is a block diagram of a memory module according to one embodiment of the present invention. Memory module 700 contains multiple memory devices 710 contained on support 715, the number depending upon the desired bus width and the desire for parity. Memory module 700 accepts a command signal from an external controller (not shown) on a command link 720 and provides for data input and data output on data links 730. The command link 720 and data links 730 are connected to leads 740 extending from the support 715. Leads 740 are shown for conceptual purposes and are not limited to the positions as shown. At least one of the memory devices 710 includes a memory cell that includes a semiconductor structure as discussed in various embodiments in accordance with the embodiments of the invention.

FIG. 8 is a block diagram of a system according to one embodiment of the present invention. Electronic system 800 contains one or more circuit modules 802. Electronic system 800 generally contains a user interface 804. User interface 804 provides a user of the electronic system 800 with some form of control or observation of the results of the electronic system 800. Some examples of user interface 804 include the keyboard, pointing device, monitor, or printer of a personal computer; the tuning dial, display, or speakers of a radio; the ignition switch, gauges, or gas pedal of an automobile; and the card reader, keypad, display, or currency dispenser of an automated teller machine. User interface 804 may further describe access ports provided to electronic system 800. Access ports are used to connect an electronic system to the more tangible user interface components previously exemplified. One or more of the circuit modules 802 may be a processor providing some form of manipulation, control, or direction of inputs from or outputs to user interface 804, or of other information either preprogrammed into, or otherwise provided to, electronic system 800. As will be apparent from the lists of examples previously given, electronic system 800 will often contain certain mechanical components (not shown) in addition to circuit modules 802 and user interface 804. It will be appreciated that the one or more circuit modules 802 in electronic system 800 can be replaced by a single integrated circuit. Furthermore, electronic system 800 may be a subcomponent of a larger electronic system. At least one of the circuit modules 802 includes a memory cell that includes a semiconductor structure as discussed in various embodiments in accordance with the embodiments of the invention.

FIG. 9 is a block diagram of a system according to one embodiment of the present invention. Memory system 900 contains one or more memory modules 902 and a memory controller 912. Each memory module 902 includes at least one memory device 910. Memory controller 912 provides and controls a bidirectional interface between memory system 900 and an external system bus 920. Memory system 900 accepts a command signal from the external bus 920 and relays it to the one or more memory modules 902 on a command link 930. Memory system 900 provides for data input and data output between the one or more memory modules 902 and external system bus 920 on data links 940. At least one of the memory devices 910 includes a memory cell that includes a semiconductor structure as discussed in various embodiments of the invention.

FIG. 10 is a block diagram of a system according to one embodiment of the present invention. Computer system 1000 contains a processor 1010 and a memory system 1002 housed in a computer unit 1005. Computer system 1000 is but one example of an electronic system containing another electronic system, e.g., memory system 1002, as a subcomponent. The memory system 1002 may include a memory cell that includes a semiconductor structure as discussed in various embodiments of the present invention. Computer system 1000 optionally contains user interface components. These user interface components include a keyboard 1020, a pointing device 1030, a monitor 1040, a printer 1050, and a bulk storage device 1060. It will be appreciated that other components are often associated with computer system 1000 such as modems, device driver cards, additional storage devices, etc. It will further be appreciated that the processor 1010 and memory system 1002 of computer system 1000 can be incorporated on a single integrated circuit. Such single-package processing units reduce the communication time between the processor and the memory circuit.

CONCLUSION

Systems, devices, structures, and methods have been described to address situations where, at high temperature, undesired diffusion acts against a high permittivity dielectric in a capacitor such that degradation occurs. Capacitors that are formed using at least one technique as described heretofore benefit from the dual ability of having an increase in storage capability yet maintain reliability in the process of manufacturing involving high temperatures.

The above-mentioned problems with capacitors as well as other problems are addressed by the embodiments described herein and will be understood by reading and studying the specification. Systems, devices, structures, and methods are described which accord these benefits.

An embodiment includes a capacitor. The capacitor includes a first electrode, a dielectric having a first compound, and a second electrode having a second compound that includes a third and a fourth substance. The first compound of the dielectric includes a first substance and a second substance. The first compound includes ditantalum pentaoxide. The second electrode also contains a trace amount of the third substance. The second compound in an as-deposited state includes a substantial amount of the fourth substance. The trace amount of the third substance is oxidized during the crystallization of the dielectric such that a diffusion of at least one of the first substance and the second substance is inhibited. The crystalline structure of the dielectric describes substantially a (001) lattice plane. The second compound includes RuOx. The x is indicative of a desired number of atoms.

An embodiment includes a method for enhancing a semiconductor structure that stores charges. The method includes forming a conductive layer of RuOx, crystallizing to form RuO2 and a trace amount of Ru, forming an amorphous insulator layer of Ta2O5, and forming a crystallized Ta2O5 with a desired lattice plane such that the permittivity of the crystallized Ta2O5 is greater than about 25.

Other aspects, advantages, and features of the embodiments set forth herein, in part will become apparent to those skilled in the art by reference to the description of the embodiments and referenced drawings or by practice of the embodiments of the invention. The aspects, advantages, and features of the embodiments the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

Although the specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the embodiments of the invention includes any other applications in which the above structures and fabrication methods are used. Accordingly, the scope of the embodiments of the invention should only be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5142438Nov 15, 1991Aug 25, 1992Micron Technology, Inc.Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact
US5177570Jul 31, 1991Jan 5, 1993Kabushiki Kaisha ToshibaMOS semiconductor device with high dielectric constant sidewall insulator and induced source/drain extension
US5358889Apr 29, 1993Oct 25, 1994Northern Telecom LimitedFormation of ruthenium oxide for integrated circuits
US5463483Mar 30, 1993Oct 31, 1995Semiconductor Energy Laboratory Co., Ltd.Electro-optical device having an anodic oxide film
US5622893Aug 1, 1994Apr 22, 1997Texas Instruments IncorporatedMethod of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes
US5702970Jun 26, 1996Dec 30, 1997Hyundai Electronics Industries Co., Ltd.Method for fabricating a capacitor of a semiconductor device
US5814539Jul 10, 1996Sep 29, 1998Seiko Epson CorporationMethod of manufacturing an active matrix panel
US5815427Apr 2, 1997Sep 29, 1998Micron Technology, Inc.Modular memory circuit and method for forming same
US5905278Jul 29, 1997May 18, 1999Fujitsu LimitedSemiconductor device having a dielectric film and a fabrication process thereof
US5910880Aug 20, 1997Jun 8, 1999Micron Technology, Inc.First tantalum-containg layer, second tantalum-nitrogen layer; dielectrics
US5969983Mar 1, 1999Oct 19, 1999Micron Technology, Inc.Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
US6066540Aug 28, 1998May 23, 2000Hyundai Electronics Industries Co., Ltd.Method for manufacturing a capacitor of a semiconductor device
US6235572Jun 17, 1999May 22, 2001Hitachi, Ltd.Method of making a memory cell having two layered tantalum oxide films
US6249040Nov 30, 1999Jun 19, 2001Fujitsu LimitedSemiconductor device having a high-dielectric capacitor
US6262450Apr 22, 1998Jul 17, 2001International Business Machines CorporationDRAM stack capacitor with vias and conductive connection extending from above conductive lines to the substrate
US6306699Apr 15, 1999Oct 23, 2001Mitsubishi Denki Kabushiki KaishaSemiconductor device having conducting material film formed in trench, manufacturing method thereof and method of forming resist pattern used therein
US6436786 *May 12, 2000Aug 20, 2002Matsushita Electronics CorporationMethod for fabricating a semiconductor device
US6545856Nov 30, 1999Apr 8, 2003Interuniversitair Microelectronica Centrum (Imec)Method of fabrication of a ferro-electric capacitor and method of growing a PZT layer on a substrate
US6627497Jun 5, 2002Sep 30, 2003Hitachi, Ltd.Semiconductor integrated circuit device and method of manufacturing the same
US6686274Sep 20, 1999Feb 3, 2004Renesas Technology CorporationSemiconductor device having cobalt silicide film in which diffusion of cobalt atoms is inhibited and its production process
US7009240Jun 21, 2000Mar 7, 2006Micron Technology, Inc.Structures and methods for enhancing capacitors in integrated circuits
US7232721 *Aug 31, 2004Jun 19, 2007Micron Technology, Inc.Structures and methods for enhancing capacitors in integrated circuits
US20050032299Aug 31, 2004Feb 10, 2005Micron Technology, Inc.Structures and methods for enhancing capacitors in integrated circuits
US20060131615Jan 31, 2006Jun 22, 2006Micron Technology, Inc.Structures and methods for enhancing capacitors in integrated circuits
Non-Patent Citations
Reference
1Aoyama, T. , et al., "Ultrathin Ta2O5 Film Capacitor with Ru Bottom Electrode", Journal of the Electrochemical Society, 145(8), (1998),2961-2364.
2Kishiro, K. , et al., "Structure and Electrical Properties of Thin Ta2O5 Deposited on Metal Electrodes", Jpn. J. Appl. Phys., 37, (1998),pp. 1336-1339.
3Lin, J. , et al., "Ta2O5 thin films with exceptionally high dielectric constant", Applied Physics Letters, (1999),2370-2372.
4Nakamura, S. , et al., "Embedded DRAM Technology compatible to the 0.13 micrometer high-speed Logics by using Ru pillars in cell capacitor and peripheral vias", IEDM, (1998),pp. 1029-1031.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7593286 *Mar 13, 2008Sep 22, 2009Micron Technology, Inc.Write latency tracking using a delay lock loop in a synchronous DRAM
US7881149Sep 1, 2009Feb 1, 2011Micron Technology, Inc.Write latency tracking using a delay lock loop in a synchronous DRAM
Classifications
U.S. Classification438/239, 438/240, 438/608, 257/E21.019, 257/E21.648, 438/253
International ClassificationH01L21/316, H01L21/02, H01L21/8242, H01L21/441
Cooperative ClassificationH01L28/65, H01L28/91, H01L21/31637, H01L27/10855, H01L27/10852
European ClassificationH01L27/108M4B2, H01L28/91, H01L28/65, H01L21/316B10
Legal Events
DateCodeEventDescription
Mar 13, 2014ASAssignment
Effective date: 20140101
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,
Free format text: CHANGE OF NAME;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:032439/0638
Jan 10, 2012ASAssignment
Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196
Owner name: ROYAL BANK OF CANADA, CANADA
Effective date: 20111223
Sep 21, 2011FPAYFee payment
Year of fee payment: 4
Oct 29, 2009ASAssignment
Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023438/0614
Effective date: 20090609