|Publication number||US7394117 B2|
|Application number||US 11/622,103|
|Publication date||Jul 1, 2008|
|Filing date||Jan 11, 2007|
|Priority date||Jun 27, 2003|
|Also published as||US7176067, US20040262687, US20070111439|
|Publication number||11622103, 622103, US 7394117 B2, US 7394117B2, US-B2-7394117, US7394117 B2, US7394117B2|
|Inventors||In-Soo Jung, Deok-Hyung Lee, Si-Young Choi, Byeong-Chan Lee, Yong-Hoon Son|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (3), Referenced by (6), Classifications (33), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. application Ser. No. 10/869,763; filed Jun. 16, 2004, now U.S. Pat. No. 7,176,067 which claims priority to Korean Patent Application No. 10-2003-0042736, filed on Jun. 27, 2003, the disclosures of which are hereby incorporated by reference herein in their entireties.
The present invention relates to semiconductor devices, and, more particularly, to field effect transistors and fabrication methods thereof.
Metal-oxide semiconductor field effect transistors (MOSFETs) may be scaled-down (i.e. reduced in size) in order to improve transistor properties and integration. For next-generation transistors, it may be essential to effectively suppress short channel effects in order to achieve channel lengths below 50 nm. In recent years, many approaches to reduce gate electrode length down to 20˜30 nm have been researched and studied. However, due to the short channel length between the source region and the drain region, efforts to suppress short channel effects have been rather unsuccessful thus far.
As such, it may be difficult to achieve stable performance with conventional (flat type) transistors as transistor size is decreased. Research has shown that double-gate field effect transistors may be good substitutes for conventional flat type transistors. Double-gate field effect transistors have gates positioned on both sides of a thin channel, so that the channel voltage may be more effectively controlled.
A fin field effect transistor (FinFET), which is a type of double-gate field effect transistor, is described by Huang et al. in “Sub 50-nm FinFET: PMOS”, 1999 IEEE International Electron Device Meeting Technical Digest.
As disclosed above, a FinFET may include a fin on a SOI (silicon on insulator) substrate that serves as a channel. A source and a drain may be formed on opposite ends of the fin, and a gate therebetween may separate the source and the drain. The FinFET may be used with and/or substituted for conventional flat type transistors.
Channel doping may be necessary for the application of FinFETs for use in dynamic memory (DRAM), which can require refreshing. Doping of the fin with impurities may result in increased threshold voltage but also may result in decreased subthreshold swing, which may improve transistor on/off characteristics. On the other hand, non-homogeneous doping of the fin may reduce subthreshold swing properties but may also reduce threshold voltage, which may reduce the ratio of on-current to off-current such that on/off performance of the memory device is also degraded. If channel doping is not performed at all, the threshold voltage may be reduced. With either alternative (i.e. where no channel doping or non-homogenous doping is used), threshold voltage variation and off-state leakage current may be increased. As such, FinFET performance may be degraded.
In various embodiments of the present invention, a method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and then removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a narrower width than the width of the active region. The method also includes forming a conductive layer on a top surface and on sidewalls of the fin.
According to further embodiments of the present invention, forming a conductive layer can include forming a conductive layer on a majority of the sidewalls of the fin and/or forming a conductive layer substantially covering the sidewalls of the fin.
In other embodiments of the present invention, removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer.
According to still further embodiments, forming an active region may include forming a trench in the substrate, forming an oxide layer on a bottom surface and on sidewalls of the trench, forming a nitride liner on a bottom surface and on sidewalls of the trench, and forming an isolation layer in the trench to define the active region adjacent the trench. The method may further include recessing the active region before forming the epitaxial layer.
In yet other embodiments according to the present invention, a fin field effect transistor includes an active region in a semiconductor substrate and a vertical fin on the active region. The fin is an epitaxial layer having a width narrower than a width of the active region. The transistor further includes a conductive layer on a top surface and sidewalls of the fin.
According to further embodiments of the present invention, the transistor may include a trench in the substrate adjacent the active region and an isolation layer in the trench. The isolation layer may fill the trench adjacent the active region. The transistor may further include an oxide layer on a bottom surface and on sidewalls of the trench and a nitride liner on a bottom surface and on sidewalls of the trench. The oxide layer and the nitride liner may be positioned between the isolation layer and the active region. The isolation layer may protrude above the surface of the substrate to a height about the same as the height of the fin.
Accordingly, various embodiments of the present invention provide a fin field effect transistor with a scaled-down fin that is narrower in width than that which may be achieved with known techniques. To account for short-channel effects from the decreased fin size, the fin is homogenously doped in situ such that threshold voltage is increased, off-state leakage current is reduced, and variations in threshold voltage are reduced.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. It will be understood that when an element such as a layer, region or substrate is referred to as “under” another element, it can be directly under the other element or intervening elements may also be present. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
Furthermore, relative terms such as beneath may be used herein to describe one layer or region's relationship to another layer or region as illustrated in the Figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, layers or regions described as “beneath” other layers or regions would now be oriented “above” these other layers or regions. The term “beneath” is intended to encompass both above and beneath in this situation. Like numbers refer to like elements throughout.
The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
Unless otherwise defined, all terms used in disclosing embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and are not necessarily limited to the specific definitions known at the time of the present invention being described. Accordingly, these terms can include equivalent terms that are created after such time. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.
Still referring to
The selectivity gas may be HCl or Cl2, and may ensure that the in situ doped silicon epitaxial layer 160 is formed on the recessed silicon substrate 100 but not on the isolation layer 140. The silicon source gas may be SiH2Cl2, Si2H6, and/or SiH4. The impurity gas may be chosen based on the desired device type. For example, if an N-channel device is desired, a phosphorous gas, such as PH3, may be used as the impurity gas in forming the in situ doped silicon epitaxial layer 160. Alternatively, if a P-channel device is desired, a boron gas, such as B2H6, may be used as the impurity gas in forming the in situ doped silicon epitaxial layer 160. The doping concentration of the impurity gas may be limited to a particular range, for example, from about 1.0 ×1017 to about 1.0×1019 ions/cm3.
As it may be doped in situ during growth, the epitaxial layer 160 may have a homogenous doping distribution. Therefore, variations in threshold voltage due to impurity nonhomogeneity may be prevented. In addition, degradation of transistor on-off characteristics caused by increases in subthreshold swing may also be reduced and/or eliminated.
However, the recessed isolation layer 140 a may be further recessed by the trimming process described below. As such, a reduced isolation layer 140 b (
As discussed above, the trimming process may involve oxidizing the surface of the in situ doped silicon epitaxial layer 160 and then removing the oxidized surface portion 160 b. As a result, a part of the isolation layer 140 a may also be removed along with the oxidized surface portion 160 b. Therefore, as part of the trimming process, a portion of the recessed isolation layer 140 a is removed to form a reduced isolation layer 140 b. The height of the reduced isolation layer 140 b may be approximately the same as that of the silicon substrate 100. The trimming process may also provide the in situ doped silicon epitaxial fin 160 a with a height of about 800 Å to about 900 Å, and a width of about 300 Å to about 500 Å. The width of the epitaxial fin 160 a is narrower than the width of the active region A of the substrate 100.
Thus, the trimming process of the present invention may provide a narrower fin than is possible with other known techniques, and may cure stacking faults as well. In other known techniques, the width of the in situ doped silicon epitaxial layer 160 may not be reduced beyond a certain size due to photolithography limitations. However, the trimming process according to embodiments of the present invention may form a scaled-down (e.g. 300˜500 Å wide) in situ doped silicon epitaxial fin 160 a, which may be beyond that which may be achieved by photolithography.
Although not shown in
Some embodiments according to the present invention may be applicable to dynamic random-access memory (DRAM), which may require a threshold voltage over 1 V, off-state leakage current below 1 fA/cell, and a reduced or eliminated subthreshold swing.
Fin field effect transistors and fabrication methods thereof according to some other embodiments of the present invention are explained in detail hereinafter.
Although not shown in
Many alterations and modifications may be made by those having ordinary skill in the art, given the benefit of present disclosure, without departing from the spirit and scope of the invention. Therefore, it must be understood that the illustrated embodiments have been set forth only for the purposes of example, and that it should not be taken as limiting the invention as defined by the following claims. The following claims are, therefore, to be read to include not only the combination of elements which are literally set forth but all equivalent elements for performing substantially the same function in substantially the same way to obtain substantially the same result. The claims are thus to be understood to include what is specifically illustrated and described above, what is conceptually equivalent, and also what incorporates the essential idea of the invention.
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|U.S. Classification||257/213, 257/E21.655, 438/157, 257/E27.091, 438/144, 257/E29.295, 257/E21.703, 257/327, 257/E27.112|
|International Classification||H01L21/8242, H01L29/34, H01L27/108, H01L21/336, H01L21/84, H01L29/786, H01L27/12|
|Cooperative Classification||H01L29/78603, H01L29/66818, H01L27/10876, H01L29/7851, H01L27/10826, H01L27/1203, H01L27/10823, H01L27/10879, H01L21/84|
|European Classification||H01L27/108M4C2, H01L29/66M6T6F16F4, H01L27/108M4C4, H01L27/108F7, H01L27/108F6, H01L27/12B, H01L21/84, H01L29/78S2|
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