|Publication number||US7395199 B2|
|Application number||US 11/198,096|
|Publication date||Jul 1, 2008|
|Filing date||Aug 5, 2005|
|Priority date||Jul 17, 2000|
|Also published as||DE60136461D1, EP1303807A2, EP1303807B1, EP1303807B8, US7069205, US20050273313, WO2002006947A2, WO2002006947A3|
|Publication number||11198096, 198096, US 7395199 B2, US 7395199B2, US-B2-7395199, US7395199 B2, US7395199B2|
|Inventors||Tim Carroll, Aaron Giles|
|Original Assignee||Microsoft Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (46), Non-Patent Citations (11), Referenced by (2), Classifications (13), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. application Ser. No. 09/617,624 now U.S. Pat. No. 7,069,205, filed Jul. 17, 2000 issued Jun. 27, 2006, which is hereby incorporated by reference in its entirety.
The present invention relates in general to the field of computer system emulation and, more particularly, to a method for emulating the operation of a video graphics adapter.
Computers include general purpose central processing units (CPUs) that are designed to execute a specific set of system instructions. A group of processors that have similar architecture or design specifications may be considered to be members of the same processor family. Examples of current processor families include the Motorola 680X0 processor family, manufactured by Motorola, Inc. of Phoenix, Ariz.; the Intel 80X86 processor family, manufactured by Intel Corporation of Sunnyvale, Calif.; and the PowerPC processor family, which is manufactured by Motorola, Inc. and used in computers manufactured by Apple Computer, Inc. of Cupertino, Calif. Although a group of processors may be in the same family because of their similar architecture and design considerations, processors may vary widely within a family according to their clock speed and other performance parameters.
Each family of microprocessors executes instructions that are unique to the processor family. The collective set of instructions that a processor or family of processors can execute is known as the processor's instruction set. As an example, the instruction set used by the Intel 80X86 processor family is incompatible with the instruction set used by the PowerPC processor family. The Intel 80X86 instruction set is based on the Complex Instruction Set Computer (CISC) format. The Motorola PowerPC instruction set is based on the Reduced Instruction Set Computer (RISC) format. CISC processors use a large number of instructions, some of which can perform rather complicated functions, but which require generally many clock cycles to execute. RISC processors use a smaller number of available instructions to perform a simpler set of functions that are executed at a much higher rate.
The uniqueness of the processor family among computer systems also typically results in incompatibility among the other elements of hardware architecture of the computer systems. A computer system manufactured with a processor from the Intel 80X86 processor family will have a hardware architecture that is different from the hardware architecture of a computer system manufactured with a processor from the PowerPC processor family. Because of the uniqueness of the processor instruction set and a computer system's hardware architecture, application software programs are typically written to run on a particular computer system running a particular operating system.
A computer manufacturer will want to maximize its market share by having more rather than fewer applications run on the microprocessor family associated with the computer manufacturer's product line. To expand the number of operating systems and application programs that can run on a computer system, a field of technology has developed in which a given computer having one type of CPU, called a host, will include an emulator program that allows the host computer to emulate the instructions of an unrelated type of CPU, called a guest. Thus, the host computer will execute an application that will cause one or more host instructions to be called in response to a given guest instruction. Thus, the host computer can both run software design for its own hardware architecture and software written for computers having an unrelated hardware architecture. As a more specific example, a computer system manufactured by Apple Computer, for example, may run operating systems and program written for PC-based computer systems. It may also be possible to use an emulator program to operate concurrently on a single CPU multiple incompatible operating systems. In this arrangement, although each operating system is incompatible with the other, an emulator program can host one of the two operating systems, allowing the otherwise incompatible operating systems to run concurrently on the same computer system.
When a guest computer system is emulated on a host computer system, the guest computer system is said to be a virtual machine, as the host computer system exists only as a software representation of the operation of the hardware architecture of the guest computer system. The terms emulator and virtual machine are sometimes used interchangeably to denote the ability to mimic or emulate the hardware architecture of an entire computer system. As an example, the Virtual PC software created by Connectix Corporation of San Mateo, Calif. emulates an entire computer that includes an Intel 80X86 Pentium processor and various motherboard components and cards. The operation of these components is emulated in the virtual machine that is being run on the host machine. An emulator program executing on the operating system software and hardware architecture of the host computer, such as a computer system having a PowerPC processor, mimics the operation of the entire guest computer system. The emulator program acts as the interchange between the hardware architecture of the host machine and the instructions transmitted by the software running within the emulated environment.
The video graphics adapter (VGA) architecture of the 80X86 computer system architecture family has evolved over the history of the PC. The VGA system provides four-bit color up to 640×480 pixel resolution or 8-bit color up to 320×200 pixel resolution. The VGA architecture is an extension of earlier standards, such as monochrome display adapter (MDA) for simple black-and-white text, color graphics adapter (CGA) for simple 2-bit color and colored text modes, and enhanced graphics adapter (EGA) for four-bit color up to 320×200 resolution. The VGA architecture, which was complex at the time of its introduction, has only grown more complex with the more recent extensions to the standard. Much of the complexity of the VGA architecture stems from the implementation of backwards compatibility with the earlier standards. The layered extensions to the original VGA standard have resulted in the very complex operation of VGA graphics in modern PC systems. As a result, even the simplest of instructions to the VGA hardware can result in a complex set of operations in the VGA hardware. The complexity of the VGA hardware architecture is also affected by the number of VGA modes and the ability to modify the operation of the VGA hardware by changing register settings in the VGA hardware. The VGA modes include a number of read modes, write modes, ALU operation modes, and adjustable plane and pixel masks. Each of these operational modes may affect a single load or store to or from video RAM.
Attempting to account for the complexity of the VGA hardware architecture, including all of the permutations that can be introduced by the VGA operating modes and hardware register settings, makes instruction translation from the PC environment to another computer environment, such as the PowerPC environment, a difficult and time-consuming task. As an example, checking all of the VGA settings slows the emulator program. Thus, translating each instruction on the basis of the full potential of the VGA architecture results in slow emulation.
VGA hardware emulation must also differentiate regular instructions from those instructions directed to VGA hardware. The only difference between guest instructions directed to VGA hardware and regular load and store instruction is that the former instructions are mapped to memory associated with the VGA hardware while the latter instructions are mapped to main memory. Generally, an emulator translates guest instructions into a load or store instruction in the host environment. Because these instructions are regular host load and store instructions, the emulator requires a mechanism to detect when the instructions are directed to the emulated VGA hardware. Therefore, the emulator ensures that the guest virtual memory pages associated with VGA hardware instructions are not mapped to the host physical memory. As a result, those instructions directed to VGA hardware will normally cause a page fault error. Because the page fault handler can detect that VGA memory is involved, a function may be called to perform the task associated with the instruction.
However, incurring a page fault on every pixel write operation consumes a considerable amount of system resources because a typical VGA display resolution will have several thousand pixels. For example, a display resolution of 320×200 consists of 64,000 pixels. Therefore, it is desirable to minimize the occurrence of page faults. In order to minimize the number of page faults, it is preferable to patch the cached translated code associated with the guest instruction so that the page fault only occurs once. Essentially, when a page fault is detected, the store or load instruction that caused the page fault is replaced with a branch instruction to a function which handles all of the VGA modes but is executed under the emulator. Note that the emulator is not required to backpatch the translated code to properly emulate VGA operation. The emulator could handle all instructions directed to the VGA hardware entirely through the page fault mechanism, but thus would incur a serious performance penalty.
However, different VGA modes require a different number of instructions to perform a given action. Because there are several disadvantages associated with generating code inline, an emulator may replace the guest load or store instruction with a branch to a general purpose VGA function. This general purpose function is capable of handling all the various graphical operations. However, every time a pixel was written, this general purpose function had to test many or all of the various attributes to determine which code to execute. Commonly, the general purpose function performed all of the various graphical operations to the pixel, even if some of those stages or operations would have no effect on the final result. For example, a pixel masking operation that returned the entire pixel would be performed, even though this operation could be ignored. As a result, the performance of the emulator is adversely affected by having to perform these unnecessary operations.
In accordance with the present invention, a method is provided for emulating the operation of VGA hardware in an emulated operating environment in a computer system that substantially eliminates or reduces the disadvantages associated with previous emulators. Rather than attempting to emulate the full functionality of the VGA hardware for each VGA hardware instruction received by the emulator program, the emulator program of the present invention instead maintains a table that permits the emulator program to branch to a function customized for both the instruction and the operating mode of the VGA hardware. If an instruction is executed at a time when the VGA operating mode has changed, the addresses of the customized function are loaded from a second table. If a customized function is not present, a customized function is generated and the tables are updated to point to the addresses of the newly created customized routine. As the VGA hardware is switching among operating modes, a customized function is not generated until such time when an actual instruction is executed for the VGA hardware.
One advantage of the present invention is that the branching process is streamlined in that when the function has already been generated, the emulator will automatically dispatch directly into the customized function without needing to first test for whether the function already exists. Another advantage of the present invention is that because a function is not generated until it is needed, the emulating process avoids any unnecessary operations.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
A more complete understanding of the present invention and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:
The present invention provides an emulation technique for the VGA hardware architecture that involves the creation of custom code for the VGA operational settings encountered by the emulator. The invention involves the use of a table that directs the emulated program to a customized function which handles the specific VGA settings that are present when the emulated instruction is executed. As the mode of the VGA hardware changes, this table of address pointers is updated to reflect the addresses of a new set of routines customized to the new mode of the VGA hardware. In some instances, a customized function will not yet have been prepared by the emulator for the operating mode of the VGA hardware. In this instance, a special address that will cause a function generator to be executed will instead be installed in the table.
Software application 20 in turn runs on guest operating system 18. In the emulated operating environment of
During the operation of software application 20, the guest operating system 18 issues instructions directed to the emulated or guest VGA hardware, part of guest hardware architecture 16. These instructions may be load or store commands. A load command requests that information be read from memory, and a store command requests that information be written to memory. The VGA instructions are actually regular load or store instructions in the guest instruction set. But because the VGA instructions occupy a different block of addresses than other instructions, VGA instructions are generally mapped to the memory devices associated with the VGA hardware rather than the main memory. Although the VGA instructions do not in themselves change, the way in which these instructions are interpreted does change, according to the particular VGA global mode. Thus, emulator 14 must take into account the particular global VGA mode in order to properly translate a specific guest instruction. The mode refers to the particular configuration of registers for the emulated VGA hardware. There are numerous global VGA modes because the global VGA mode is determined by the combination of the particular VGA submode and other operational settings. As discussed above, examples of submodes include graphics mode, text mode, and arithmetic logic unit (ALU) mode, among other examples. Examples of other operational settings that determine the global VGA mode include pixel masking and planar setting, among other examples.
As discussed above, emulating VGA hardware is difficult due to the complexity of VGA architecture and the large number of modes and configurations. Because several operations will generally be performed in a single graphics mode before changing to another mode, it is desirable to generate a set of instructions for a custom VGA mode only once and avoid regenerating this code multiple times or performing unnecessary tests through a general purpose VGA function. Therefore, it is preferable to store the function, or set of translated code, corresponding to the guest instruction so that the stored function may be used instead of generating the function again in response to a repeated instruction. For example, if the guest instruction is repeated several thousand times in a row, it is desirable to generate a customized function once, on the first load or store instruction executed, rather than calling through a general purpose function or regenerating code for each instruction executed. The function is preferably stored in a VGA cache in the main memory. The VGA cache is typically not a hardware cache, but rather a location in the main memory.
Jump table 42 is stored in memory and allows emulator 14 to utilize specialized functions instead of general purpose functions. Therefore, each jump table 42 is specific to a particular VGA mode. For example, the jump table 42 for VGA mode 0 will be different from the jump table 42 that is generated for VGA mode 1. Each entry 46 in jump table 42 contains a function pointer for each permissible operation that can be performed on VGA memory. Thus, jump table 42 may contain a section for function pointers for store instructions 48 a and a section for function pointers for load instructions 48 b. For example, entry 46 a contains the memory address for the function corresponding to a 1 byte store instruction, while entry 46 f contains the memory address for the function corresponding to a 4 byte load instruction. As a result, jump table 42 is operable to point to the VGA cache address of the function that corresponds to the guest instruction for the particular VGA mode for which jump table 42 was generated. Thus, if a load or store instruction is patched to point into jump table 42, then that load or store instruction will indirectly point to a function which implements the current VGA mode settings. If the VGA mode changes, the patched code need not be modified further.
After the emulator checks the new flags against the flag settings 44 associated with the current VGA mode that are contained in jump table 42, the emulator must then determine whether the two flags are different at step 28. If the flags are not different, then the new VGA mode is equivalent to the current VGA mode for which jump table 42 was generated. In other words, the change in register settings at step 22 was a minor change or operation and does not require any potentially new code. As a result, the function pointers 46 in jump table 42 may be used because the underlying functions are operable to execute the guest operating instructions for the new VGA mode. Thus, at step 30, the emulator is ready for the next guest instruction.
If the new flags do not match the current flag 44, then this dissimilarity indicates that the two VGA modes are substantially different. Because the change in register settings at step 22 was a major change involving a different VGA mode, a potentially different set of functions will be needed to handle the guest instructions under this new VGA mode. Thus, the emulator must then attempt to locate the appropriate set of functions for this new VGA mode.
Generally, mode table 50, shown in
At step 32, the emulator searches mode table 50 to find the mode flag entry 58 that matches the new mode flags in order to determine whether mode table 50 contains the function pointers 60 for functions which are operable to the new VGA mode. Mode table 50 is searched twice, once for load instructions and once for store instructions. At step 34, the emulator decides whether it has found a match between the flag for the new VGA mode and any of the mode flags 58. If so, then the entry 56 and corresponding function pointers 60 for the matching mode flag 58 are operable for the new VGA mode. Thus, at step 36, the emulator copies all of the function pointers 60 from matching entry 56 to jump table 42. The emulator copies the appropriate function pointers 60 from both the write section 52 and the read section 54. All six entries 46, and the underlying pointer addresses, in jump table 42 have now been changed from those associated with the current VGA mode to those associated with the new VGA mode. Thus, when the guest operating system issues an instruction under the new VGA mode, emulator 14 may use the repopulated jump table 42 to patch to the correct function.
If the emulator searches mode table 50 and does not find a mode flag entry 58 which matches the flags for the new VGA mode, then this indicates that the mode has not been used before and new functions must be generated to deal with guest operating instructions under the new VGA mode. Accordingly, at step 38, emulator 14 sets all entries 46 in jump table 42 to point to the function generator of emulator 14. The function generator is an emulator functionality that is operable to generate a set of translated code which allows the host to execute guest instructions. Regardless of whether a match was found in mode table 50, the current flag setting 44 of jump table 42 must be changed to the flags for the new VGA mode at step 40. Once jump table 42 has been updated with the appropriate pointer addresses, then emulator 14 is ready for the next guest operating instruction at step 30.
Once emulator 14 has accounted for the new VGA mode, guest operating system 18 may issue an instruction that will require a corresponding function to allow the host operating system to execute the guest instruction. For example, at step 62, shown in
If jump table 42 points to the function generator, then the function generator creates a customized function based on the current flag setting 44 contained in jump table 42 at step 70. After the customized function has been created, it is stored in the VGA cache at step 72 and is allocated a memory address. Once the customized function has an associated address in VGA cache, jump table 42 and mode table 50 may be updated.
For the purposes of efficiency, the function generator will typically only generate that function necessary to execute the guest instruction. It is unnecessary to commit resources to generate a function unless the corresponding instruction has actually been issued. For example, if the guest instruction was a 1 byte store instruction, then only that function necessary to execute this instruction will be created. Thus, only entry 46 a of jump table 42 will be updated. The other entries in jump table 42 will point to the address for the function generator. Similarly, mode table 50 will only be updated to contain an address in entry 60 a in store section 52. The other entries for 60 b and 60 c will either be left blank or point to the function generator. An entry 56 for a new mode will preferably only be added to mode table 50 when the first function for that new mode is actually generated. This avoids populating mode table 50 with mode entries 56 that will never actually have generated code associated with them. Searching these empty entries would incur a needless performance penalty in the event of a mode change. Next, at step 76, jump table 42 points to the host executable customized function that now corresponds to the guest instruction under the current mode. The function is then executed under the host environment at step 78. The emulator 14 is now ready for the next guest instruction.
In order to conserve system resources, it may be desirable to defer the process of searching mode table 50 and repopulating jump table 42, as illustrated at steps 32 through 38 of
Rather than attempting to emulate the full functionality of the VGA hardware for each VGA hardware instruction received by the emulator program, the emulator program of the present invention instead maintains a set of tables that permits the emulator program to branch to a routine customized for both the instruction and the operating mode of the VGA hardware. The branching process is streamlined in that when the function has already been generated, the emulator will automatically dispatch directly into the customized function without needing to first test for whether the function already exists. Thus, large pixel operations do not incur any unnecessary overhead. If an instruction is executed at a time when the VGA operating mode has changed, the addresses of the customized routines are loaded from a second table. If a customized routine is not present, a customized routine is generated and the tables are updated to point to the addresses of the newly created customized routine. As the VGA hardware is switching among operating modes, a customized routine is not generated until such time an actual instruction is executed for the VGA hardware.
Although the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4779188||Oct 19, 1987||Oct 18, 1988||International Business Machines Corporation||Selective guest system purge control|
|US4875186||Feb 28, 1986||Oct 17, 1989||Prime Computer, Inc.||Peripheral emulation apparatus|
|US4903218||Aug 13, 1987||Feb 20, 1990||Digital Equipment Corporation||Console emulation for a graphics workstation|
|US4958378||Apr 26, 1989||Sep 18, 1990||Sun Microsystems, Inc.||Method and apparatus for detecting changes in raster data|
|US4979738||Dec 6, 1983||Dec 25, 1990||Midway Manufacturing Corporation||Constant spatial data mass RAM video display system|
|US5063499||Jan 9, 1989||Nov 5, 1991||Connectix, Inc.||Method for a correlating virtual memory systems by redirecting access for used stock instead of supervisor stock during normal supervisor mode processing|
|US5269021||Oct 12, 1989||Dec 7, 1993||Texas Instruments Incorporated||Multiprocessor software interface for a graphics processor subsystem employing partially linked dynamic load modules which are downloaded and fully linked at run time|
|US5278973||Jun 27, 1991||Jan 11, 1994||Unisys Corporation||Dual operating system computer|
|US5301277||Dec 23, 1991||Apr 5, 1994||Seiko Epson Corporation||Method and apparatus for communicating peripheral data to/from minor operating systems running as subprocesses on a main operating system|
|US5367628||Oct 15, 1992||Nov 22, 1994||Hitachi, Ltd.||Multi-window system and display method for controlling execution of an application for a window system and an application for a non-window system|
|US5406644||Nov 23, 1988||Apr 11, 1995||Insignia Solutions, Inc.||Apparatus and method for emulating a computer instruction set using a jump table in the host computer|
|US5448264||Jun 14, 1993||Sep 5, 1995||Hewlett-Packard Company||Method and apparatus for separate window clipping and display mode planes in a graphics frame buffer|
|US5452456||Dec 18, 1992||Sep 19, 1995||Apple Computer, Inc.||Apparatus for executing a plurality of program segments having different object code types in a single program or processor environment|
|US5502809||Sep 6, 1994||Mar 26, 1996||Nec Corporation||Image storage of a changeable display|
|US5581766||Oct 27, 1994||Dec 3, 1996||Compaq Computer Corporation||Selectable video driver system|
|US5617552||Feb 29, 1996||Apr 1, 1997||Connectix Corporation||Lossless data compression system and method|
|US5640562||Feb 27, 1995||Jun 17, 1997||Sun Microsystems, Inc.||Layering hardware support code on top of an existing operating system|
|US5666521||Nov 20, 1996||Sep 9, 1997||Intel Corporation||Method and apparatus for performing bit block transfers in a computer system|
|US5675382||Apr 8, 1996||Oct 7, 1997||Connectix Corporation||Spatial compression and decompression for video|
|US5699539||May 7, 1996||Dec 16, 1997||Connectix Corporation||Virtual memory management system and method using data compression|
|US5742797||Aug 11, 1995||Apr 21, 1998||International Business Machines Corporation||Dynamic off-screen display memory manager|
|US5752275||Jul 14, 1997||May 12, 1998||Intel Corporation||Translation look-aside buffer including a single page size translation unit|
|US5757386||Aug 11, 1995||May 26, 1998||International Business Machines Corporation||Method and apparatus for virtualizing off-screen memory of a graphics engine|
|US5768593||Mar 22, 1996||Jun 16, 1998||Connectix Corporation||Dynamic cross-compilation system and method|
|US5790825||Aug 5, 1997||Aug 4, 1998||Apple Computer, Inc.||Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions|
|US5801717||Apr 25, 1996||Sep 1, 1998||Microsoft Corporation||Method and system in display device interface for managing surface memory|
|US5815686||Sep 12, 1996||Sep 29, 1998||Silicon Graphics, Inc.||Method and apparatus for address space translation using a TLB|
|US5831607||Jan 25, 1996||Nov 3, 1998||International Business Machines Corporation||Method for adapting multiple screens of information for access and use on a single graphical panel in a computer system|
|US5860147||Sep 16, 1996||Jan 12, 1999||Intel Corporation||Method and apparatus for replacement of entries in a translation look-aside buffer|
|US5940872||Nov 1, 1996||Aug 17, 1999||Intel Corporation||Software and hardware-managed translation lookaside buffer|
|US5964843||Apr 25, 1996||Oct 12, 1999||Microsoft Corporation||System for enhancing device drivers|
|US6008847||Mar 3, 1997||Dec 28, 1999||Connectix Corporation||Temporal compression and decompression for video|
|US6014170||Jun 20, 1997||Jan 11, 2000||Nikon Corporation||Information processing apparatus and method|
|US6026476||Aug 6, 1997||Feb 15, 2000||Intel Corporation||Fast fully associative translation lookaside buffer|
|US6044408||Apr 25, 1996||Mar 28, 2000||Microsoft Corporation||Multimedia device interface for retrieving and exploiting software and hardware capabilities|
|US6067618||Mar 26, 1998||May 23, 2000||Innova Patent Trust||Multiple operating system and disparate user mass storage resource separation for a computer system|
|US6115054||Dec 29, 1998||Sep 5, 2000||Connectix Corporation||Graphics processor emulation system and method with adaptive frame skipping to maintain synchronization between emulation time and real time|
|US6332184||Aug 18, 1999||Dec 18, 2001||Ati International, Srl||Method and apparatus for modifying memory accesses utilizing TLB entries|
|US6452599||Nov 30, 1999||Sep 17, 2002||Ati International Srl||Method and apparatus for generating a specific computer hardware component exception handler|
|US6542938||Jun 16, 1998||Apr 1, 2003||Seiko Epson Corporation||Mechanism and apparatus for adaptive quality performance control in 3D based PC applications|
|US6633905||Sep 22, 1999||Oct 14, 2003||Avocent Huntsville Corporation||System and method for accessing and operating personal computers remotely|
|US6884171||Sep 18, 2001||Apr 26, 2005||Nintendo Co., Ltd.||Video game distribution network|
|US7069205 *||Jul 17, 2000||Jun 27, 2006||Microsoft Corporation||System and method for emulating the operation of a video graphics adapter|
|EP0524773A1||Jul 16, 1992||Jan 27, 1993||International Business Machines Corporation||Multiple command set support for rendering components|
|EP0645701A2||Sep 26, 1994||Mar 29, 1995||Bull HN Information Systems Inc.||Emulating the memory functions of a first system on a second system|
|WO1998057262A1||Jun 12, 1998||Dec 17, 1998||Telefonaktiebolaget Lm Ericsson (Publ)||Simulation of computer processor|
|1||"Intel386 DX Microprocessor," Intel, 1995, 32-58.|
|2||"Processor instruction sets," The PC Guide, version dated Dec. 18, 2000, http://www.pcguide.com/ref/cpu/arch/int/instc.html.|
|3||Abrash, M., "Demystifying 16-bit VGA," Doctor Dobbs J., 1990, 70-81.|
|4||Chalk, A.J., "Ega and Vga smooth scrolling and panning," Doctor Dobbs J., 1988, 1-25.|
|5||M68040 User's Manual, Motorola, Inc., 1990, revised 1992, 1993, Chapter 3.|
|6||M68060 user's Manual, Motorola, 1994, Section 4, pp. i-xviii; Memory Management Unit, pp. 401-4-30, http://e-www.motorola.com/brdata/PDFDB/MICROPROCESSORS/32<SUB>-</SUB>BIT/68K-COLDFIRE/M680X0/MC68060.pdf.|
|7||MacIntosh & Technology: changing chips in the middle of the stream, or Apple takes a risc, URL:www.btech.co/changingchips.mtml, paragraphs 00061-00071, retrieved Dec. 10, 2001.|
|8||MP750, RISC Microprocessor User's Manual, Motorola, 1997, Contents, pp. iii-xvi; Chapter 5; Memory Management, pp. 5-1-5-34; Glossary, pp. Glosary-1-Glossary-13, http://e-www.motorola.com/brdata/PDFDB/MICROPROCESSORS/32<SUB>-</SUB>BIT/POWERPC/MPC7XX/MPC750UM.pdf.|
|9||Osisek, D.L., et al., "ESA/390 interpretive-executive architecture, foundation for VM/ESA," IBM Systems J., 1991, 30(1), 34-51.|
|10||Traut, E., "Building the virtual PC," Byte, McGraw-Hill, Inc., 1997, 22(11), 51-52.|
|11||Tsai, S.R., et al., "On the architectural support for logical machine systems," Microprocessing and Microprogramming, 1988, 22(2), 81-96.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8271258 *||Mar 30, 2007||Sep 18, 2012||International Business Machines Corporation||Emulated Z-series queued direct I/O|
|US20080243467 *||Mar 30, 2007||Oct 2, 2008||International Business Machines Corporation||Emulated z-series queued direct i/o|
|U.S. Classification||703/23, 703/24, 712/E09.037, 345/522|
|International Classification||G06F9/318, G09G5/36, G06F9/455|
|Cooperative Classification||G06F9/30189, G06F9/30174, G09G5/363, G06F9/45541|
|European Classification||G06F9/30U, G06F9/30U2|
|Sep 21, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Dec 9, 2014||AS||Assignment|
Owner name: MICROSOFT TECHNOLOGY LICENSING, LLC, WASHINGTON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICROSOFT CORPORATION;REEL/FRAME:034543/0001
Effective date: 20141014
|Dec 16, 2015||FPAY||Fee payment|
Year of fee payment: 8