|Publication number||US7397717 B2|
|Application number||US 11/137,503|
|Publication date||Jul 8, 2008|
|Filing date||May 26, 2005|
|Priority date||May 26, 2005|
|Also published as||CN1869963A, CN100418079C, US20060268642|
|Publication number||11137503, 137503, US 7397717 B2, US 7397717B2, US-B2-7397717, US7397717 B2, US7397717B2|
|Inventors||Han-Sung Chen, Chia-Yen Yeh, Chen-Hao Po, Ching-Chung Lin|
|Original Assignee||Macronix International Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (25), Classifications (15), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The invention relates to nonvolatile memory devices that utilize a serial peripheral interface (SPI) for the serial transmission of data.
A serial peripheral interface (SPI) has been utilized in the past for enabling the serial exchange of data between two devices, one referred to as the master and the other referred to as the slave. Serially exchanging data involves transmitting data between the master and slave devices one bit at a time, and is often used in computer systems for transmitting data between the central processing unit (CPU) and various peripheral devices. In such a case, the CPU acts as the master device and the peripherals are the slave devices. The bit-by-bit transmission of data is limited by the speed of the serial clock rate of the master device, so that if the serial clock rate is low, large amounts of data will be transmitted very slowly.
Another means of transmitting data is through a parallel interface. Exchanging data in parallel involves transmitting a plurality of bits over a plurality of transmission paths simultaneously. Parallel transmission has the advantage of allowing more bits to be transmitted over a given time, and thus a faster transmission rate. However, parallel transmission between devices suffers from the drawbacks of often having complicated connection schemes, and often needing short transmission paths to minimize crosstalk between transmission paths.
Nonvolatile memory devices, including flash memory devices, have traditionally transmitted data using a parallel interface. Recently, however, the serial peripheral interface has been implemented in flash memory designs. Flash memory devices using the serial peripheral interface are less complex, and can be made on a much smaller scale, needing only an input terminal, an output terminal, a clock input terminal, a chip select terminal, and an applied voltage to be able to program and read data.
In accordance with the invention, there is provided a method of operating a serial peripheral interface flash memory device, comprising applying a parallel mode command to a first pin operatively coupled to an input/output interface of the memory device to cause the device to operate in a parallel data transmission mode; applying a chip select signal to a second pin of the memory device to enable operation in response to the parallel mode command; applying a serial clock signal to a third pin of the memory device; applying one of a read command and a write command to the first pin; and transmitting data in parallel on a fourth pin and additional pins, operatively coupled to the input/output interface, at a frequency corresponding to the serial clock signal, wherein data is transmitted only on the fourth pin and at the frequency when the device operates in a serial mode.
Also in accordance with the invention, there is provided a semiconductor memory device comprising an input/output interface; a serial data transmission input terminal, operably coupled to the input/output interface, for receiving a parallel mode command; a clock signal input terminal for receiving a serial clock signal; a serial data transmission terminal, operably coupled to the input/output interface, for serving as a sole data transmission pin in a serial mode for serially transmitting data at a frequency determined by the serial clock signal; a chip select input terminal for receiving a chip select signal to enable operation in response to the parallel mode command; a plurality of dummy input/output terminals, operably connected in parallel to the input/output interface, for transmitting data in the parallel mode in parallel with data being transmitted on the serial data terminal at the frequency determined by the serial clock signal.
Further in accordance with the invention, there is provided a serial peripheral interface flash memory integrated circuit device comprising a serial data transmission input terminal, for receiving a data or command input; a clock signal input terminal for receiving a serial clock signal; a serial data transmission terminal, for serving as a sole data transmission pin in a serial mode for serially transmitting data at a frequency determined by the serial clock signal; a chip select input terminal for receiving a chip select signal; at least one voltage input terminal for receiving an applied voltage; a ground terminal for grounding the device; and a plurality of dummy input/output terminals for transmitting data in a parallel mode in parallel with data being transmitted on the serial data terminal at the frequency determined by the serial clock signal.
Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to present embodiments of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
In accordance with embodiments consistent with the present invention, there is provided a serial peripheral interface flash memory device that includes an accelerated parallel mode that enables higher performance on lower clock frequency systems.
Data is input into, and output from, an input/output shift register 504 that is operably connected to a data buffer 506, used for the temporary storage of data being read from or written to a memory array 508. A write address corresponding to a physical location in memory array 508, may be supplied through an address register 510. The position of the write address in memory array 508 is decoded by an X-decoder 512 and a Y-decoder 514. A status register 516 supplies an indication of the current status of serial peripheral interface flash memory device 400.
Commands input through serial input terminal 416 may include an operation command which is transferred from shift register 504 to control logic 502. Upon receipt, control logic 502 interprets the command to determine if a read, erase, or write operation should be performed. Additionally, the received command may indicate whether a read or write operation will be performed in serial mode or parallel mode.
If control logic 502 determines that the operation requires a high voltage, e.g., for a write operation, a signal will be sent to a high voltage generator 518 to facilitate the high voltage operation. In performing the write operation in serial mode, data is input through serial input terminal 416 into input/output shift register 504 and loaded into data buffer 506 for temporary storage prior to writing to memory array 508. The write address of the data is supplied through address register 510. The supplied write address corresponds to a physical location in memory array 508. The physical location of the write address in memory array 508 is decoded by X-decoder 512 and Y-decoder 514. The data is then written to the corresponding write address in memory array 508. In serial mode, the data is input through serial input terminal 416 at a rate of one bit per cycle of serial clock signal SCLK.
If the write operation is performed in parallel mode, the data is input through parallel input/output terminals PO0-PO7, consisting of dummy input/output terminals 418 and serial output terminal 412, at a rate of eight bits (one byte) per cycle of serial clock signal SCLK.
If the operation is a data read operation, which does not require a high voltage, X-decoder 512 and Y-decoder 514 determine the location of the data to be read from memory array 508. In performing the read operation, the data read from memory array 508 is output to data buffer 506. The data is then transferred from data buffer 506 to input/output shift register 504. In serial mode, data is output from shift register 504 through serial output terminal 412 at a frequency of one bit per cycle of serial clock signal SCLK. If, however, device 400 is operating in parallel mode, data is output from shift register 504 through dummy input/output terminals 418 and serial output terminal 412 at a frequency of eight bits (one byte) per cycle of serial clock signal SCLK.
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Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
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|U.S. Classification||365/221, 365/51, 365/219, 365/189.05, 711/103, 365/233.19, 365/220, 365/233.1, 365/185.33, 365/63|
|Cooperative Classification||G11C7/1075, G11C5/066|
|European Classification||G11C5/06M, G11C7/10T|
|May 26, 2005||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, HAN-SUNG;YEH, CHIA-YEN;PO, CHEN-HAO;AND OTHERS;REEL/FRAME:016607/0489
Effective date: 20050421
|Sep 22, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Dec 15, 2015||FPAY||Fee payment|
Year of fee payment: 8