|Publication number||US7398372 B2|
|Application number||US 10/180,391|
|Publication date||Jul 8, 2008|
|Filing date||Jun 25, 2002|
|Priority date||Jun 25, 2002|
|Also published as||US20030236966|
|Publication number||10180391, 180391, US 7398372 B2, US 7398372B2, US-B2-7398372, US7398372 B2, US7398372B2|
|Inventors||Nicholas G. Samra, Stephan J. Jourdan, David J. Sager, Glenn J. Hinton|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (1), Referenced by (9), Classifications (16), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Embodiments of the invention relate to the field of instruction caching within a computer system. More particularly, embodiments of the invention relate to improving storage efficiency within a cache memory and increasing instruction throughput within a microprocessor without significantly increasing computer system cost.
Cache memory is used in computer systems in order to increase performance by alleviating the need for a processor to fetch instructions from main system memory sources, such as dynamic random-access memory (DRAM). DRAM and other main memory sources may require longer access times due to the paging and memory cell access speed of such memory sources, which can cause the processor to incur wait-states and degrade computer system performance.
Cache memory, on the other hand, provides the processor with a way to fetch instructions quickly without incurring the wait-states associated with main memory sources, such as DRAM. Using cache memory improves computer system performance by making commonly-used instructions available to the processor in a memory architecture that does not require paging cycles, that uses a relatively fast-access memory cell, and that places the cache memory in close proximity to the processor's local bus in order to reduce physical delay associated with bus structures.
Similarly, instruction caches can also be used in high-performance microprocessor to decrease the average instruction fetch latency. In order to further decrease fetch latency, instructions may be cached in decoded, or “micro-op” (uop), format. Advantageously, caching instructions in uop format can decrease instruction decode logic within the microprocessor, because only instructions fetched as a result of a cache miss need be decoded.
Typically, one uop is able to be stored in each cache memory entry, as illustrated in
Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
Embodiments of the invention described herein pertain to increasing cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. More particularly, embodiments of the invention relate to “fusing” together a load micro-operation (uop) and an arithmetic uop contained within a computer instruction and storing the fused uop within a single cache memory entry.
The cache memory of
Uops typically do not vary in size, but the instruction to which they correspond often do depending on the instruction and the micro architecture for which the uop was designed. For example, a 32-bit microprocessor may have instructions containing 32 bits, whereas other instructions within the same instruction set may have only 16 bits, two of which may be included within the same 32-bit instruction.
Uops typically contain fields, such as an opcode, register, and immediate fields. The particular opcode(s) and number of registers and immediates supported by a particular uop vary, depending on the type of uop. Some instructions contain multiple uops, each performing a part of a complex instruction.
For example, one complex instruction that may be performed in conjunction with at least one embodiment the invention is the arithmetic/load instruction, add eax, [ebx][ecx], which contains an arithmetic uop and a load uop. The instruction loads a value from the address indicated by [ebx+ecx] and adds that value to the value currently stored in eax. Traditionally, the load and arithmetic uops are stored in separate cache entries, but embodiments of the invention enable them to be stored within the same cache entry.
The load/arithmetic instruction described above is an Intel® Architecture (IA) 32-bit instruction as specified by Intel Corporation of Santa Clara, Calif. However, other types of instructions in other instruction sets may be used in conjunction with embodiments of the invention, including instructions used in reduced instruction-set computing (RISC) processors.
An instruction residing in memory may be read into a cache memory residing either within the microprocessor or in close proximity to the microprocessor. Upon being stored within the cache memory, the instruction can be decoded into the separate uops of which it is composed. Traditionally the separate uops are stored within separate entries of the cache memory. However, embodiments of the invention enable the storage of intra-instruction uops into one cache entry.
Once the fused uop is stored within the instruction cache, it can be fetched by the rename unit 405 where it is unfused into an arithmetic child uop and a load child uop. Each child uop is further processed by a different parallel scheduling unit 410 415 and execution unit 420 425. Each execution unit executes a child uop according to register dependencies within the child uop and scheduling algorithms implemented by the corresponding scheduling unit. The child uops are then stored in, or “collected” by, the retirement unit 430 until both uops have successfully executed and are ready for retirement.
Advantageously, embodiments of the invention may be implemented using a minimal number of hardware and or software modifications. In fact, there are three general rules that can be followed in order to implement at least one embodiment with minimal hardware or software modifications:
1. Only one of the child uops of a fused uop may generate an exception in order to limit the complexity of the retirement unit necessary to process fused uops.
2. Each child uop must be sent to a different scheduling unit in order to allow all child uops to be issued simultaneously to the scheduling units without requiring additional scheduling unit ports.
3. The child uops must utilize only the existing fields of the original instruction uop, such as the opcode field, registers, immediates, etc. This allows uops to be stored within the same entry of an instruction cache without incurring a die size increase.
In many cases, uop fields are identical between two uops within an instruction, and may therefore be combined relatively easily. However, in some instances, the opcode field and register fields may require special fusing/unfusing techniques in order to facilitate execution of the child uops.
In the case of an arithmetic/load instruction, for example, the opcode field of each child uop is encoded with information pertaining to both the arithmetic operation and the load operation. When the opcode is presented to a load execution unit, the information corresponding to the load operation is decoded, whereas when the field is presented to the arithmetic execution unit the arithmetic information is decoded. In order to extract the proper information, each execution unit of
Each uop or groups of uops typically use registers to store data in ways unique to the needs of the uop or uop group. Therefore, when the fused uop is unfused into separate child uops, the register assignment may be unique to the particular uop or uop pairs involved. In one embodiment, the rename unit manages the assignment of registers for unfused uops, using special register unfusing techniques, such as the one illustrated in
As illustrated in
The result of the register unfusing technique illustrated in
The load and arithmetic child uops are presented to different scheduling units 635 in parallel where they are prepared for execution 640 by two separate parallel execution units. The execution units decode opcode information from a common opcode field corresponding to each child uop. The information pertaining to the particular child uop that an execution is operating upon is interpreted by the execution unit and the information pertaining to the other child uop is ignored.
Finally, once both child uops have executed, they are collected by the retire unit, which then retires the instruction 650.
Embodiments of the invention may include various implementations, including circuits (hardware) using complementary metal-oxide-semiconductor (CMOS) technology, machine-readable media with instructions (software) to perform embodiments of the invention when executed by a machine, such as a processor, or a combination of hardware and software.
The invention has been described herein by way of example without limiting the invention to any particular embodiment. Furthermore, embodiments of the invention facilitate numerous ways in which to take advantage of higher density instruction storage and is not limited to the advantages described herein.
For example, in addition to allowing for higher density instruction storage in cache memory without incurring additional cache capacity or significant die cost, embodiments of the invention enable increased fetch and rename throughput by operating on multiple uops at a time. In a processor with a fetch/rename throughput of uops per cycle, the same processor may increase the fetch/rename throughput to 8 uops per cycle using embodiments of the invention. Furthermore, since each fused uop only requires one entry in the retirement unit, the maximum number of unfused uops in the processor at any time as well as the retirement throughout may increase accordingly.
In the forgoing specification the invention has been described with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, according, to be regarded in an illustration rather than a restrictive sense.
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|U.S. Classification||712/209, 712/211, 712/243, 712/E09.054, 712/244, 712/24, 712/E09.037|
|International Classification||G06F15/00, G06F9/38, G06F9/30, G06F9/318, G06F9/40|
|Cooperative Classification||G06F9/3017, G06F9/3853|
|European Classification||G06F9/30U, G06F9/38E6|
|Sep 3, 2002||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SAMRA, NICHOLAS G.;JOURDAN, STEPHAN J.;SAGAR, DAVID J.;AND OTHERS;REEL/FRAME:013242/0240;SIGNING DATES FROM 20020730 TO 20020801
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