|Publication number||US7399674 B2|
|Application number||US 10/971,465|
|Publication date||Jul 15, 2008|
|Filing date||Oct 22, 2004|
|Priority date||Oct 22, 2004|
|Also published as||US7847336, US20060086968, US20080224200|
|Publication number||10971465, 971465, US 7399674 B2, US 7399674B2, US-B2-7399674, US7399674 B2, US7399674B2|
|Inventors||Ming-Shang Chen, Wen-Pin Lu|
|Original Assignee||Macronix International Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (10), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to fabrication of NAND-type flash EEPROMS without field oxide isolation.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of electrical power. Read only memory (ROM) is a non-volatile memory commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices.
ROM devices typically include multiple memory cell arrays. Each memory cell array may be visualized as including intersecting word lines and bit lines. Each word and bit line (or bit line pair) intersection can correspond to one bit of memory. In mask programmable metal oxide semiconductor (MOS) ROM devices, the presence or absence of an active MOS transistor at word and bit line intersections distinguishes between a stored logic ‘0’ and logic ‘1’.
A programmable read only memory (PROM) is similar to mask programmable ROM except that a user may store data values (i.e., program the PROM) using a PROM programmer. A PROM device is typically manufactured with fusible links at all word and bit line intersections. This corresponds to having all bits at a particular logic value, typically logic ‘1’. The PROM programmer is used to set desired bits to the opposite logic value, typically by applying a high voltage that vaporizes the fusible links corresponding to the desired bits. A typical PROM device can only be programmed once.
An erasable programmable read only memory (EPROM) is programmable like a PROM, but can also be erased (e.g., to an all logic ‘1’s state) by exposing it to ultraviolet light. A typical EPROM device has a floating gate MOS transistor at word and bit line intersections. Each MOS transistor has two gates: a floating gate and a non-floating or control gate. The floating gate is not electrically connected to any conductor, and is surrounded by a high impedance insulating material. To program the EPROM device, a high voltage is applied to the non-floating gate at each bit location where a logic value (e.g., a logic ‘0’) is to be stored. This causes a breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains on the floating gate. During subsequent read operations, the negative charge prevents the MOS transistor from forming a low resistance channel between a drain bit line and a source bit line (i.e., from turning on) when the transistor is selected.
An EPROM integrated circuit is normally housed in a package having a quartz lid, and the EPROM is erased by exposing the EPROM integrated circuit to ultraviolet light passed through the quartz lid. The insulating material surrounding the floating gates becomes slightly conductive when exposed to the ultraviolet light, allowing the accumulated negative charges on the floating gates to dissipate.
A typical electrically erasable programmable read only memory (EEPROM) device is similar to an EPROM device except that individual stored bits may be erased electrically. The floating gates in an EEPROM device are surrounded by a much thinner insulating layer, and accumulated negative charges on the floating gates can be dissipated by applying a voltage having a polarity opposite that of the programming voltage to the non-floating gates.
A relatively recent development in non-volatile memory is localized trapped charge devices. While these devices are sometimes referred to as nitride read only memory (NROM) devices, the acronym “NROM” is a part of a combination trademark of Saifun Semiconductors Ltd. (Netanya, Israel).
EEPROM arrays can be fabricated in either NOR or NAND configurations. The NAND configuration, which typically comprises parallel strings of memory cells connected in series, source-to-drain (NAND strings), may be preferred over the NOR configuration because of economy in the use of semiconductor real estate. Fabrication of NAND-type EEPROM arrays normally requires that isolation be provided between NAND strings in order that potentials applied to program a given cell do not influence the program state of neighboring EEPROM cells. Field oxide formed in a substrate between NAND strings may be used to provide the needed isolation. Shallow trench isolation (STI) may be employed as well. Field oxide and STI normally are formed before cell threshold voltage adjustment can be done. Including field oxide isolation in the design of EEPROM arrays may contribute undesirably to an increase in the thickness of individual cells, making it relatively difficult to fabricate flat arrays. Both STI and field oxide may consume substrate area that would be better utilized to provide a greater number of memory cells. That is, the requirement for field oxide isolation regions or STI in EEPROM arrays wastes semiconductor area and contributes to a decrease in the density of EEPROM arrays.
A need thus exists in the prior art for an EEPROM array without field oxide isolation regions. A further need exists for an EEPROM array without shallow trench isolation.
The present invention addresses these needs by providing methods for fabricating a NAND-type flash EEPROM without field oxide isolation. The invention herein disclosed provides, in an exemplary embodiment, a substrate doped with a first impurity type in which an implantation of the first impurity type is performed in order to control a desired threshold voltage of a memory cell. A tunnel oxide layer is formed on the substrate, a first floating gate layer is deposited on the tunnel oxide layer, and a first isolation layer is deposited on the first floating gate layer. A plurality of parallel regions is then etched in the first isolation layer and the first floating gate layer, the parallel regions being oriented in a reference direction and exposing portions of the tunnel oxide layer. A dopant of the first impurity type is then implanted into the substrate under the exposed portions of the tunnel oxide layer, forming a plurality of parallel electrical isolation regions in the substrate. A second isolation layer may be deposited to overlie the first isolation layer and the exposed portions of the tunnel oxide layer. A portion of the second isolation layer that overlies the first isolation layer then may be removed, and the first isolation layer then removed as well. A second floating gate layer may be deposited on the first floating gate layer, and a portion of the second floating gate layer that overlies the second isolation layer may be removed to expose a portion of the second isolation layer. An oxide-nitride-oxide (ONO) layer may then be formed on the second floating gate layer and the exposed portion of the second isolation layer. A layer of conducting material may be deposited on the ONO layer to form a control gate layer. After a re-oxidation step, a plurality of parallel regions of the control gate layer, the ONO layer, the second floating gate layer, the first floating gate layer, and the second isolation layer is etched to expose a plurality of parallel regions of the tunnel oxide layer. The parallel regions of the tunnel oxide layer are oriented in a direction substantially at a right angle to the reference direction. A dopant of a second impurity type is then implanted into the substrate under the exposed portions of the tunnel oxide layer to form a plurality of source/drain regions. In an exemplary embodiment, a dopant of the first impurity type may be a p-type dopant, and a dopant of the second impurity type may be an n-type dopant.
While the apparatus and method has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless expressly formulated under 35 U.S.C. 112, are not to be construed as necessarily limited in any way by the construction of “means” or “steps” limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents, and in the case where the claims are expressly formulated under 35 U.S.C. 112 are to be accorded full statutory equivalents under 35 U.S.C. 112.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one skilled in the art. For purposes of summarizing the present invention, certain aspects, advantages and novel features of the present invention are described herein. Of course, it is to be understood that not necessarily all such aspects, advantages or features will be embodied in any particular embodiment of the present invention. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims that follow.
Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the drawings are in simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as, top, bottom, left, right, up, down, over, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms should not be construed to limit the scope of the invention in any manner.
Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. The intent of the following detailed description, although discussing exemplary embodiments, is to be construed to cover all modifications, alternatives, and equivalents of the embodiments as may fall within the spirit and scope of the invention as defined by the appended claims. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of NAND-type EEPROM arrays. The present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are conventionally used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention.
Referring more particularly to the drawings,
The etch process that forms the plurality of parallel regions 217 may include, for example, a two-step etching process performed in sequence. The first etch process may be a selective etch process (e.g., a dry plasma etch process) in which the etchant has a higher selectivity for nitride than for photoresist. The first etch process may remove material in the first isolation layer 215 (that may be formed of silicon nitride), using photoresist as a mask. A second etch process may be a selective etch process (e.g., a dry plasma etch process) in which the etchant has a higher selectivity for silicon than for photoresist. The second etch process may remove material in the first floating gate layer 210 (that may be formed of polysilicon), likewise using photoresist as a mask. Remaining photoresist material then may be removed.
Formation of the plurality of parallel regions 217 exposes the thin tunnel oxide layer 205 in those regions. A first impurity type dopant, which in the illustrated embodiment is a p-type dopant, may then be implanted through the exposed portions, i.e. strips, of the thin tunnel oxide layer 205 into the substrate 200 at step 125. This implantation, which is self-aligned to the strips of the exposed tunnel oxide layer 205, forms p-type electrical isolation regions. It should be noted that the impurity type of the isolation regions is opposite to that of the drain/source regions described infra. According to an illustrative embodiment depicted in
At step 130 a second isolation layer 225 is deposited, covering the first isolation layer 215 and the exposed portion of tunnel oxide layer 205 in the plurality of parallel regions 217 as shown in
With reference to
An interlayer dielectric, which as presently embodied may comprise an oxide-nitride-oxide (QNO) layer 235 as shown in
The preceding cross-sectional views of
The cross-sectional depiction of
With the tunnel oxide layer 205 exposed, a second impurity type implantation, which as presently embodied comprises an n-type implantation, may be performed at step 170 to form a plurality of source/drain regions 247 in the substrate 200 under the exposed portions of the tunnel oxide layer 205 as shown in
An alternative embodiment of a NAND-type EEPROM array, i.e. a silicon-ONO-silicon (SONOS) NAND flash EEPROM array, employing localized trapped charge storage is illustrated in
Steps 320, 325, 330, 335, and 340 in the present implementation, and corresponding
The cross-sectional view illustrated in
In view of the foregoing, it will be understood by those skilled in the art that the methods of the present invention can facilitate formation of memory devices, and in particular memory devices not having field oxide, in an integrated circuit. The above-described embodiments have been provided by way of example, and the present invention is not limited to these examples. Multiple variations and modification to the disclosed embodiments will occur, to the extent not mutually exclusive, to those skilled in the art upon consideration of the foregoing description. Additionally, other combinations, omissions, substitutions and modifications will be apparent to the skilled artisan in view of the disclosure herein. Accordingly, the present invention is not intended to be limited by the disclosed embodiments, but is to be defined by reference to the appended claims.
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|U.S. Classification||438/264, 257/E21.682, 257/E27.103, 257/E21.679, 257/E21.179|
|Cooperative Classification||H01L27/11568, H01L27/115, H01L27/11521|
|European Classification||H01L27/115, H01L27/115G4, H01L27/115F4|
|Oct 22, 2004||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, MING-SHANG;LU, WEN-PIN;REEL/FRAME:015926/0187
Effective date: 20041021
|Sep 22, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Dec 15, 2015||FPAY||Fee payment|
Year of fee payment: 8