|Publication number||US7405161 B2|
|Application number||US 11/320,977|
|Publication date||Jul 29, 2008|
|Filing date||Dec 30, 2005|
|Priority date||Aug 31, 2005|
|Also published as||US20070049039|
|Publication number||11320977, 320977, US 7405161 B2, US 7405161B2, US-B2-7405161, US7405161 B2, US7405161B2|
|Inventors||Jeong Yel Jang, Kang Hyun Lee|
|Original Assignee||Dongbu Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (54), Referenced by (3), Classifications (22), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of Korean Application No. P2005-80708, filed on Aug. 31, 2005, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a method for fabricating a semiconductor device in which etching by-product is deposited on a photoresist film used as a mask.
2. Discussion of the Related Art
In a logic device, particularly, a flash memory device, the higher the packing density of the device, the smaller the Critical Dimension (CD) becomes. Consequently, if a floating gate pattern of the critical dimension below 130 nm is to be formed, not only the critical dimension of the gate pattern, but also the critical dimension of a space between adjacent gate lines becomes smaller, i.e. below 100 nm.
This requires reducing the thickness of the photoresist film to match the depth of focus of a KrF light source of a 248 nm wavelength. However, a balance must be achieved between reducing the thickness of the photoresist film for matching a depth of focus and maintaining a minimum required thickness of the photoresist film for etching. If the proper thickness of the photoresist film is not obtained, a defective pattern, such as deformation, or collapse of the pattern, is likely to happen.
To solve this problem, instead of using a KrF light source, an ArF light source of a 193 nm wavelength can be used in fabrication of a polysilicon transistor. However, since the critical dimension of a space between adjacent gate patterns is below 100 nm, the fabrication of the polysilicon transistor is difficult and takes a long time.
Following is a description of a method for fabricating a semiconductor device of a micronite pattern by using the KrF light source in accordance with the related art. The related art method for fabricating a semiconductor device will be described with reference to the attached drawings.
A photoresist film is coated on an entire surface of the substrate 10 including the BARC 14, and subjected to selective exposure and development, to form a photoresist film pattern 15.
The polysilicon pattern 12 a formed in this manner is used as a gate line or a gate electrode. The related art method for fabricating a semiconductor device suffers from poor process yield caused by repetitive and complicate deposition and etching steps, and contamination with defects caused by the use of many apparatuses coming from the repetitive, and complicated deposition and etching processes.
Additionally, the related art method uses an oxide hard mask to form a gate pattern with a line to line space critical dimension of below 100 nm.
Repetitive etching and film deposition as done in the related art complicate the fabrication process, require many apparatuses, and have a poor process yield caused by the contamination defects.
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An advantage of the present invention is that it provides a method for fabricating a semiconductor device, in which a by-product of etching is deposited on a photoresist film used as a mask.
Additional advantages, and features of the invention will be set forth in part in the description which follows, and will become apparent from the description, or may be learned by practice of the invention. These and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a semiconductor device includes the steps of depositing a polysilicon, and a bottom anti-refection coating on an entire surface of a substrate in succession, forming a photoresist film pattern on a predetermined portion of the bottom anti-refection coating, etching the bottom anti-refection coating by using the photoresist film pattern, to deposit by-product of the etching on sidewalls of the photoresist pattern to form spacers, and etching the polysilicon using the photoresist film pattern and the spacers as a mask to form a line.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
A method for fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention will be described in detail with reference to the attached drawings.
A photoresist film is coated on an entire surface of the substrate 100 including the BARC 103, and subjected to selective exposure and development, to form a photoresist film pattern 104.
Conditions for etching the BARC 103, and forming the sidewall spacers 103 b will be reviewed. The etching of the BARC 103, and the formation of the sidewall spacers 103 b are done using a Capacitive Coupled Plasma (CCP) apparatus, with the following conditions.
In the etching the BARC 103 to form the BARC pattern 103 a, about 60-100 sccm of CF4, about 100-150 sccm of Ar, and about 5-15 sccm of O2 are supplied for about 10-20 seconds at about 40-70 mT of pressure, and about 500-1000 W of power. Also, the gap between a plasma source (not shown) and the substrate 100 is about 25-30 mm in the CCP apparatus.
The by-product is deposited on the photoresist film pattern 104 using, O2 for about 15-30 seconds at about 20-50 mT of pressure and about 500-1000 W of power, with a gap of 25-30 mm between the plasma source (not shown) and the substrate 100.
The etching of the BARC 103, and the deposition of the by-product on a surface of the photoresist film pattern 104 are made in the CCP apparatus by applying RF power after injection of a reactive gas with the photoresist film pattern 104 into a chamber to form plasma to perform etching using radicals. The residence time period of the by-product of etching may be elongated to increase the probability that the by-product will deposit on the photoresist pattern 104, so that the critical dimension of the photoresist film pattern having the by-product deposited thereon is increased so that it is larger than the critical dimension of the photoresist film pattern measured after an original exposure. After increasing the critical dimension so that it is larger than the critical dimension measured after the original exposure by elongating the by-product residence time period, to increase the probability of deposition of the by-product on the photoresist film pattern 104, the polysilicon layer 102 of a gate is etched by using the photoresist pattern 104+103 b having the by-product deposited thereon.
All of the photoresist film pattern 104, the underlying BARC pattern 103 a, and the sidewall spacers 103 b are then removed. The polysilicon layer pattern left in this manner is the line 102 a. The line may be a gate line or a gate electrode.
The method for fabricating a semiconductor device according to an exemplary embodiment of the present invention permits to obtain a result in which a critical dimension of an actual width of the line is increased in a range of about 100-200 nm compared to a critical dimension (a width of the photoresist film pattern: CD) of each of pattern lines of the photoresist film pattern 104 after exposure. Accordingly, the line to line space critical dimension can be formed to be blow 100 nm. In the method for fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention, the line is constructed of a polysilicon layer.
The plasma etching is performed using plasma in a dry anisotropic etching process, during which an etch gas is supplied to a particular layer to be etched in a plasma etch chamber, and a RF field having a high energy is applied thereto to excite gas molecules to high energy levels so that the gas molecules can react with the layer to etch the layer.
In the anisotropic etching, a plasma source is one of the most important factors. Moreover, the anisotropic etching requires conditions which conflict with one another, such as a high etch rate, a high selectivity, less damage, and so on. To meet the above conditions a scheme for using capacitive coupling plasma (CCP), and a scheme for using inductive coupled plasma (ICP) have been developed.
In the method for fabricating a semiconductor device according to an exemplary embodiment of the present invention, the capacitive coupled plasma (CCP) apparatus may be used in the process of etching the BARC and of the forming sidewall spacers of the by-product. The CCP apparatus uses Dipole Ring Magnetron (DRM).
SEM photographs of a top view image of the polysilicon gate, and a section after the etching to form the polysilicon gate indicate that the method for fabricating a semiconductor device according to an exemplary embodiment of the present invention permits to obtain the same result of the related art but with fewer steps.
In the method for fabricating a semiconductor device according to an exemplary embodiment of the present invention, an exposure is made with a 248 nm light source and a KrF photoresist film, wherein by-product of etching of a BARC under the photoresist film is used as a hard mask, by means of which etching can be performed enabling formation of a gate pattern with a line to line space critical dimension below 10 nm, even if no micronite light source is used.
The above fabrication process permits reduction in steps in the fabrication process compared to the related art, and avoids expensive photoresist film for ArF and apparatus thereof to carry out a process for fabricating a semiconductor device having a micronite line to line space critical dimension.
As has been described, the method for fabricating a semiconductor device of the present invention has the following advantages.
By not removing the by-product of etching of a BARC under a photoresist pattern right away, but by depositing the by-product on a surface of the photoresist pattern, a hard mask with a greater width is formed with which an underlying polysilicon layer may be etched to form a polysilicon gate.
Accordingly, there is no need for a high definition photoresist film and apparatus for forming a gate polysilicon space with a line to line space below 100 nm. However, even if a 248 nm KrF photoresist film and apparatus thereof are used, formation of a micronite space is possible in correspondence to a space between adjacent hard mask patterns by forming the hard mask by growing widths of the photoresist film pattern by using the by-product. Thus, even if a design rule is small, the same effect is obtainable by using the KrF photoresist film and apparatus thereof without using the expensive apparatus (the ArF apparatus and the photoresist film thereof).
The method for fabricating a semiconductor device of the present invention allows to reduce the fabrication process from 7 or more steps down to 3 steps, thereby enhancing effectiveness of apparatus in etching, and reducing defective factors that are likely to occur during the steps coming from many steps. According to this, the yield can be increased.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
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|U.S. Classification||438/717, 216/49, 438/710, 438/585, 430/317, 257/E21.314, 216/51, 216/67, 216/41, 257/E21.252, 216/79, 257/E21.256|
|International Classification||H01L21/308, H01L21/28, H01L21/3213, H01L21/3065|
|Cooperative Classification||H01L21/31138, H01L21/31116, H01L21/32139|
|European Classification||H01L21/311C2B, H01L21/3213D, H01L21/311B2B|
|Dec 30, 2005||AS||Assignment|
Owner name: DONGBUANAM SEMICONDUCTOR INC., KOREA, REPUBLIC OF
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Effective date: 20051227
|Jun 15, 2006||AS||Assignment|
Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
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Owner name: DONGBU ELECTRONICS CO., LTD.,KOREA, REPUBLIC OF
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Effective date: 20060324
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