US 7421044 B2 Abstract Quasi error free method and system are presented for encoding and decoding information using turbo codes as an inner code in conjunction with an algebraic outer code linked by an interleaver. This combination of outer algebraic code and turbo inner code linked by an interleaver, which has a guaranteed minimum Depth between symbols output from the interleaver, can produce a quasi error free performance in systems utilizing Turbo-Codes without an increase in bandwidth.
Claims(24) 1. A method for encoding data for correction of burst errors with a predetermined length, the method comprising:
algebraically encoding the data for producing algebraically encoded data;
determining a guaranteed depth for an interleaver to guarantee that the burst errors with the predetermined length are repaired, the guaranteed depth corresponding to the predetermined length of the burst errors and a depth of separation of input symbols;
performing interleaving of the algebraic encoded data in the interleaver having the guaranteed depth for producing interleaved data;
turbo encoding the interleaved data for producing turbo encoded data;
mapping a first symbol of the turbo encoded data to a first constellation having a corresponding first mapping;
mapping a second symbol of uncoded data, that has bypassed the turbo encoding, to a second constellation having a corresponding second mapping; and
mapping a third symbol of uncoded data, that includes at least one bit that has undergone interleaving using an interleaving employed in accordance with the turbo encoding, to the second constellation having the corresponding second mapping.
2. The method of
3. The method of
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6. The method of
7. The method of
8. A method for decoding quasi error free encoded data the method comprising:
accepting data to be decoded which has been encoded according to the method of
turbo decoding the data;
deinterleaving the turbo decoded data, after the turbo decoding is completed, using a deinterleaver having a guaranteed depth to produce deinterleaved data; and
algebraically decoding the deinterleaved data to produce decoded data.
9. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. A decoder apparatus comprising:
a turbo decoder that accepts data to be decoded, which has been encoded according to the method of
a deinterleaver that accepts the turbo decoded data and produce deinterleaved data; and
an algebraic decoder that decodes the deinterleaved data to produce decoded data.
16. The apparatus of
17. The apparatus of
18. The apparatus of
19. The apparatus of
20. An encoding apparatus for correcting burst errors with a predetermined length comprising:
an input for accepting data;
an algebraic encoder for receiving the data and algebraically encoding the data for producing algebraically encoded data;
an interleaver for interleaving the algebraically encoded data, said interleaver having a guaranteed depth to guarantee that the burst errors with the predetermined length are repaired,
the guaranteed depth corresponding to said predetermined length of the burst errors and a depth of separation of input symbols, for producing interleaved data;
a turbo encoder for encoding the interleaved data for producing turbo encoded data; and
a mapper that is operable to:
map a first symbol of the turbo encoded data to a first constellation having a corresponding first mapping;
map a second symbol of uncoded data, that has bypassed turbo encoding within the turbo encoder, to a second constellation having a corresponding second mapping; and
map a third symbol of uncoded data, that includes at least one bit that has undergone interleaving using an interleaving employed in accordance with the turbo encoding of the turbo encoder, to the second constellation having the corresponding second mapping.
21. The apparatus of
22. The apparatus of
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24. The apparatus of
Description This application claims priority from provisional applications “TURBO TRELLIS ENCODER AND DECODER” Ser. No. 60/232,053 filed on Sep. 12, 2000, “PARALLEL CONCATENATED CODE WITH SISO INTERACTIVE TURBO DECODER Ser. No. 60/232,288 filed on Sep. 12, 2000, and “QUASI ERROR FREE (QEF) COMMUNICATION USING TURBO CODES” SER. No. 60/230,578 filed on Sep. 5, 2000 all of which are incorporated by reference herein as though set forth in full. This application also incorporates by reference the disclosure of U.S. application Ser. No. 09/878,148 filed Jun. 08, 2001 entitled PARALLEL CONCATENATED CODE WITH SOFT-IN SOFT-OUT INTERACTIVE TURBO DECODER as though set forth herein in full. The invention relates to methods, apparatus, and signals used in channel coding and decoding, and, in particular embodiments to methods, apparatus for use with a code having a turbo encoded inner code linked to an outer algebraic code via an interleaver. A significant amount of interest has recently been paid to channel coding. For example a recent authoritative text states: “Channel coding refers to the class of signal transformations designed to improve communications performance by enabling the transmitted signals to better withstand the effects of various channel impairments, such as noise, interference, and fading. These signal-processing techniques can be thought of as vehicles for accomplishing desirable system trade-offs (e.g., error-performance versus bandwidth, power versus bandwidth). Why do you suppose channel coding has become such a popular way to bring about these beneficial effects? The use of large-scale integrated circuits (LSI) and high-speed digital signal processing (DSP) techniques have made it possible to provide as much as 10 dB performance improvement through these methods, at much less cost than through the use of most other methods such as higher power transmitters or larger antennas.” From “Digital Communications” Fundamentals and Applications Second Edition by Bernard Sklar, page 305 ©2001 Prentice Hall PTR. Stated differently, improved coding techniques may provide systems that can operate at lower power, provide higher data rates, or provide lower bit error rates. Turbo codes in particular have received recent attention due to their ability to obtain good performance over relatively noisy channels. For example bit error rates on the order of 10 Although Turbo-Codes may recover data at low signal to noise ratios, an increase in relative signal strength does not produce a corresponding drop in error rate. In fact BERs of 10 Conventions and Definitions: Particular aspects of the invention disclosed herein depend upon and are sensitive to the sequence and ordering of data. To improve the clarity of this disclosure the following convention is adopted. Usually, items are listed in the order that they appear. Items listed as #1, #2, #3 are expected to appear in the order #1, #2, #3 listed, in agreement with the way they are read, i.e. from left to right. However, in engineering drawings, it is common to show a sequence being presented to a block of circuitry, with the right most tuple representing the earliest sequence, as shown in Herein, the convention is adopted that items, such as tuples will be written in the same convention as the drawings. That is in the order that they sequentially proceed in a circuit. For example, “Tuples Herein an interleaver is defined as a device having an input and an output. The input accepting data tuples and the output providing data tuples having the same component bits as the input tuples, except for order. An integral tuple (IT) interleaver is defined as an interleaver that reorders tuples that have been presented at the input, but does not separate the component bits of the input tuples. That is the tuples remain as integral units and adjacent bits in an input tuple will remain adjacent, even though the tuple has been relocated. The tuples, which are output from an IT interleaver are the same as the tuples input to interleaver, except for order. Hereinafter when the term interleaver is used, an IT interleaver will be meant. A separable tuple (ST) interleaver is defined as an interleaver that reorders the tuples input to it in the same manner as an IT interleaver, except that the bits in the input tuples are interleaved independently, so that bits that are adjacent to each other in an input tuple are interleaved separately and are interleaved into different output tuples. Each bit of an input tuple, when interleaved in an ST interleaver, will typically be found in a different tuple than the other bits of the input tuple from where it came. Although the input bits are interleaved separately in an ST interleaver, they are generally interleaved into the same position within the output tuple as they occupied within the input tuple. So for example, if an input tuple comprising two bits, a most significant bit and a least significant bit, is input into an ST interleaver the most significant bit will be interleaved into the most significant bit position in a first output tuple and the least significant bit will be interleaved into the least significant bit position in a second output tuple. Modulo-N sequence designation is a term meaning the modulo-N of the position of an element in a sequence. If there are k item s A modulo-N interleaver is defined as an interleaver wherein the interleaving function depends on the modulo-N value of the tuple input to the interleaver. Modulo interleavers are further defined and illustrated herein. A modulo-N encoding system is one that employs one or more modulo interleavers. In one aspect of the invention, the disclosure illustrates a method for providing quasi error free (QEF) encoding by algebraically encoding data, interleaving the encoded data in an interleaver having a guaranteed Depth, and turbo encoding the interleaved data. In another aspect of the invention, the disclosure illustrates a method for decoding QEF encoded data by turbo decoding the QEF encoded data, deinterleaving the data using a deinterleaver having a guaranteed Depth and algebraically decoding the deinterleaved data. In a further aspect of the invention, the disclosure illustrates an apparatus for providing quasi error free (QEF) encoding. The apparatus includes an input that accepts data, an algebraic encoder that receives the data, an interleaver, which has a guaranteed depth, that interleaves the data and a turbo encoder that encodes the interleaved data. In still a further aspect of the invention, the disclosure illustrates an apparatus for providing quasi error free (QEF) encoding. The apparatus includes a turbo decoder that accepts QEF data to be decoded, a deinterleaver that accepts the turbo decoded data and produce deinterleaved data and an algebraic decoder that decodes the deinterleaved data. The features, aspects, and advantages of the present invention which have been described in the above summary will be better understood with regard to the following description, appended claims, and accompanying drawings where: In Data Source The interleaved sequence provided by interleaver A particular interleaver implementation is next described in order to illustrate diversification of the outer code such that long bursts of errors at the output of the inner (turbo) decoder do not preclude the overall coding system from achieving quasi error free operation. Such data bits which bypasses the turbo encoder The Ramsey interleaver Input symbols are placed in the ring Depth tuples apart. The ringsize is selected so that Depth * Blen (where Blen is equal to the length, in terms of the symbols input into the interleaver, of an outer code block.) is equal to the ring size. Also Depth and Blen are selected to be relatively prime numbers, which are not divisors of one another. The symbols are placed in the ring Depth apart until the ring is full. Once the ring is full the interleaver can output interleaved symbols by outputting sequential symbols from the ring as shown generally at In order to achieve quasi error free communications interleaver The necessity of being able to correct burst errors in order to achieve a quasi error free communication using a system as illustrated in Constituent encoders, such as first encoder One of the forms of a constituent encoder is illustrated in The encoder of The encoder illustrated in The encoder illustrated in The encoder of The first interleaver In Source tuples T Interleavers In order not to miss any symbols, each interleaver is a modulo-type interleaver. To understand the meaning of the term modulo interleaver, one can consider the interleaver of For example, in In other words an interleaver is a device that rearranges items in a sequence. The sequence is input in a certain order. An interleaver receives the items form the input sequence, I, in the order I For example, in the case of a modulo-2 interleaver the sequence designation may be even and odd tuples as illustrated at The modulo-2 type interleaver illustrated in As a further illustration of modulo interleaving, a modulo-8 interleaver is illustrated at In summary, a modulo interleaver accepts a sequence of input tuples which has a modulo sequence designation equal to the input tuple number modulo-N where N=H of the interleaver counting the null interleaver. The modulo interleaver then produces an interleaved sequence which also has a sequence designation equal to the interleaved tuple number divided by the modulo of the interleaver. In a modulo interleaver bits which start out in an input tuple with a certain sequence designation must end up in an interleaved modulo designation in embodiments of the present invention. Each of the N interleavers in a modulo N interleaving system would provide for the permuting of tuples in a manner similar to the examples in The input tuple of an interleaver, can have any number of bits including a single bit. In the case where a single bit is designated as the input tuple, the modulo interleaver may be called a bit interleaver. Inputs to interleavers may also be arbitrarily divided into tuples. For example, if 4 bits are input to in interleaver at a time then the 4 bits may be regarded as a single input tuple, two 2 bit input tuples or four 1 bit input tuples. For the purposes of clarity of the present application if 4 bits are input into an interleaver the 4 bits are generally considered to be a single input tuple of 4 bits. The 4 bits however may also be considered to be ½ of an 8 bit input tuple, two 2 bit input tuples or four 1 bit input tuples the principles described herein. If all input bits input to the interleaver are kept together and interleaved then the modulo interleaver is designated a tuple interleaver (a.k.a. integral tuple interleaver) because the input bits are interleaved as a single tuple. The input bits may be also interleaved as separate tuples. Additionally, a hybrid scheme may be implimented in which the input tuples are interleaved as tuples to their appropriate sequence positions, but additionally the bits of the input tuples are interleaved separately. This hybrid scheme has been designated as an ST interleaver. In an ST interleaver, input tuples with a given modulo sequence designation are still interleaved to interleaved tuples of similar sequence designations. Additionally, however, the individual bits of the input tuple may be separated and interleaved into different interleaved tuples (the interleaved tuples must all have the same modulo sequence designation as the input tuple from which the interleaved tuple bits were obtained). The concepts of a tuple modulo interleaver, a bit modulo interleaver, and a bit-tuple modulo interleaver are illustrated in the following drawings. In the illustrated interleaver of Similarly, the most significant bits of input tuples Selector mechanism A feature of modulo tuple interleaving systems, as well as a modulo ST interleaving systems is that encoded versions of all the input tuple bits appear in an output tuple stream. This is illustrated in output sequence Those skilled in the art will realize that the scheme disclosed with respect to Additionally, the selection of even and odd encoders is arbitrary and although the even encoder is shown as receiving uninterleaved tuples, it would be equivalent to switch encoders and have the odd encoder receive uninterleaved tuples. Additionally, as previously mentioned the tuples provided to both encoders may be interleaved. The seed interleaving sequence can also be used to create an additional two sequences. The interleaving matrix This methodology can be extended to any modulo desired. Once the sequence It should be noted that each component sequence in the creation of any modulo interleaver will contain all the same elements as any other component sequence in the creation of a modulo interleaver. Sequence 1 and 2 have the same elements as sequence 3 and 4. Only the order of the elements in the sequence are changed. The order of elements in the component sequence may be changed in any number of a variety of ways. Four sequences have been illustrated as being created through the use of interleaving matrix and a seed sequence, through the use of the inverse interleaving of a seed sequence, through the use of a timed reversed interleaving of a seed sequence and through the use of an inverse of a time interleaved reverse of a seed sequence. The creation of component sequences are not limited to merely the methods illustrated. Multiple other methods of creating randomized and S randomized component sequences are known in the art. As long as the component sequences have the same elements (which are translated into addresses of the interleaving sequence) modulo interleavers can be created from them. The method here described is a method for creating modulo interleavers and not for evaluating the effectiveness of the modulo interleavers. Effectiveness of the modulo interleavers may be dependent on a variety of factors which may be measured in a variety of ways. The subject of the effectiveness of interleavers is one currently of much discussion in the art. Table 5 is an illustration of the use of sequence 1, 2, and 3 in order to create a modulo-3 interleaving sequence. In row 1 of table 5 sequence 1 is listed. In row 2 of table 5 sequence 2 is listed and in row 3 sequence 3 is listed. The elements of each of the three sequences are then interspersed in row 4 of table 5 to create sequence 1-2-3. In table 6 the positions of the elements in sequence 1-2-3 are labeled from 0 to 17. Each value in sequence 1-2-3 is then multiplied by In table 8 row 1 the positions of each element in sequence 1-2-3 -4 are listed. In row 3 of table 8 each element of sequence 1-2-3 -4 is multiplied by a 4 as it is desired to create a modulo-4 interleaving sequence. Once the elements of sequence 1-2-3 -4have been multiplied by 4 as illustrated in row 3 of table 8, each element has added to it a modulo-4 of the position number, i.e. the modulo sequence designation of that element within the 1-2-3-4 sequence. The multiplied value of sequence 1-2-3 -4 is then added to the modulo-4 of the position in sequence 8 results. Sequence 8 is listed in row 5 of table 8. To verify that the sequence 8 generated is a modulo-4 interleaving sequence each number in the sequence can be divided mod 4. When each element in sequence 6 is divided modulo-4 sequence of 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 etc. results. Thus, it is confirmed that sequence 8 is a modulo-4 interleaving sequence, which can be used to take an input sequence of tuples and create a modulo interleaved sequence of tuples. The encoded tuple c Accordingly, all the components of each tuple are encoded in the odd encoder and all components of each tuple are also encoded in the even encoder. However, only encoded tuples corresponding to input tuples having an odd modulo sequence designation are selected from odd encoder Both encoder The even/odd encoder of Both encoders The overall TTCM encoder is a ⅔ encoder because both the odd encoder The output of odd encoder From the foregoing TTCM encoder examples of The basic constituent encoders illustrated in Additionally the interleavers illustrated in Additionally the TTCM encoders illustrated in Maps 0 through 3 are chosen through a process different from the traditional approach of performing an Ungerboeck mapping (as given in the classic work “Channel Coding with Multilevel/Phase Signals” by Gottfried Ungerboeck, IEEE Transactions on Information Theory Vol. 28 No. 1 January 1982). In contrast in embodiments of the present invention, the approach used to develop the mappings was to select non Ungerboeck mappings, then to measure the distance between the code words of the mapping. Mappings with the greatest average effective distance are selected. Finally the mappings with the greatest average effective distance are simulated and those with the best performance are selected. Average effective distance is as described by S. Dolinar and D. Divsalar in their paper “Weight Distributions for Turbo Codes Using Random and Non-Random Permeations,” TDA progress report 42-121, JPL, August 1995. The TTCM decoder of The MAP Algorithm is used to determine the likelihood of the possible particular information bits transmitted at a particular bit time. Turbo decoders, in general, may employ a SOVA (Soft Output Viterbi Algorithm) for decoding. SOVA is derived from the classical Viterbi Decoding Algorithm (VDA). The classical VDA takes soft inputs and produces hard outputs a sequence of ones and zeros. The hard outputs are estimates of values, of a sequence of information bits. In general, the SOVA Algorithm takes the hard outputs of the classical VDA and produces weightings that represent the reliability of the hard outputs. The MAP Algorithm, implimented in the TTCM decoder of The input to the circular buffer i.e. input queue The metric calculator SISO modules The decoding process is done in iterations. The SISO module One feature of the TTCM decoder is that, during each iteration, the two SISO modules After the first iteration, the SISO modules Because the component decoders SISO At the end of the For rate ⅔, the conditional points processing module SISOs 0 through N process the points provided by the metric calculator in parallel. The output of one SISO provides A Priori values for the next SISO. For example SISO 0 will provide an A Priori value for SISO 1, SISO 1 will provide an A Priori value for SISO 2, etc. This is made possible because SISO 0 impliments a Map decoding algorithm and processes points that have a modulo sequence position of 0 within the block of data being processed, SISO 1 impliments a Map decoding algorithm and processes points that have a modulo sequence position of 1 within the block of data being processed, and so forth. By matching the modulo of the encoding system to the modulo of the decoding system the decoding of the data transmitted can be done in parallel. The amount of parallel processing available is limited only by the size of the data block being processed and the modulo of the encoding and decoding system that can be implemented. Patent Citations
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