|Publication number||US7433401 B1|
|Application number||US 10/443,972|
|Publication date||Oct 7, 2008|
|Filing date||May 22, 2003|
|Priority date||May 22, 2003|
|Also published as||US7564900|
|Publication number||10443972, 443972, US 7433401 B1, US 7433401B1, US-B1-7433401, US7433401 B1, US7433401B1|
|Original Assignee||Marvell International Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (1), Referenced by (7), Classifications (7), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to signal processors for communications channels, and more particularly to a signal processor having a mixed-mode architecture and a mixed-mode decision feedback equalizer.
Communications systems often employ digital signal processors (DSPs) on the receiver end of a communications channel. The DSPs apply amplification, filtering and/or equalization to reduce attenuation, distortion and other channel effects. The channel may cause intersymbol interference (ISI), for example when the transmitted signals have a data rate that exceeds the bandwidth of the communications channel. When a transmitted symbol having a period of T is transmitted, the received signal may have a period that exceeds T, which may interfere with subsequent transmitted symbols.
Referring now to
An output of the ADC 42 is input to a finite impulse response (FIR) filter 44, which performs filtering using one or more taps and delay elements. An output of the FIR filter 44 is input to a non-inverting input of a summer 48, which has an output that is input to a decision circuit 50 and to a non-inverting input of a summer 54. The decision circuit 50 attempts to identify the transmitted signal based upon the received signal. The decision circuit 50 is typically implemented using a comparator, which compares the received signal to a predetermined threshold.
An output of the decision circuit 50 is input to an inverting input of the summer 54 and to an input of a decision feedback equalizer (DFE) 58. The DFE 58 is operated in a manner that is similar to a FIR filter. The DFE 58 attempts to eliminate the ISI effects of a detected symbol on future received symbols. The DFE 58 includes one or more taps having tap weights and one or more delay elements. An output of the DFE 58 is fed back to an inverting input of the summer 48.
An output of the summer 54 is input to an adaptation circuit 60, which gradually adjusts parameters of the DSP 30 to minimize errors. For example, the adaptation circuit 60 may be a least means squared (LMS) adaptation circuit. The adaptation circuit 60 outputs adjusted tap weights to the DFE 58 and adjusted timing to a phase locked loop (PLL) 64. The adaptation circuit 60 may also output an automatic gain control (AGC) signal to the amplifier 40, which adjusts the gain of the amplifier 40. The PLL 64 receives the timing adjustments and outputs a clock signal to the ADC 42.
Referring now to
In the example illustrated in
The tap weight w0 of the DFE 58 defines a critical path that is shown in a simplified form in
The critical path 96 is formed by a path y→decision block→ŷ→ŷw0→x−ŷw0=1T. As the frequency of operation increases and approaches and/or exceeds 1 GHz, the ADC 42 becomes increasingly more difficult to implement. Even if the ADC 42 can be implemented at a desired high operating frequency, the power that is required to operate the ADC 42 becomes prohibitive.
A mixed-mode signal processor architecture according to the present invention provides decision feedback equalization for a communications channel. A decision circuit receives an analog signal and outputs a digital signal. A mixed-mode decision feedback equalizer (DFE) includes a plurality of tap weights and produces a DFE signal using the analog signal, the digital signal and the tap weights.
In other features, a first summer has a first input that communicates with an input of the decision circuit, a second input that communicates with an output of the decision circuit, and an output. An adaptation circuit communicates with the output of the first summer and adjusts the tap weights of the mixed-mode DFE.
In still other features, a phase locked loop (PLL) outputs a clock signal to the decision circuit. The adaptation circuit adjusts the clock signal of the PLL. An amplifier amplifies a received signal from the communications channel. The adaptation circuit generates an automatic gain control signal that adjusts a gain of the amplifier.
In yet other features, a second summer has a first input that receives the analog signal, a second input that receives the DFE signal and an output that communicates with the decision circuit. The mixed-mode DFE includes a voltage to current converter that converts the analog signal to a current signal. A polarity switching circuit selectively switches a polarity of the current signal based on an output of the decision circuit. A current scaling circuit receives an output of the polarity switching circuit and scales the current signal using a first tap weight.
In still other features, the mixed-mode DFE includes a first comparator having a reset stage and an output stage. A second comparator has a reset stage and an output stage. The reset stage of the first comparator overlaps the output stage of the second comparator. The mixed-mode DFE includes a voltage to current converter that converts the analog signal to a current signal. A first polarity switching circuit selectively adjusts a polarity of the current signal based on an output of the first comparator. A second polarity switching circuit selectively adjusts a polarity of the current signal based on an output of the second comparator. A current scaling circuit receives outputs of the first and second polarity switching circuits and scales the current signal using a first tap weight.
In still other features, the mixed-mode DFE includes a delay element that receives the current signal and that outputs a first delayed signal. A second multiplier multiplies the first delayed signal by a second tap weight to generate a second product. A second delay element receives the first delayed signal and outputs a second delayed signal. A third multiplier multiplies the second delayed signal by a third tap weight to generate a third product.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:
The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements.
Referring now to
The decision circuit 114 can be implemented using a comparator, which compares the input signal to a predetermined threshold. The decision circuit 114 decides whether the input signal corresponds to a first state such as 1 or a second state such as −1. An output of the decision circuit 114 is connected to an inverting input of the summer 118 and to a mixed-mode DFE 124 according to the present invention. In a preferred embodiment, the DFE 124 is a mixed-mode DFE 124, as will be described below.
An output of the summer 118 is input to a digital adaptation device 128, which updates tap weights of the DFE 124. The adaptation device 128 also updates timing of a phase locked loop (PLL) 130, which generates a clock signal for the decision circuit 114. The adaptation device 128 also outputs an AGC signal to the amplifier 110, which adjusts the gain of the amplifier 110. The adaptation device 128 can be a least means squared (LMS) adaptation device.
Referring now to
More particularly, when the decision circuit 114 turns on switches S1, the input to the polarity switching circuit 140 is multiplied by 1. When the decision circuit 114 turns on switches
Referring now to
The DFE 124 attempts to cancel the effects of the received signal x that occur after 2 T. A DFE tap weight w0 attempts to offset the effects of the received signal x that occur at 3 T. A DFE tap weight w1 attempts to offset the effects of the received signal x that occur at 4 T. A DFE tap weight w2 attempts to offsets the effects of the received signal x that occur at 5 T. While the signals at these successive periods are not cancelled completely, substantial cancellation occurs. As a result of the cancellation provided by the DFE 124, the decision circuit 114 can use a lower threshold to decide whether a signal is present, which improves accuracy. For example, a lower threshold of 0.25 can be used in
Referring now to
Referring now to
Referring now to
Referring now to
Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. While the present invention is particularly suited to operation at speeds of 1 GHz and above, the present invention may also be used at lower operating frequencies. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7633318 *||Jul 18, 2008||Dec 15, 2009||Hynix Semiconductor Inc.||Data receiver of semiconductor integrated circuit and method for controlling the same|
|US7991078 *||Dec 10, 2007||Aug 2, 2011||Sony Corporation||Signal processing apparatus, signal processing method, and program|
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|International Classification||H03H7/30, H03K5/159|
|Cooperative Classification||H04L2025/03605, H04L2025/03503, H04L25/03057|
|May 22, 2003||AS||Assignment|
Owner name: MARVELL SEMICONDUCTOR, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROO, PIERTE;REEL/FRAME:014114/0129
Effective date: 20030520
|May 23, 2003||AS||Assignment|
Owner name: MARVELL INTERNATIONAL LTD., BERMUDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL SEMICONDUCTOR, INC.;REEL/FRAME:014111/0779
Effective date: 20030521
|Dec 16, 2008||CC||Certificate of correction|
|Apr 9, 2012||FPAY||Fee payment|
Year of fee payment: 4
|Apr 7, 2016||FPAY||Fee payment|
Year of fee payment: 8