|Publication number||US7441137 B1|
|Application number||US 11/189,203|
|Publication date||Oct 21, 2008|
|Filing date||Jul 25, 2005|
|Priority date||Jul 25, 2005|
|Publication number||11189203, 189203, US 7441137 B1, US 7441137B1, US-B1-7441137, US7441137 B1, US7441137B1|
|Original Assignee||Nvidia Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (41), Classifications (9), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is related to co-pending U.S. patent application Ser. No. 10/189,223 entitled, “ADVANCED VOLTAGE REGULATION USING ANTICIPATORY LOAD INFORMATION”, filed herewith.
1. Field of the Invention
This invention relates generally to computer systems and more specifically to an apparatus and method for adjusting operation of a voltage regulator in anticipation of a change in load.
2. Description of the Related Art
In a typical computer system, one or more voltage regulators provide supply voltages to various system components. For example, a first voltage regulator on a motherboard may provide a supply voltage to a central processing unit (CPU) while a second voltage regulator on a graphics card may provide a supply voltage to a graphics processing unit (GPU). Unfortunately, as operating frequencies increase, voltage regulators may struggle to supply enough current when such processing devices rapidly demand additional current.
This may be illustrated by considering the exemplary graphics processing subsystem shown in
As illustrated in
Similarly, when the pipelines are unloaded (at time T1), a sudden decrease in current load may result in a upward transient spike. For some cases, the peak-to-peak magnitude of the transient may be even greater upon release of the load than when the load is increased. In any case, the feedback mechanism may ensure that after a recovery time (labeled TR1) the output voltage may recover to at least approach the previous level.
If these transient voltage spikes cause the supply voltage level to fall below a minimum threshold or exceed a maximum threshold, the GPU may fail, regardless of how quickly the previous voltage level is restored. Unfortunately, by the time the regulator 100 is able to detect the transient voltage changes based on the feedback signal, the output voltage may have changed too much to allow the regulator 100 to adequately compensate. In some cases, the peak-to-peak magnitude of the transient voltage spikes may be controlled with careful selection of components in the regulator circuit. For example, output capacitors CO (typically dominated by rather large “bulk” capacitors) used in the regulator circuit may be chosen with an effective series resistance (ESR) that minimizes peak-to-peak transient magnitudes, while still providing an adequate recovery time. Unfortunately, the size and/or cost penalty of such capacitors tends to be prohibitive.
Accordingly, what is needed is an improved method and apparatus for regulating voltage supplied to integrated circuit devices, such as processing devices (CPUs and GPUs) that exhibit large abrupt changes in current demand.
Embodiments of the present invention generally provide methods and apparatus for controlling a voltage supplied to a device based on an anticipated change of load current demanded by the device.
One embodiment provides a method of controlling an output voltage provided to a device by a voltage regulator. The method generally includes receiving, by the voltage regulator, a load control signal indicating an anticipated change in load current required by the device and directly controlling a driver circuit of the voltage regulator used to generate the output voltage based on the load control signal.
Another embodiment provides a voltage regulator including a drive circuit and a control circuit. The voltage regulator includes at least one input pad to receive a load control signal indicating an anticipated change in load current required by the device. The control circuit is generally configured to control the drive circuit to alter the output voltage based on the load control signal.
Another embodiment provides a computer system generally including a voltage regulator and a processor device that is supplied an output voltage by the voltage regulator. A control circuit is included, internal to the voltage regulator, to alter the output voltage based on a load control signal indicating an anticipated change in load current required by the processor device.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Embodiments of the present invention provide a mechanism allowing a voltage regulator to adjust its output voltage in anticipation of a change in load. The voltage regulator provides a supply voltage to a device which, therefore, represents a load driven by the voltage regulator. The device, in turn, provides a load signal in anticipation of a change in load (e.g., caused by the utilization of a greater or lesser number of components on the device). In other words, the load signal may provide an “early warning signal” of sorts, causing the voltage regulator to adjust the supply voltage provided to the device to minimize the impact of transient voltage spikes caused by the change in load. As a result, the effective transient voltage response of the voltage regulator may improved, while the size and cost of components in the regulator circuitry (e.g., load capacitors) may be reduced.
As a specific, but not limiting example, one embodiment of the present invention provides a graphics processing unit (GPU) that adjusts a load signal in anticipation of a change in load, for example, based on an expected change in utilization of a number of parallel processing pipelines. However, those skilled in the art will recognize that the concepts described herein may be used to similar advantage in a variety of different devices, such as central processing units (CPUs) digital signal processors (DSPs), and the like, to reduce the impact of voltage transients caused by abrupt changes in load.
As previously described, the GPU 310 may utilize a number of high speed processing pipelines operating in parallel. When several of these pipelines are loaded up for processing, after being idle, the resultant load increase may cause current demand several times greater than what is demanded when the pipelines are not as heavily loaded. With several hundred million transistors in the pipelines, the increase in current may be well over 100%. As previously described, with reference to
As explained in greater detail herein, by generating the load signal in anticipation of such a change in load, the GPU 310 may provide an early warning signal of sorts, causing the voltage regulator 300 to adjust the supply voltage to compensate. For example, as illustrated in
For comparison, in
The operations begin, at step 502, by detecting an expected change in load current. As an example, the GPU 310 may monitor a number of idle cycles for a sample set of pipelines as an indication that the pipelines are being loaded. As another example, a set of instructions (e.g., a shader program), executed by the GPU 310 may contain markers that provide an indication to the GPU 310 that heavy pipeline activity, or a reduction in pipeline activity, is likely.
In any case, if a change in load is not expected, as determined at step 504, the operations are repeated without adjusting the load signal. On the other hand, if a change is load is expected, the load signal is adjusted, at step 506, thereby causing the a corresponding anticipatory change in the voltage supplied by the voltage regulator. As will be described in greater detail below, the load signal may be a single bit (e.g., driven on a singly output pin) or multiple bits. A single bit output signal will allow a device to indicate more or less current is to be required. Multiple bits, on the other hand, may allow quantification of the additional current expected (e.g., 25%, 50%, etc.), allowing the anticipatory increases or decreases in voltage supplied by the regulator to be adjusted accordingly.
For some embodiments, feedback circuitry external to the voltage regulator may be configured to allow adjustment of a feedback signal provided to the voltage regulator in response to a change in an anticipatory load signal provided by a processing device. The exact circuitry may vary depending on the exact type of feedback signal utilized by the voltage regulator.
As an example,
V FB =V OUT *[R B/(R A +R B)]
Once the load signal is asserted (logic high or ‘1’), indicating an expected increase in current demand, the transistor NL is switched on and the bottom portion of the voltage divider network becomes RL in parallel with RB (RB∥RL). As a result, the feedback voltage is defined by the following equation based on the voltage divider:
V FB =V OUT *[R B ∥R L/(R A +R B ∥R L)]
Because the parallel combination of RB and RL is less than RB alone, the feedback voltage is reduced which should cause the voltage regulator 600 to increase its output and raise VOUT. As illustrated, the regulator 600 may include an error amplifier 602 that generates an offset or “error” voltage VERROR indicating a difference between the feedback voltage and a reference voltage. The error voltage may be fed back to a voltage adjust circuit 604 that increases the output voltage if the feedback voltage is less than the reference or decreases the output voltage if the feedback voltage is greater than the reference voltage.
For embodiments where a multi-bit load signal is generated, multiple load resistors may be selectively placed in parallel to incrementally adjust the feedback voltage, as necessary. For some embodiments, the load signal may be used to adjust the reference voltage in a similar manner, which may have a similar effect. For example, increasing VREF when the load signal is asserted would also result in an increase in VERROR and a corresponding increase in VOUT.
As another example of how the load signal may be used to adjust the output voltage of a regulator,
Those skilled in the art will recognize that various other types of feedback mechanisms may also be used and such mechanisms may be configured to allow the feedback signal provided thereby to be varied in any manner appropriate based on a load signal generated by a processor device.
For some embodiments, a voltage regulator may be provided with internal control circuitry to vary the regulator output in response to a change in an anticipatory load signal provided by a processing device. In some cases, such internal control circuitry may provide faster response times than conventional feedback mechanisms manipulated by the load control signal, as discussed above. In other words, while the embodiments described above may be used to achieve substantial improvement in performance of conventional voltage regulators, regulators with internal controls that allow a more direct path to adjust regulator output based on the load control signal may provide even greater improvements.
However, the internal controls 802 may, in effect bypass the conventional feedback path and provide a much faster response time by directly affecting the driver circuit 806. For some embodiments, internal controls 802 may work in conjunction with a conventional feedback mechanism. For example, the normal feedback mechanism may serve to and provide stability in situations with relatively normal changes in load current demands, while the internal controls 802 allows regulator output to be rapidly adjusted when a large change in load current demand is anticipated. Exactly how the internal controls 802 control the driver circuit 806 will depend on the mechanism used by the driver circuit 806.
For example, as illustrated in
For other embodiments, the driver circuit 806 may include a pulse width modulation (PWM) circuit 908 configured to vary the duty cycle of one or more pulse width modulated signals used to switch an output field effect transistor (FET) 909, as illustrated in
For example, if the anticipatory load control signal received by the internal controls 902 indicates a sudden increase in load current demand is anticipated, the internal controls 902 may generate PWM control signals to cause the PWM circuit 908 to immediately increase the duty cycle of the PWM output signals to increase the regulator output. The PWM control signals may include a set of clock or “phase” signals that are out of phase with respect to one another. To compensate for an anticipated increase in load current demand, all phases may be “turned on” (e.g., full duty cycle) to temporarily increase regulator output. Conversely, if the load control signal indicates a sudden decrease in load current demand is anticipated, the internal controls 902 may generate PWM control signals to cause the PWM circuit 908 to immediately decrease the duty cycle of the PWM output signals to decrease the regulator output.
As described above, a single bit load control signal may allow the voltage regulator to simply increase or decrease regulator output, while multiple bits may allow quantification of the additional current expected (e.g., 25%, 50%, etc.), allowing the anticipatory increases or decreases in voltage supplied by the regulator to be adjusted accordingly. In either case, the internal controls may include signal conditioning designed to receive the load control signal and generate the necessary type control signals (e.g., PWM phase signals) to cause the drive circuit to adjust the regulator output as accordingly.
In some cases, an even greater degree of flexibility in regulator may be achieved by providing a scaling mechanism, wherein the magnitude of the changes in regulator output caused by the load control signal may be controlled. In other words, such scaling may allow the same regulator to be configured to increase/decrease the regulator output voltage over a relatively wide range (e.g., 1.5V to 3.3 V), with the particular range selected depending on the needs of a particular application. This may provide an advantage from an inventory perspective, as a single such regulator may be stocked rather than multiple regulators. Further, increases in volume may also be achieved, which may lead to reduced cost.
As illustrated in
As illustrated in
For some embodiments, such a register 1009 may also be used to enable/disable use of the internal controls 1002 to alter regulator output based on the load control signal. For example, single bit may be set to enable/disable the effect of the load control signal. A default setting of the bit may be to disable the effect of the load control signal, for example, until a processor device writes to the register 1009 to enable use of the internal controls 1002. For some embodiments, similar scalability may be provided by non-volatile storage means, such as one or more electrically programmable fuses that may be blown under external control.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
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|U.S. Classification||713/340, 713/310, 713/300|
|Cooperative Classification||H02M2001/0019, G05F1/462, H02M3/156|
|European Classification||G05F1/46B, H02M3/156|
|Jul 25, 2005||AS||Assignment|
Owner name: NVIDIA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MIMBERG, LUDGER;REEL/FRAME:016801/0079
Effective date: 20050722
|Apr 4, 2012||FPAY||Fee payment|
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