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Publication numberUS7442570 B2
Publication typeGrant
Application numberUS 11/084,296
Publication dateOct 28, 2008
Filing dateMar 18, 2005
Priority dateMar 18, 2005
Fee statusPaid
Also published asCN101171665A, EP1859475A2, EP1859475A4, US8084332, US8633049, US20060208326, US20080283990, US20120094435, US20140131820, WO2006101769A2, WO2006101769A3
Publication number084296, 11084296, US 7442570 B2, US 7442570B2, US-B2-7442570, US7442570 B2, US7442570B2
InventorsSteven S. Nasiri, Anthony Francis Flannery, JR.
Original AssigneeInvensence Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US 7442570 B2
Abstract
A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.
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Claims(10)
1. A method for bonding a CMOS wafer and a MEMS wafer, the CMOS wafer including an integrated circuit, the MEMS wafer including a MEMS device, the method comprising:
depositing a germanium bonding layer on the MEMS wafer;
forming a substantially aluminum bonding layer on the CMOS wafer, wherein the CMOS wafer is placed in a first chuck and the MEMs wafer is placed in a second chuck;
aligning CMOS wafer and the MEMS wafer; and
forming a eutectic bond between the germanium bonding layer on the MEMS wafer and the substantially aluminum metalization bonding layer on the CMOS wafer, wherein the eutectic bond is formed by keeping the CMOS wafer and the MEMS wafer apart until the temperature on each of the top and bottom chucks reaches a first predetermined temperature that is less than 450° C., inducing forming gas at an atmospheric pressure prior to bonding, providing a vacuum to remove the forming gas, applying a uniform force across the first chuck and the second chuck, and then ramping the temperature over the eutectic point of the aluminum/germanium bond to a second predetermined temperature that is less than 500° C. for a period not to exceed thirty minutes.
2. The method of claim 1 wherein the CMOS wafer and the MEMs wafer is cleaned before forming the eutectic bond.
3. The method of claim 2, wherein cleaning the CMOS wafer and the MEMS wafer comprises one or more of:
dipping the CMOS wafer and the MEMS wafer in deionized water;
dipping the CMOS wafer and the MEMS wafer in a 50:1 HF solution;
placing the CMOS wafer and the MEMS wafer in a dump rinse; and
placing the CMOS wafer and the MEMS wafer through a spin-rinse-dry process.
4. The method of claim 1, wherein the substantially aluminum metalization bonding layer on the CMOS wafer is a ratio mix of 97.5:2:.5 Al:Si:Cu (Aluminum:Silicon:Copper)
5. The method of claim 1, wherein forming a eutectic bond includes creating a hermetic seal between the CMOS wafer and the MEMS wafer.
6. The method of claim 1 wherein the first predetermined temperature is approximately 420° C.
7. The method of claim 1 wherein the second predetermined temperature is approximately 450° C.
8. The method of claim 1 wherein the MEMS layer is doped to provide an ohmic contact to the CMOS once the aluminum/germanium eutectic bond is formed.
9. The method of claim 1 wherein the forming gas is utilized to deoxidize the surfaces of the germanium layer and the aluminum layer to initiate the reflow process of aluminum/germanium eutectic bond.
10. The method of claim 1 wherein the germanium layer can be deposited on a MEMS substrate layer that is highly doped such that the resulting contact with the CMOS wafer is an ohmic contact.
Description
FIELD OF THE INVENTION

The present invention relates generally to wafer bonding and more particularly to a method and system of bonding in a wafer packaging environment.

RELATED APPLICATIONS

U.S. patent application Ser. No. 10/690,224, entitled “X-Y Axis Dual-Mass Tuning Fork Gyroscope with Vertically Integrated Electronics and Wafer-Scale Hermetic Packaging,” filed Oct. 20, 2003.

U.S. patent application Ser. No. 10/691,472, entitled “Method of Making an X-Y Axis Dual-Mass Tuning Fork Gyroscope with Vertically Integrated Electronics and Wafer-Scale Hermetic Packaging,” filed Oct. 20, 2003.

U.S. patent application Ser. No. 10/770,838, entitled “Vertically Integrated MEMS Structure,” filed Feb. 2, 2004.

U.S. patent application Ser. No. 10/771,135, entitled “Vertical Integration of a MEMS Structure with Electronics in a Hermetically Sealed Cavity,” filed Feb. 2, 2004.

BACKGROUND OF THE INVENTION

MEMS technology has been under steady development for some time, and as a result various MEMS devices have been considered and demonstrated for several applications. MEMS technology is an attractive approach for providing inertial sensors, such as accelerometers for measuring linear acceleration and gyroscopes for measuring angular velocity. A MEMS inertial sensor typically includes a proof mass which is flexibly attached to the rest of the device. Relative motion between the proof mass and the rest of the device is driven by actuators and/or sensed by sensors in various ways, depending on the detailed device design. Other MEMS applications include optical applications such as movable mirrors, and RF applications such as RF switches and resonators.

Since MEMS fabrication technology is typically based on processing planar silicon wafers, it is useful to classify MEMS devices according to whether the actuation and/or sensing performed in an inertial sensor (or other application) is in-plane or out of plane (i.e., vertical). More specifically, a device is “in-plane” if all of its sensing and/or actuation is in-plane, otherwise it is “vertical”. Thus MEMS devices are undergoing steady development, despite fabrication difficulties that tend to increase.

One approach which has been used to fabricate vertical MEMS devices is hybrid integration, where elements of a MEMS assembly are individually assembled to form the desired vertical structure. For example, attachment of a spacer to a substrate, followed by attachment of a deformable diaphragm to the spacer, provides a vertical MEMS structure having a spacing between diaphragm and substrate controlled by the spacer. U.S. Pat. No. 6,426,687 provides further information on this approach. Although hybrid integration can provide vertical MEMS devices, the cost tends to be high, since manual processing steps are usually required, and because hybrid integration is typically performed on single devices. Therefore, there is a need for reduced cost integrated MEMS devices that is unmet in the prior art.

CMOS compatible wafer-wafer bonding is very desirable for wafer-level-packaging. Its use has been demonstrated in a variety of different technologies. However, most of these processes have been limited to providing protection of a sensitive feature from post process handling, such as sawing, die bonding, testing, package, etc.

The need for a robust wafer level integration that can allow for simultaneous wafer-level-packaging and electrical interconnect is very high and can open up a multitude of new smaller, low-cost and feature rich MEMS products. The following describes conventional methods for bonding and their problems.

Organic or Adhesive Based Methods

Materials such as Benzocyclobutene (BCB), polyamide, photo resists, patternable RTV, and others have been spun on and used to form permanent bonds between wafers. These materials have disadvantages in that because they are organic, they tend to outgas and so are unsuitable for forming hermetic enclosures, and also they are susceptible to solvents, or moistures which can lead to problems with long term reliability and drift of a device's performance. Additionally, they are insulating materials and so are incapable of forming a conductive path between two substrates.

One popular method of making wafer-wafer bonding is by use of frit glass. Frit glass is typically screen printed on the cover wafers and reflowed to form a patterned glass interface for subsequent wafer-wafer bonding. Frit glass has a typical melting point near 500° C. and can be remelted post wafer-wafer aligned bond in a special temperature chamber with a controlled environment. The primary use of glass frit is to provide for the cover substrate and a hermetic sealed cavity for the MEMS. Frit glass technology has been utilized in the MEMS industry for many decades. Several major drawbacks are that frit glass does not provide for electrical interconnection between the MEMS and cover, to achieve a hermetic seal interface, minimum of 400 micron seal ring width is required which makes small MEMS devices, such as resonators and optical devices, much larger than otherwise. Also, frit glass screen printed is inherently a thick film process with tens of microns in thickness and several microns of nonuniformity.

Metal-Metal Bonding

CMOS compatible eutectic bonding has been demonstrated with indium-gold, solder-gold, gold-gold, etc. In order to bond a CMOS wafer, all of these prior art systems require the addition of non-standard layers, such as plating of lead, indium, gold, etc., to be added to the CMOS wafer. Although these processes are capable of creating hermetic seals and electrical interface, achieving fine features, small gaps and wafer uniformity is very challenging and will result in yield losses.

There are many MEMS device applications that require an electro-mechanical interface between the CMOS substrate and the MEMS substrates that are in micron gaps and require submicron uniformity. Most plating processes require under-layer barrier metallization with tens of microns thickness, and uniformity across the wafer is measured in microns. Hence it is not possible to specify one or two micron gap controls between the MEMS and CMOS substrates using this bonding methodology.

The ability to make high density and reliable electrical contacts between the MEMS and CMOS substrates can be very beneficial and provide for an all new generation of MEMS devices with much added functionality, smart electronics, smaller size, and lower cost. Finally, it is important to provide a lead free alloy based upon environmental considerations.

Accordingly, what is needed is a system and method for providing wafer bonding that overcomes the above-identified problems. The system and method should be easily implemented, cost effective and adaptable to existing bonding processes. The present invention addresses such a need.

SUMMARY OF THE INVENTION

A method of bonding two substrates to create a robust electrical and mechanical contact by using aluminum and germanium eutectic alloys is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as a standard foundry CMOS process; (5) this process is compatible with completely fabricated CMOS wafers as post process; (6) this process can provide for high density electrical interconnect; and (7) this process is highly controllable and provides for the smallest gap between two substrates. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart of a method for fabrication of a wafer level package in accordance with the present invention.

FIGS. 2A and 2B are cross sectional and top views of a first embodiment of an assembly in accordance with the present invention.

FIGS. 3A and 3B are cross sectional and top views of a second embodiment of an assembly in accordance with the present invention.

FIG. 4 illustrates an exemplary bonding profile to achieve a proper Al/Ge bond.

DETAILED DESCRIPTION

The present invention relates generally to wafer bonding and more particularly to a method and system of bonding utilizing aluminum and germanium in a wafer-level-packaging of MEMS devices with electrical substrate interconnect environment. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

FIG. 1 is a flow chart of a method of fabrication of a wafer level package in accordance with the present invention. The method comprises providing a MEMS structure including a substantially germanium top layer, via step 12, and providing a CMOS structure including a substantially aluminum top layer, via step 14. Finally, the method comprises bonding the top layer of the MEMS structure with the top layer of the CMOS structure, via step 16.

The following describes a preferred embodiment in accordance with the present invention. FIGS. 2A and 2B are cross sectional and top views of a first embodiment of an assembly 100 in accordance with the present invention. Referring to the embodiment shown in FIG. 2A, a standard foundry CMOS wafer 104 which includes aluminum is bonded to a MEMS substrate 102 which includes germanium to provide an aluminum/germanium (Al/Ge) bond 110. In this embodiment, a cavity 106 is within the substrate 104. The CMOS substrate wafer 104 can be any substrate with patterned aluminum shown in FIG. 2B that is designed to interface with the MEMS substrate 102 to make for a complete functioning product. In addition, a plurality of aluminum contacts 116 are on the top of the CMOS substrate 104 which are coupled to bond pads 105 by interconnect 107. Vias 107 are provided in both the bond pads 105 and the aluminum contacts 116 to allow for electrical connection thereto. As an example, the substrate 104 can comprise only a collection of metal layers and interconnects for providing for an electrical interconnection to the MEMS layers. Furthermore, the MEMS substrate 102 includes a MEMS feature 108 to complement the MEMS layers on the MEMS substrates 104, such as corresponding cavity 106. A gap control standoff 111 is provided to provide a precise separation of the MEMS substrate 102 from the CMOS substrate 104. The gap control standoff 111 provides a seal ring 112 for the device.

FIGS. 3A and 3B are cross sectional and top views of a second embodiment of an assembly in accordance with the present invention. The assembly 200 includes many of the same elements as assembly 100 of FIG. 2 and those elements have the same reference numerals. Additionally, the assembly 200 has via contacts 202 through the MEMS substrate 102′ and the gap control standoff 111′ to provide electric feedthrough of signals.

Another important feature of the substrate 104 is the availability of the multilayer metallization standard in CMOS foundries with chemical-mechanical-polishing of the oxide to make for a very planar metallized layer suitable for forming Al/Ge eutectic alloy with a germanium presence on the MEMS layer. The MEMS substrate 102 can be a silicon wafer or combination of silicon wafers assembled with all the MEMS features and functionalities including any type of preprocessed features.

In the preferred embodiment, the MEMS substrate on which the germanium has been patterned is a silicon substrate doped with boron to a conductivity of 0.006-0.02 Ωcm. This p+ doping forms an ohmic contact with the aluminum-germanium eutectic mix following the bond.

To describe the bonding layers in more detail refer now to the following.

Bonding Layers

In a preferred embodiment, the top metal layer of the foundry CMOS wafer is a ratio mix of 97.5:2:0.5 Al:Si:Cu and is 700 nm thick and is on a planarized oxide layer using CMP which is the standard processing step for most CMOS processes of 0.5 um or lower geometries. In a preferred embodiment, the bonding layers on the MEMS are 500 nm of germanium deposited in a standard vacuum sputter deposition system which is properly patterned to match the corresponding aluminum patterned for bonding.

Below is an example of the preferred embodiment of the equipment and process in accordance with the present invention.

Required Equipment

The bonding is performed in a commercially available wafer bonder such as that supplied by Electronic Visions Group, Inc., or Suss Microtec, Inc. The equipment should meet the following standards and have the following capabilities: (1) temperature control of both the top and the bottom chuck to nominally 450° C.; (2) ambient pressure control to sub-tor; (3) ambient gas control (via a purge line); (4) plumbed with 4-3-5 percent forming gas; and (5) the capability of applying a uniform force across the wafer pair of a minimum of 3000N.

In the preferred embodiment, the wafers are pre cleaned and then aligned prior to bonding in a compatible alignment tool.

Pre-Bond Cleaning

In the preferred embodiment, both the CMOS wafer and the MEMS wafer are cleaned prior to bonding. Both wafers are assumed to be free of any photoresist or other extraneous materials from previous processing steps. The wafers are cleaned by: (1) a 1.30 second dip in deionized water, (2) a 1.30 second dip in 50:1 HF; (3) a dump rinse; and (4) a standard spin-rinse-dry process.

Alignment

The bonding pair is aligned in an Electronic Visions 620 wafer-wafer aligner. Separation flags are inserted to maintain separation of the bonded pair prior to bonding.

Bonding

The aligned pair is transferred to an Electronic Visions 501 bonder. The purge line of this machine has been plumbed with forming gas. Following the cool down period of the bonding recipe, the bonding is complete and requires no further processing. An example of an exemplary bonding temperature profile for achieving the proper Al/Ge bond is shown in FIG. 4.

Description of Various and Alternate Embodiments

Alternative embodiments include, for example, (1) the utilization of different materials on top of the germanium to protect it during subsequent MEMS processing; (2) the employment of different pre-bond cleaning methods; (3) the bond may be performed unaligned; (4) the bond may be performed without patterning the aluminum and/or the germanium; (5) the CMOS wafer may be bonded without any additional processing other than the pre-bond clean; (6) the aluminum-germanium bond may be configured so as not to create a hermetic seal; (7) utilization of a substrate other than a MEMS wafer (such as a simple cover wafer); (8) the MEMS substrate may comprise something other than a gyroscope (such as a pressure sensor or accelerometer); (9) the aluminum of the standard CMOS wafer may comprise different formulations of standard aluminum (2% silicon, 2% silicon/1% copper, etc.)

In addition, (10) a specific temperature profile can be utilized; (11) a forming gas can be used to deoxidize the contact surfaces; (12) aluminum can be utilized as the standard metallization used for IC fabrication; (13) aluminum substrate can be kept below a predetermined temperature to prevent complete leaching of aluminum and germanium alloy from the oxide on the substrate; (14) the bonding can be performed using controlled ambient such as forming gas; (15) the bonding can be performed using low pressure bonding force or high pressure bonding force as assistance for/in order to assist in breaking of the aluminum oxide to initiate the interaction; (16) two wafers can be pre-aligned prior to bonding process; (17) a special cleaning solution can be utilized to clean the oxide from both surfaces; (18) the bonding surfaces can be cleaned by sputter etching; (19) a thin layer of TiW can be utilized to protect the bonding surface during MEMS processing; (20) including pre bond cleaning using plasma and/or other insitu cleaning techniques, in addition to a more concentrated forming gas and higher force bond; (21) the germanium can be deposited on a non-conductive layer (such as silicon dioxide) to create an insulating contact.

The germanium can be deposited on a semiconductor substrate that has been doped such that the resulting contact between the aluminum of the substrate and the MEMS is rectifying. This substrate can be a silicon substrate with n-type doping to 0.02-0.05 Ω-cm.

The germanium can be deposited on a semiconductor substrate that has been doped such that the resulting contact between the aluminum of the substrate and the MEMS is ohmic.

A method and structure of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum -germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as a standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5249732 *Feb 9, 1993Oct 5, 1993National Semiconductor Corp.Method of bonding semiconductor chips to a substrate
US5359893Dec 19, 1991Nov 1, 1994Motorola, Inc.Multi-axes gyroscope
US5367194Apr 23, 1992Nov 22, 1994Hewlett-Packard CompanyMicrochip assembly with electrical element in sealed cavity
US5485032 *Dec 8, 1994Jan 16, 1996International Business Machines CorporationAntifuse element with electrical or optical programming
US5656778Apr 24, 1995Aug 12, 1997Kearfott Guidance And Navigation CorporationFor measuring linear and angular motion
US5659195Jun 8, 1995Aug 19, 1997The Regents Of The University Of CaliforniaCMOS integrated microsensor with a precision measurement circuit
US5693574 *Feb 4, 1994Dec 2, 1997Deutsche Aerospace AgApplying a layer of aluminum to front side of each of silicon semiconductor slices, applying germenium layer on to of first layer, stacking slices, alloying the both layers in presecne of heat and pressure
US5895850Apr 11, 1995Apr 20, 1999Robert Bosch GmbhMicromechanical resonator of a vibration gyrometer
US5915168May 6, 1998Jun 22, 1999Harris CorporationMethod for packaging individual die at the wafer level
US5992233May 31, 1996Nov 30, 1999The Regents Of The University Of CaliforniaMicromachined Z-axis vibratory rate gyroscope
US6036872Mar 31, 1998Mar 14, 2000Honeywell Inc.Method for making a wafer-pair having sealed chambers
US6122961Sep 2, 1997Sep 26, 2000Analog Devices, Inc.Micromachined gyros
US6128961Dec 24, 1996Oct 10, 2000Haronian; DanMicro-electro-mechanics systems (MEMS)
US6153917Mar 16, 1999Nov 28, 2000Akebono Brake Industry Co., Ltd.Semiconductor acceleration sensor and manufacturing method thereof
US6189381Apr 26, 1999Feb 20, 2001Sitek, Inc.Angular rate sensor made from a structural wafer of single crystal silicon
US6199748Aug 20, 1999Mar 13, 2001Nova Crystals, Inc.Semiconductor eutectic alloy metal (SEAM) technology for fabrication of compliant composite substrates and integration of materials
US6229190Dec 18, 1998May 8, 2001Maxim Integrated Products, Inc.Compensated semiconductor pressure sensor
US6250157Jun 22, 1999Jun 26, 2001Aisin Seiki Kabushiki KaishaAngular rate sensor
US6391673Nov 1, 2000May 21, 2002Samsung Electronics Co., Ltd.Method of fabricating micro electro mechanical system structure which can be vacuum-packed at wafer level
US6426687May 22, 2001Jul 30, 2002The Aerospace CorporationRF MEMS switch
US6430998Nov 30, 2000Aug 13, 2002Murata Manufacturing Co., Ltd.Resonant element
US6433411May 22, 2000Aug 13, 2002Agere Systems Guardian Corp.Packaging micromechanical devices
US6448109Nov 15, 2000Sep 10, 2002Analog Devices, Inc.Wafer level method of capping multiple MEMS elements
US6452238Sep 27, 2000Sep 17, 2002Texas Instruments IncorporatedMEMS wafer level package
US6479320Feb 2, 2000Nov 12, 2002Raytheon CompanyVacuum package fabrication of microelectromechanical system devices with integrated circuit components
US6480320Feb 7, 2001Nov 12, 2002Transparent Optical, Inc.Microelectromechanical mirror and mirror array
US6481283Apr 4, 2000Nov 19, 2002Milli Sensor Systems & Actuators, Inc.Coriolis oscillating gyroscopic instrument
US6481284Dec 17, 2001Nov 19, 2002Analog Devices, Inc.Micromachined devices with anti-levitation devices
US6481285Apr 20, 2000Nov 19, 2002Andrei M. ShkelMicro-machined angle-measuring gyroscope
US6487908Dec 17, 2001Dec 3, 2002Analog Devices, Inc.Micromachined devices with stop members
US6508122Sep 15, 2000Jan 21, 2003American Gnc CorporationMicroelectromechanical system for measuring angular rate
US6513380Jun 19, 2001Feb 4, 2003Microsensors, Inc.MEMS sensor with single central anchor and motion-limiting connection geometry
US6519075Jan 25, 2001Feb 11, 2003Agere Systems Inc.Packaged MEMS device and method for making the same
US6528344Jun 22, 2001Mar 4, 2003Samsung Electronics Co., Ltd.Chip scale surface-mountable packaging method for electronic and MEMS devices
US6528887Mar 1, 2001Mar 4, 2003Onix MicrosystemsConductive equipotential landing pads formed on the underside of a MEMS device
US6533947Jun 27, 2001Mar 18, 2003Transparent Optical, Inc.Microelectromechanical mirror and mirror array
US6555417Dec 5, 2001Apr 29, 2003Analog Devices, Inc.Method and device for protecting micro electromechanical system structures during dicing of a wafer
US6559530Sep 19, 2001May 6, 2003Raytheon CompanyMethod of integrating MEMS device with low-resistivity silicon substrates
US6621137Oct 12, 2000Sep 16, 2003Intel CorporationMEMS device integrated chip package, and method of making same
US6635509Apr 12, 2002Oct 21, 2003Dalsa Semiconductor Inc.Wafer-level MEMS packaging
US6650455Nov 13, 2001Nov 18, 2003Iridigm Display CorporationPhotonic mems and structures
US6660564Jan 25, 2002Dec 9, 2003Sony CorporationWafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
US6686639Sep 30, 2002Feb 3, 2004Innovative Technology Licensing, LlcHigh performance MEMS device fabricatable with high yield
US6770569Aug 1, 2002Aug 3, 2004Freescale Semiconductor, Inc.Low temperature plasma Si or SiGe for MEMS applications
US6794272Mar 18, 2003Sep 21, 2004Ifire Technologies, Inc.Wafer thinning using magnetic mirror plasma
US6796178Feb 6, 2003Sep 28, 2004Samsung Electronics Co., Ltd.Rotation-type decoupled MEMS gyroscope
US6808955Nov 2, 2001Oct 26, 2004Intel CorporationMethod of fabricating an integrated circuit that seals a MEMS device within a cavity
US6852926Mar 26, 2002Feb 8, 2005Intel CorporationPackaging microelectromechanical structures
US6936491Jun 4, 2003Aug 30, 2005Robert Bosch GmbhMethod of fabricating microelectromechanical systems and devices having trench isolated contacts
US6936494Oct 22, 2003Aug 30, 2005Rutgers, The State University Of New JerseyProcesses for hermetically packaging wafer level microscopic structures
US6939473 *Oct 20, 2003Sep 6, 2005Invensense Inc.Method of making an X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging
US7104129Feb 2, 2004Sep 12, 2006Invensense Inc.Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US20030074967Dec 3, 2002Apr 24, 2003California Institute Of TechnologyMicrogyroscope with integrated vibratory element
US20030110858Nov 14, 2002Jun 19, 2003Samsung Electronics Co., Ltd.MEMS gyroscope having mass vibrating vertically on substrate
US20030164041Feb 6, 2003Sep 4, 2003Samsung Electronics Co., Ltd.Rotation-type decoupled MEMS gyroscope
US20040055380Aug 12, 2003Mar 25, 2004Shcheglov Kirill V.Isolated planar gyroscope with internal radial sensing and actuation
US20050170656Feb 2, 2004Aug 4, 2005Nasiri Steven S.Vertical integration of a MEMS structure with electronics in a hermetically sealed cavity
Non-Patent Citations
Reference
1Vu, Bao et al., Patterned eutectic bonding with Al/Ge thin films for microelectromechanical systems, May 31, 1996, 2588-2594.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7943411May 4, 2009May 17, 2011Analog Devices, Inc.Apparatus and method of wafer bonding using compatible alloy
US7981765May 4, 2009Jul 19, 2011Analog Devices, Inc.Substrate bonding with bonding material having rare earth metal
US8044736Apr 29, 2008Oct 25, 2011Sand9, Inc.Timing oscillators and related methods
US8044737Apr 29, 2008Oct 25, 2011Sand9, Inc.Timing oscillators and related methods
US8089144Dec 10, 2009Jan 3, 2012Denso CorporationSemiconductor device and method for manufacturing the same
US8169082Nov 2, 2011May 1, 2012Denso CorporationSemiconductor device and method for manufacturing the same
US8288191 *Apr 8, 2011Oct 16, 2012Analog Devices, Inc.Apparatus and method of wafer bonding using compatible alloy
US8293124 *Mar 4, 2008Oct 23, 2012Samsung Electronics Co., Ltd.Method of multi-stage substrate etching and terahertz oscillator manufactured using the same method
US8357560 *May 18, 2009Jan 22, 2013Magnachip Semiconductor Ltd.Package of MEMS device and method for fabricating the same
US8378490 *Mar 15, 2011Feb 19, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor apparatus including a metal alloy between a first contact and a second contact
US8410868May 17, 2010Apr 2, 2013Sand 9, Inc.Methods and apparatus for temperature control of devices and mechanical resonating structures
US8466606Oct 6, 2010Jun 18, 2013Sand 9, Inc.Integration of piezoelectric materials with substrates
US8476809May 8, 2012Jul 2, 2013Sand 9, Inc.Microelectromechanical systems (MEMS) resonators and related apparatus and methods
US8485416Jan 5, 2012Jul 16, 2013Silex Microsystems AbBonding process and bonded structures
US8507913Sep 29, 2010Aug 13, 2013Analog Devices, Inc.Method of bonding wafers
US8587183Nov 20, 2012Nov 19, 2013Sand 9, Inc.Microelectromechanical systems (MEMS) resonators and related apparatus and methods
US8592285Dec 11, 2009Nov 26, 2013Pioneer CorporationMethod of bonding semiconductor substrate and MEMS device
US8647962Mar 23, 2010Feb 11, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Wafer level packaging bond
US8648468Jul 29, 2010Feb 11, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Hermetic wafer level packaging
US8698376Nov 20, 2012Apr 15, 2014Sand 9, Inc.Microelectromechanical systems (MEMS) resonators and related apparatus and methods
US8710597 *Apr 19, 2011Apr 29, 2014MCube Inc.Method and structure for adding mass with stress isolation to MEMS structures
US8729685Apr 30, 2010May 20, 2014Silex Microsystems AbBonding process and bonded structures
US8741738 *Jun 8, 2011Jun 3, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method of fabrication of a semiconductor apparatus comprising substrates including Al/Ge and Cu contact layers to form a metallic alloy
US8766512Mar 31, 2010Jul 1, 2014Sand 9, Inc.Integration of piezoelectric materials with substrates
US20110212563 *Apr 8, 2011Sep 1, 2011Analog Devices, Inc.Apparatus and Method of Wafer Bonding Using Compatible Alloy
US20120086126 *Oct 8, 2010Apr 12, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Package systems and manufacturing methods thereof
US20120235301 *Mar 15, 2011Sep 20, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor apparatus
US20120313246 *Jun 8, 2011Dec 13, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor apparatus
US20130161820 *Dec 19, 2012Jun 27, 2013Julian GonskaMethod for bonding two silicon substrates, and a correspondeing system of two silicon substrates
DE102011089569A1Dec 22, 2011Jun 27, 2013Robert Bosch GmbhVerfahren zum Verbinden zweier Siliziumsubstrate und entsprechende Anordnung zweier Siliziumsubstrate
Classifications
U.S. Classification438/48, 438/455, 438/51, 438/118
International ClassificationH01L21/00
Cooperative ClassificationB81C1/00238, B81C1/00269, B81B3/0018, B81C2203/035, B81C2203/038, B81C3/001, B81C2203/0118
European ClassificationB81C1/00C12D
Legal Events
DateCodeEventDescription
Apr 27, 2012FPAYFee payment
Year of fee payment: 4
Jan 25, 2011CCCertificate of correction
Mar 18, 2005ASAssignment
Owner name: INVENSENSE INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NASIRI, STEVEN S.;FLANNERY, ANTHONY FRANCIS, JR.;REEL/FRAME:016401/0004
Effective date: 20050318