US 7446686 B2 Abstract A method of operating a delta-sigma data converter includes receiving an input signal at an input of a delta-sigma modulator having a loop filter including a plurality of integrator stages, a quantizer for generating a quantized output code from outputs of the integrator stages, and a feed-back loop coupling a feed-back signal from the output of the quantizer to the input of the delta-sigma modulator. The input signal is converted to quantized output codes during a conversion period including a plurality of integrator cycles in which at least one of the integrator stages is held in reset for at least one integration cycle at the start of the conversion period to maintain stability of the modulator over a wider range of levels of the input signal.
Claims(20) 1. A method of operating a delta-sigma data converter comprising:
receiving an input signal at an input of a delta-sigma modulator having a loop filter including a plurality of integrator stages, a quantizer for generating a quantized output code from outputs of the integrator stages, and a feed-back loop coupling a feed-back signal from the output of the quantizer to the input of the delta-sigma modulator; and
converting the input signal to quantized output codes during a conversion period including a plurality of integrator cycles comprising:
holding each of the plurality of the integrator stages in reset for at least one integration cycle at the start of the conversion period to maintain stability of the modulator over a wider range of levels of the input signal; and
sequentially releasing each of the plurality of integrator stages from reset over a selected number of integration cycles to sequentially increase the order of the delta-sigma modulator at the start of the conversion period.
2. The method of
3. The method of
4. The method of
5. The method of
6. A method of operating a delta-sigma data converter comprising:
receiving an input signal at an input of a delta-sigma modulator having a loop filter including a plurality of integrator stages, a quantizer for generating a quantized output code from outputs of the integrator stages, and a feed-back loop coupling a feed-back signal from the output of the quantizer to the input of the delta-sigma modulator; and
converting the input signal to quantized output codes during a conversion period including a plurality of integrator cycles comprising:
holding at least a first one of the integrator stages in reset for at least one integration cycle at the start of the conversion period to maintain stability of the modulator over a wider range of levels of the input signal; and
feeding-forward a signal directly from the input of the delta-sigma modulator to the quantizer to generate the feed-back signal while the first one of the integrator stages is in reset.
7. The method of
8. The method of
9. A delta-sigma data converter comprising:
an input for receiving an input signal;
a loop filter including a plurality of integrator stages;
a quantizer for generating a quantized output code from outputs of the integrator stages;
a feed-back loop coupling a feed-back signal from the output of the quantizer to the input of the delta-sigma modulator; and
timing and control circuitry for converting the input signal to quantized output codes during a conversion period including a plurality of integrator cycles, wherein the timing and control circuitry:
holds each of the integrator stages in reset for at least one integration cycle at the start of the conversion period to maintain stability of the modulator over a wider range of levels of the input signal; and
sequentially releases each of the integrator stages from reset over a selected number of integration cycles to sequentially increase the order of the delta-sigma modulator at the start of the conversion period.
10. The delta-sigma data converter of
11. The delta-sigma data converter of
12. The delta-sigma data converter of
13. The delta-sigma data converter of
14. The delta-sigma data converter of
15. A delta-sigma data converter comprising:
an input for receiving an input signal;
a loop filter including a plurality of integrator stages;
a quantizer for generating a quantized output code from outputs of the integrator stages;
a feed-back loop coupling a feed-back signal from the output of the quantizer to the input of the delta-sigma modulator;
timing and control circuitry for converting the input signal to quantized output codes during a conversion period including a plurality of integrator cycles, wherein the timing and control circuit holds at least one of the integrator stages in reset for at least one integration cycle at the start of the conversion period to maintain stability of the modulator over a wider range of levels of the input signal; and
a direct feed-forward path from the input of the delta-sigma modulator to the quantizer for generating the feed-back signal with the quantizer when a first one of the integrator stages is in reset.
16. The delta-sigma data converter of
17. An incremental analog to digital converter comprising:
a feed-forward delta-sigma modulator including an input summer for summing an analog input signal with a feed-back signal, a loop filter including a plurality of integrators, a quantizer for quantizing a weighted sum of outputs of each of the integrator stages, and a feed-back loop including a digital to analog converter for providing the feed-back signal from the quantizer to the input summer;
control circuitry for controlling conversion by the delta-sigma modulator of the analog input signal into a plurality of quantized output codes during a sequence of integration cycles defining each of a plurality of conversion periods, wherein the control circuitry maintains stability of the modulator by holding in reset at least one of the integrator stages during a selected number of integration cycles at the start of each conversion period; and
accumulator circuitry for accumulating at least some of the output codes generated by the delta-sigma modulator during each conversion period to generate a digital output word.
18. The incremental analog to digital converter of
19. The incremental analog to digital converter of
20. The incremental analog to digital converter of
Description The present invention relates in general to delta-sigma data converters techniques, and in particular, to incremental delta-sigma data converters with improved stability over wide input voltage ranges. Delta-sigma modulators are particularly useful in digital to analog and analog to digital converters (DACs and ADCs). Using oversampling, the delta-sigma modulator spreads the quantization noise power across the oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, a low-pass delta-sigma modulator performs noise shaping by acting as a lowpass filter to the input signal and a highpass filter to the noise; most of the quantization noise power is thereby shifted out of the signal band. The typical delta-sigma modulator ADC includes a summer that sums the input signal with negative feed-back, a linear filter, a quantizer, and a feed-back loop with a digital to analog converter coupling the quantizer output and an inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in a higher order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer. Higher-order modulators have improved quantization noise transfer characteristics over those of a lower order, but stability becomes a more critical design factor as the order increases. In particular, higher order delta-sigma modulators implement multiple sets of poles and zeros that advantageously provide for improved noise shaping and consequently an increased signal to noise ratio (SNR) in the signal base band. However, high order delta-sigma modulators with aggressive noise transfer functions (NTF's) (i.e. NTF's that provide high out-of-band gain) are also subject to instability for large input signals. Generally, in order to avoid instability with higher order delta-sigma modulators, it becomes important to maintain the input voltage range within given limits in order to ensure that the loop filter integrator stages do not saturate and/or that the quantizer does not overload. Additionally, stability can be ensured by decreasing the out-of-band gain of the NTF. Disadvantageously, reducing the input voltage range limits the dynamic range of the delta-sigma modulator, while reducing the NTF out-of-band gain reduces the SNR. In sum, new techniques are desirable for designing and constructing high order delta-sigma modulators having NTF's with high out-of-band gain and a maximum dynamic input voltage range. The principles of the present invention are embodied in incremental delta-sigma data conversion techniques that provide modulator stability over a wider input voltage range. According to one representative embodiment, a method of operating a delta-sigma data converter is disclosed that includes receiving an input signal at an input of a delta-sigma modulator having a loop filter including a plurality of integrator stages, a quantizer for generating a quantized output code from outputs of the integrator stages, and a feed-back loop coupling feed-back from the output of the quantizer to the input of the delta-sigma modulator. The input signal is converted to quantized output codes during a conversion period including a plurality of integrator cycles in which at least one of the integrator stages is held in reset for at least one integration cycle at the start of the conversion period to maintain stability of the modulator over a wider range of levels of the input signal. Embodiments of the present principles advantageously allow a delta-sigma data converter to operate in an incremental conversion mode while remaining stable over a wider range of input voltages. In one exemplary technique, the integrator stages of a delta-sigma converter are sequentially released from reset at the start of each conversion cycle to sequentially increase the order of the modulator. As a result, the delta-sigma modulator is maintained in stability while a full aggressive noise transfer function is gradually implemented. In another technique, all the integrator stages of a delta-sigma converter are initially held in reset for at least one integration period at the start of each conversion period. While the integrator stages are in reset, a feed-forward stage ensures that feedback is generated through the converter quantizer and feedback loop, such that the first integrator stage in the cascade remains stable when all the integrator stages are simultaneously released from reset to begin noise shaping. For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in The digital output from ADC Oscillator/clock generator block The chip select pin cs\ allows an external device to access the SDO port. In particular, when the cs\ input is set to an inactive high state, the SDO output is held in a high impedance output state. The ready (RDY\) input operates in conjunction with the convert (CONV\) input pin to microcontroller The SLEEP\ input to calibration microcontroller Delta-sigma modulator In incremental delta-sigma modulator In the illustrated embodiment, each integration cycle is composed of the two-phases, φ One advantage of incremental delta-sigma modulator Additionally, incremental delta-sigma modulator However, with higher order incremental delta-sigma modulators, particularly those having aggressive NTFs, instability can result when a high level input signal is present at reset before the start of each new conversion period. Specifically, at reset, the input to the delta-sigma modulator is subjected to a full-scale step input with a full scale input signal. For a conventional incremental delta-sigma modulator, the feed-back to the input summer is necessarily zero at the start of each new conversion period, due to reset of the quantizer and feedback DAC at the end of the previous conversion period. For high values of the input signal, and with the feed-back being zero, the signal appearing at the summing nodes of the first integrator stage can approach one half (˝) the full scale input value during the first integration cycle, thereby driving the first integrator stage into saturation. In turn, the following integrator stages and the quantizer can overload, such that the entire delta-sigma loop becomes unstable. In conventional delta-sigma modulators, the entire delta-sigma modulator must typically be reset to return the delta-sigma loop to a stable state. Switched capacitor integrator In the general case, switches During Phase φ In the illustrated embodiment, control signals Dx and /Dx are set in the short period between the end of Phase φ During incremental conversions, at the end of each integration cycle, integration capacitors In particular, at time t After i number of integration cycles (i.e. MCLK signal periods), in which i is an integer, second integrator stage The analog input signal continues to be sampled and converted until the desired number of integration cycles have been completed at time t In sum, the principles of the present invention allow a delta-sigma converter to operate in an incremental conversion mode and remain stable over a wider range of input voltages. In one technique, the integrator stages of an incremental delta-sigma converter are sequentially released from reset at the start of each conversion cycle to sequentially increase the order of the modulator. As a result, the delta-sigma modulator remains stable while a full aggressive NTF is gradually implemented. In a second technique, all integrators are initially held in reset for at least one integration period at the start of each conversion period. While the integrator stages are in reset, a feedforward stage ensures that feedback is generated through the delta-sigma modulator quantizer and feedback loop, such that the first integrator in the cascade remains stable when all the integrator stages are simultaneously released from reset such that noise shaping can begin. Although the invention has been described with reference to specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed might be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. It is therefore contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention. Patent Citations
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