|Publication number||US7454632 B2|
|Application number||US 11/153,950|
|Publication date||Nov 18, 2008|
|Filing date||Jun 16, 2005|
|Priority date||Jun 16, 2005|
|Also published as||CN101198923A, CN101198923B, EP1891500A2, EP1891500B1, US20060288240, WO2006138687A2, WO2006138687A3|
|Publication number||11153950, 153950, US 7454632 B2, US 7454632B2, US-B2-7454632, US7454632 B2, US7454632B2|
|Inventors||James P Kardach, David L Williams, Animesh Mishra|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Non-Patent Citations (2), Referenced by (65), Classifications (19), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
Certain embodiments of the present invention generally relate to power management. In particular, some embodiments relate to synchronizing the idleness of system devices with the idleness of a system processor based on an operating system schedule.
The popularity of computing systems continues to grow and the demand for more functionality has reached new heights. As a result, modern workloads and computing systems can consume more power and generate more heat than previously experienced. Modern platform power management techniques use drivers to emulate hardware timers, where when a timer expires the respective device has been idle for a predetermined amount of time and is turned off to conserve power. While such an approach can be acceptable at coarse levels of granularity, there may be lost power saving opportunities at relatively fine levels of granularity.
The various advantages of the embodiments of the present invention will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention. It will be evident, however, to one skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other instances, specific apparatus structures and methods have not been described so as not to obscure the embodiments of the present invention. The following description and drawings are illustrative of the embodiments of the invention and are not to be construed as limiting the embodiments of the invention.
Some portions of the detailed description, which follow, are presented in terms of algorithms and symbolic representations of operations on data bits or binary digital signals within a computer memory. These algorithmic descriptions and representations may be the techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art.
Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices. Furthermore, the use of the terms “first”, “second”, etc. do not necessarily infer a chronological relationship, and are used to facilitate discussion only. In addition, the term “coupled” may be used to refer to any arrangement, whether direct or indirect, in which the components in question have a mechanical, electrical, optical, electromagnetic or other relationship.
The illustrated apparatus 10 also includes synchronization logic 22 to synchronize the idleness of the processor 14 with the idleness of one or more devices 24. The devices 24 may be system buses, memory devices, clock sources, controllers, etc. By creating such a platform-wide idleness scheme, the apparatus 10 can be more aggressive in power saving. In addition, conducting the synchronization based on the OS schedule 16, which has a relatively high level of granularity, the apparatus 10 is able to achieve greater stability and much more resolution over power management activities.
As already noted, the OS schedule 16 can be used to force the processor 14 into and out of an idle state on a relatively fine level of granularity. For example, the OS schedule 16 could be implemented as a periodic interrupt that is generated by a timer and is programmed to a value such as 10-15 ms. If the illustrated processor 14 is in an idle state such as one of the Advanced Configuration and Power Interface (e.g., ACPI Specification, Rev. 3.0, Sep. 2, 2003) C1-C3 states, it is inactive and consumes a relatively low amount of power. When the OS schedule timer counts down, the timer can generate an interrupt to the processor 14, where the interrupt may awaken the processor 14 into an active/executing state. In ACPI, the active state is referred to as the C0 state. Upon awakening, the illustrated processor 14 begins to execute a workload scheduled by the OS. When the workload is complete, the processor 14 can return to one of the idle states until the next OS schedule timer interrupt is detected. Thus, the power management logic 12 is able to detect an event such as an OS schedule timer interrupt, place the processor 14 in an active state in response to the event, and remove the processor 14 from the active state if the processor is ready to enter an idle state. This process can be repeated on a periodic basis according to the OS schedule 16.
Turning now to
For example, in the illustrated embodiment, the preventing includes deferring bus transactions, deferring interrupts, suspending memory refresh, turning off power to clock sources and turning off power to system/controller combinatorial logic until the next AW. Combinatorial logic elements generally have at least one output channel and one or more input channels, all characterized by discrete states. Thus, at any instant the state of each output channel can be completely determined by the states of the input channels at the same instant. By selectively powering such logic on and off, substantial power savings can be achieved. In the resulting scheme, all devices can work together and sleep together.
It can also be seen that, depending upon the device, an idleness exit procedure may be initiated during an exit period 34 (34 a-34 c) near the end of the IW 30. For example, the memory controller may run an exit suspend refresh routine during exit period 34 a in order to prepare the memory for the next AW 28. Similarly, a phase locked loop (PLL) warm-up routine may be executed during exit period 34 b for any PLLs that have been turned off. In the illustrated example, a power up routine is also conducted during exit period 34 c for any combinatorial logic that may have been turned off during the IW 30. Because the length of the IW 30 may be linked to the OS 16, and is therefore known, the idleness exit procedures can be conducted without delaying the next AW 28.
Turning now to
The illustrated pre-timing logic 36 latches the running count value 44 into a plurality of compare modules 46 that compare the running count value 44 to the appropriate exit period value. As the exit period values are reached, the necessary signaling (e.g., TPA#, TSR#, TPLL#) can be generated by flip-flops 48, which also use the timer clock input 40, to initiate the corresponding idleness exit procedures. The schedule timer 38 and the pre-timing logic 36 may be centrally located or distributed throughout the platform, depending upon the circumstances.
In the illustrated example, the GMCH 52 includes a clock controller 41 that receives a timer clock signal from a timer clock 43. The ICH 54 may include power management logic 12, which can use schedule timer 38 (38 a, 38 b) circuitry to control the idleness of the processor 14 based on an OS schedule and the timer clock signal. Idleness synchronization logic (ISL) 22 (22 a-22 g) can be distributed throughout the system 50, wherein the ISL 22 is able to synchronize the idleness of one or more devices with the idleness of the processor 14 in accordance with an OS schedule-based idle policy 62. In one example, the idle policy 62 can enforce idle window rules, where the ISL 22 manages device participation with respect to these rules. For example, a processor interface module 60 could include ISL 22 a, where the ISL 22 a may synchronize the idleness of the high speed bus 102 with the idleness of the processor 14. In particular, the ISL 22 a could permit transactions on the bus 102 during active windows in the OS schedule and defer transactions on the bus 102 during idle windows in the OS schedule until the next active window. Similarly, hub interface modules 64, 66 can include ISLs 22 d, 22 e, respectively, where the ISLs 22 d, 22 e can defer transactions on the hub bus 108 during idle windows in the OS schedule. Deferring bus transactions during the idle windows can provide significant power savings.
In addition, a memory controller 68 may include ISL 22 c, which supports activities in the DRAM 104 such as read/write accesses and self refresh during the active window. The ISL 22 c can suspend these activities during the idle windows. For example, it has been determined that suspending memory refresh in the DRAM 104 may conserve a substantial amount of power. Also in the illustrated example, I/O controllers 70, 72 include ISLs 22 f, 22 g, respectively, for turning off power to power to combinatorial logic (not shown) in the controllers 70, 72 during the idle windows. As already noted, by selectively powering combinatorial logic on and off, substantial power savings can be achieved. Furthermore, a graphics (Gfx) module 58 could include ISL 22 b, where the ISL 22 b may synchronize the idleness of the Gfx module 58 with the idleness of the processor 14 to create a more ordered environment. In yet another example, clock logic (not shown) can selectively turn off power to various clock sources to synchronize their idleness with the idleness of the processor 14.
The illustrated system 50 also includes pre-timing logic 36 (36 a, 36 b) circuitry to manage the exiting of the various devices from their respective sleep states during the idle windows. By initiating the appropriate idleness exit procedures, the pre-timing logic 36 can substantially obviate idleness-related latency. The result can be a highly deterministic solution that provides for unique power saving opportunities.
One key to enabling this sort of platform behavior could involve changing the way active block I/O devices (e.g., bus masters) operate. Conventional bus masters operate anytime, which may lead to the system-level power management problems currently experienced. In one approach, these devices may only be allowed to operate during active windows. The behavior of many bus controllers and some devices may have to comply with the idle policy 62 in order to create a highly ordered behavior. Such a result could be difficult to obtain as many of these devices were designed to not operate in this fashion. This compliance requirement, however, can be simplified by observing the system behavior as a whole.
It may be observed first that the system 50 is mostly idle, and when executing a moderate workload is also idle (e.g., doing nothing). If the system 50 is idle 90% of the time, and (in general) devices are doing nothing when idle, it may be easier to force block I/O devices to behave in this manner when idle. Roughly 90% of the benefit may be achievable while avoiding 90% of the difficulties associated with block I/O device behavior if idleness synchronization is only used to enhance the behavior of idle systems.
To elaborate further, much of the performance of block I/O devices is derived for when the device is very busy (e.g., executing ISOSYNCH data streams). Much of the optimization for these active workloads could compromise performance in the idle state because it may not be known when this behavior is needed. If we can identify when the system is idle and then change the behavior of these devices to obtain fine grain power control, then it may be easier to change these devices without radically affecting their system behavior. For example, the system 50 could be switched into an active “mode” when it is determined that the system 50 is active (upon an OS schedule interval). Here good idle performance behavior can be obtained while maintaining the legacy active behavior with a minor impact to performance. Such an approach may require that the idle policy 62 dynamically determine when the system is active or idle and then switch the platform into a normal or idle behavior. Simply put, the ISL 22/idle policy 62 may selectively synchronize the idleness of each of the devices with the idleness of the processor 14 based on the overall idleness of the system 50.
Turning now to
The machine-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disk Read Only Memory (CD-ROM), Compact Disk Recordable (CD-R), Compact Disk Rewriteable (CD-RW), optical disk, magnetic media, various types of Digital Versatile Disks (DVDs), a tape, a cassette, or the like. The instructions may include any suitable type of code, for example, source code, compiled code, interpreted code, executable code, static code, dynamic code, or the like, and may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, e.g., C, C++, Java, BASIC, Pascal, Fortran, Cobol, assembly language, machine code, or the like.
In the illustrated example, processing block 76 provides for controlling an idleness of a processor based on an OS schedule. Such a process may involve, for example, detecting an OS schedule event, placing the processor in an active state in response to the event, removing the processor from the active state if the processor is ready to enter an idle state, and repeating the detecting, placing and removing on a periodic basis according to the OS schedule. Block 78 provides for synchronizing the idleness of at least one device with the idleness of the processor. In one example, such a process can include permitting an activity of the device during an active window in the OS schedule and preventing the activity during an idle window in the OS schedule.
Those skilled in the art can appreciate from the foregoing description that the broad techniques of the embodiments of the present invention can be implemented in a variety of forms. Therefore, while the embodiments of this invention have been described in connection with particular examples thereof, the true scope of the embodiments of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.
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|U.S. Classification||713/300, 713/320, 713/323|
|International Classification||G06F1/00, G06F1/32|
|Cooperative Classification||G06F1/3228, G06F1/3237, G06F1/3253, G06F1/3275, G06F1/3287, Y02B60/1282, Y02B60/1235, Y02B60/1221, Y02B60/1228|
|European Classification||G06F1/32P1D, G06F1/32P5P8, G06F1/32P5S, G06F1/32P5P1, G06F1/32P5C|
|Jun 16, 2005||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KARDACH, JAMES P.;WILLIAMS, DAVID L.;MISHRA, ANIMESH;REEL/FRAME:016703/0030;SIGNING DATES FROM 20050609 TO 20050614
|May 9, 2012||FPAY||Fee payment|
Year of fee payment: 4
|May 5, 2016||FPAY||Fee payment|
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