|Publication number||US7457487 B2|
|Application number||US 11/524,530|
|Publication date||Nov 25, 2008|
|Filing date||Sep 19, 2006|
|Priority date||Dec 9, 2004|
|Also published as||US20080232735|
|Publication number||11524530, 524530, US 7457487 B2, US 7457487B2, US-B2-7457487, US7457487 B2, US7457487B2|
|Inventors||David A. B. Miller, Yu-Hsuan Kuo, James S. Harris, Jr.|
|Original Assignee||The Board Of Trustees Of The Leland Stanford Junior University|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (1), Referenced by (9), Classifications (42), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of U.S. provisional application 60/718,429, filed on Sep. 19, 2005, entitled “Surface Parallel Modulator”, and hereby incorporated by reference in its entirety. This application is also a continuation in part of U.S. application Ser. No. 11/230,285, filed on Sep. 19, 2005. U.S. application Ser. No. 11/230,285 claims the benefit of U.S. provisional application 60/635,093, filed on Dec. 9, 2004.
This invention was made with Government support under grant number W911NF-05-1-0251 (PTA number 194674-601-TBABC) from DARPA/Army Research Office. The Government has certain rights in this invention.
This invention relates to semiconductor quantum well structures.
Although silicon is the dominant material technology for most electronics applications, there are significant applications for which conventional silicon technology is unsuitable. For example, optoelectronic devices (e.g., sources, modulators and detectors) are typically fabricated in compound semiconductor material systems having more favorable optoelectronic properties than silicon. However, it is difficult to monolithically integrate silicon electronics with compound semiconductor optoelectronic devices, as desired for many applications. Accordingly, various approaches for providing Si-compatible optoelectronic devices have been under development for some time. An article entitled “Silicon-based group IV heterostructures for optoelectronic applications” by Richard A. Soref and published in the Journal of Vacuum Science and Technology, pp 913-918, May/June 1996, provides a review of some of these approaches.
The use of the Si/SiGe/Ge material system is one approach under consideration for Si-compatible optoelectronics. However, the lattice mismatch of about 4% between Si and Ge is a significant complication for epitaxial growth of Ge (or Ge-rich SiGe) on silicon. A conventional approach for managing the lattice mismatch is to grow a buffer layer having a graded composition on a Si substrate, e.g., as considered in U.S. Pat. No. 6,784,466. The buffer layer composition is increasingly Ge rich as the distance from the substrate increases. In this manner, the strain introduced by the lattice mismatch can be accommodated in the buffer layer. However, this fabrication approach is disadvantageous, because the graded buffer layer may need to be relatively thick (e.g., 5-10 microns or so) which is costly, and because the resulting device chips are often mechanically fragile. It also results in a surface that is too rough for the growth of uniform, thin Ge or Ge-rich SiGe layers on thick graded buffer layers. This is commonly overcome by performing a chemical-mechanical polish (CMP) before growth of the desired epitaxial device structures. Such CMP processes further add to the cost and also expose the surface to contamination and further difficulties and limitations from regrowth on this once exposed interface. A further disadvantage of this thick graded buffer layer approach arises from the coefficient of thermal expansion (CTE) mismatch between Ge (5.90×10−6 K−1) and Si (2.57×10−6 K−1). This CTE mismatch can lead to defect formation and/or to breaking or cracking of a wafer including a thick buffer layer as temperature is varied during post-growth processing.
Management of lattice mismatch strain is particularly relevant for fabrication of quantum wells, which are often used in various optoelectronic devices. A quantum well includes a thin semiconductor well layer sandwiched between two semiconductor barrier layers. The well layer thickness is typically less than about 10 nm, and the energy bandgap of the well layer is less than the energy bandgap of the barrier layers. Further, the effective bandgap and optical properties of this well layer are dependent upon the layer thickness, hence, uniformity on a scale around 1 nm or better is extremely critical. Quantum wells in the SiGe material system are considered in U.S. Pat. No. 6,784,466 (referenced above), U.S. Pat. No. 5,886,361 and in US 2005/0141801. However, as indicated in U.S. Pat. No. 5,886,361 and US 2005/0141801, SiGe quantum wells tend to have poor electron confinement, since most of the quantum well bandgap discontinuity is in the valence band. The device of U.S. Pat. No. 5,886,361 does not require electron confinement in the quantum wells, and doping with electron donors is considered in US 2005/0141801 to improve electron confinement.
Accordingly, it would be an advance in the art to provide SiGe quantum wells having improved optical properties, especially when undoped. It would be a further advance in the art to provide such quantum wells on a Si substrate without the use of a graded buffer layer for lattice mismatch.
The present invention provides SiGe quantum wells where the well material has a conduction band energy local minimum at k=0 (the Γ point of the first Brillouin zone). Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, especially optical modulators. In the Si1-x-Gex material system, this condition on the band structure is satisfied for x greater than about 0.7. The quantum well barrier composition may or may not have Kane-like bands. A preferred method of providing such quantum well structures on a substrate (e.g., a silicon substrate) is to grow a first Ge-rich SiGe buffer layer on the substrate, and then anneal the resulting layered structure. In many cases it is further preferred to grow a second Ge-rich SiGe buffer layer on top of the first buffer layer and anneal the resulting layered structure.
Quantum well structures of the invention are broadly applicable to electronic, optoelectronic and spintronic devices. Application of the invention to optical modulators is especially promising.
Embodiments of the invention having a surface parallel configuration are especially suitable for use in fiber coupled devices. Such surface parallel devices have light propagating in the plane of the quantum wells, in a device geometry that is preferably not single-mode waveguided.
In order to appreciate the invention, it is best to consider several typical semiconductor E-k (energy-momentum) band diagrams.
A key discovery of the present invention is that indirect bandgap materials of the kind shown in
The reason the shape of the conduction band at k=0 is critical is that optical transitions on an E-k band diagram are vertical (to a good approximation). Since the highest energy occupied state in the valence band is nearly always at or near k=0, inter-band optical absorption is strongly affected by the band structure at and near k=0. However, it is still possible for the presence of lower energy conduction band minima at non-zero k to spoil the optical performance of a material having Kane-like bands. For example, an optical modulator that is based on free carrier absorption by electrons in a quantum well will require good confinement of electrons to the quantum well. As indicated above, electron confinement in SiGe quantum wells (which is determined by the indirect bandgap) tends to be poor. Another possible mechanism for degraded optical performance in indirect Kane-like materials is electron scattering from the k=0 conduction band minimum to lower energy conduction band minima having non-zero k. Depending on the scattering rate, this effect can degrade or even eliminate physical effects associated with the k=0 band structure.
A second key discovery of the present invention is that the SiGe/Ge material system is a suitable material system for practicing the invention. More specifically, as discussed later, experimental evidence has been obtained showing clear evidence of physical effects from the k=0 band structure of Ge quantum wells that can be exploited for device applications. As indicated above, Ge is Kane-like, Si is not Kane-like, and we have found that Si1-xGex is Kane-like for x greater than about 0.7. Thus the invention relates to Ge quantum wells and to Si1-xGex quantum wells having x greater than about 0.7.
Valence band 202 shows that the quantum well acts to confine holes. Indirect conduction band 206 shows that the quantum well acts to confine electrons, although this confinement is relatively weak. Direct conduction band 204 shows a much more pronounced conduction band discontinuity than the indirect conduction band 206. More precisely, the quantum well energy is the difference in direct bandgap (i.e., k=0 energy gap) between the barrier layers and the well layer. The direct conduction band discontinuity of the structure is about 30% to about 80% of the quantum well energy.
Various physical effects can be exploited to provide optoelectronic devices. In the present invention, preferred physical mechanisms do not rely on electron confinement in the quantum well, since such confinement is weak in the SiGe material system. Instead, preferred physical effects relate to electric field induced shifts in the direct absorption edge of the quantum well structure such as the Quantum Confined Stark Effect (QCSE), the Wannier-Stark effect, and the Franz-Keldysh effect. These effects can provide both electro-absorption (i.e., a field-dependent absorption) and electro-refraction (i.e., a field-dependent refractive index). Devices can be based on one or several of these effects. Typically, devices based on such effects are fabricated as P-I-N diodes with the quantum wells in the I region (i.e., the quantum wells are not intentionally doped).
Buffer layers 304 and 306 provide a preferred approach for dealing with the lattice mismatch between Si and SiGe (or Ge) and with surface roughness of the buffer layer. Buffer layer 304 is preferably a Ge-rich SiGe buffer layer having a thickness of about 250-500 nm and a surface roughness of about 1 nm or better deposited on substrate 302 by chemical vapor deposition at a growth temperature of about 300° C. to about 700° C. After the growth of buffer layer 304, the layered structure including substrate 302 and layer 304 is annealed at a temperature of about 550° C. to about 930° C., preferably for about 30-60 minutes.
After this annealing, it is preferred, although not required, to deposit a second Ge-rich SiGe buffer layer 306 also having a thickness of about 250-500 nm on layer 304 by chemical vapor deposition at a growth temperature of about 300° C. to about 700° C. After the growth of buffer layer 306, the layered structure including substrate 302 and layers 304 and 306 is preferably annealed at a temperature of about 550° C. to about 930° C., preferably for about 10-30 minutes.
The compositions of buffer layers 304 and 306 are preferably selected such that device layers 308, 310, 312 and 314 as a whole are lattice matched to the device substrate provided by substrate 302 and buffer layers 304 and 306. Techniques for such strain compensation (or strain balancing) are known in the art. For example, if the device layers include Ge quantum wells and Si0.2Ge0.8 barriers having equal total well and barrier thickness, then the buffer layer composition should be Si0.1Ge0.9 to compensate the strain.
We have found that this growth method provides a device substrate including substrate 302 and layers 304 and 306 that is suitable for the further growth of device-quality SiGe material. In particular, the lattice constant at the top of layer 306 is close to that of the following SiGe device layers, and layer 306 is relaxed and has low defect density. Since buffer layers 304 and 306 are relatively thin compared to conventional graded composition buffer layers, the effect of CTE mismatch is advantageously reduced. The invention can also be practiced by growing a thick buffer layer having a graded SiGe composition in order to accommodate the lattice mismatch, but this approach is not preferred.
The QCSE observed on
Quantum wells according to the invention can be used in electronic, optoelectronic, optical or spintronic devices. The invention is especially applicable to optical modulators, since optical modulators often require sophisticated device structures such as quantum wells, but typically do not require extremely low defect density. Optical modulators tend to be more tolerant of material defects than optical sources (e.g., lasers) because optical modulators are typically not high-current devices.
Various geometrical configurations for optical modulators are known, having different optical coupling geometries and/or different electric field biasing geometries. The invention is applicable to any optical modulator geometrical configuration, since the active region of any such modulator can include Ge or SiGe quantum wells as described above.
Transmissive devices similar to the device of
Because of this decreased interaction length, surface-normal modulators tend to require a significantly larger number of quantum wells in the active region in order to provide a desired level of modulation performance than waveguide or “side-coupled” modulators. Foe example, 20-70 quantum wells may be needed in a surface-normal modulator, while a waveguide modulator may need only 1-3 quantum wells. Having a large number of quantum wells in the active region can present two difficulties. The first difficulty is that the thicker a structure is, the more carefully strain due to lattice constant mismatch has to be considered. As indicated above, strain compensation techniques are known for addressing this issue. Also as indicated above, modulators tend to be relatively tolerant of material defects. For example, dislocations which would undesirably increase dark current in a detector would have comparatively little impact on a modulator, since dark current is not a critical modulator parameter.
The second difficulty is that having a thick I-region with many quantum wells in it increases the reverse voltage required to provide a given electric field to the quantum wells. QCSE modulators having a small number (e.g., 1-3) of quantum wells can have operating voltages that are consistent with CMOS operating voltages (e.g., ˜1 V or less). However, QCSE modulators having a large number of quantum wells in series in an I region can have operating voltages significantly higher than readily available in CMOS circuitry.
This problem of excessive operating voltage is addressed by the configuration of
The arrangement of
The preceding examples are representative, and are not an exhaustive description of modulator configurations. The invention is also applicable to many other modulator configurations, such as amplitude and/or phase modulators, reflective and/or transmissive modulators, and modulators with and without a resonant cavity. This invention is also applicable to optoelectronic devices other than modulators (e.g., sources and detectors), and to electronic and spintronic devices.
Modulator configurations where the light propagates in the plane of the quantum wells typically include a single mode optical waveguide to increase interaction length and thereby reduce operating voltage (e.g., as in some of the preceding embodiments). However, coupling to single mode waveguides can entail significant practical difficulties. Alignment tolerances for coupling to single mode waveguide are tight (e.g., on the order of 0.1 μm) due to the small mode size in such waveguides. Furthermore, single mode waveguides in semiconductor electro-optic devices tend to have non-circular mode profiles and/or significantly different divergence angles in different directions. Significant coupling loss can be incurred in coupling such waveguides to optical fibers, which usually have circular modes and the same divergence angle in all directions. Mode matching optics can be employed to reduce this coupling loss, but inclusion of mode matching optics undesirably increases device complexity.
Accordingly, in some preferred embodiments of the invention, light propagates in the plane of the quantum wells, but is not necessarily single-mode guided in the modulator. Instead, confinement can be provided by multi-mode guiding in the modulator active region or by focusing an optical beam through the modulator active region. Such modulator configurations can be referred to as “surface parallel modulators”.
Modulator 1204 is preferably thick (e.g., vertical thickness ˜6 μm) and short (e.g., length ˜40 μm). Such dimensions are compatible with simply focusing light to be modulated as a beam through the modulator active region, thereby making waveguiding unnecessary. Modulator 1204 preferably has a large total quantum well thickness (e.g., ˜0.2 μm total quantum well thickness), to provide sufficient modulation despite the short device length. Modulator 1204 is preferably an electro-absorption modulator.
V-grooves can be formed in silicon by lithographic patterning followed by etching, as is well known in the art. A preferred fabrication method is to use a KOH etchant in combination with a silicon nitride mask. Such V-grooves have precisely angled and positioned surfaces (e.g., θ on
Trenches 1210 and 1212 have vertically etched faces including end faces of modulator 1204. Methods for providing such vertically etched surfaces are well known in the art. A preferred approach is to dry-etch a vertical surface with a CF4 reactive ion etch, and smooth the resulting somewhat rough vertical surface with an H2O2 wet etch.
Input and/or output optical coupling from fiber to modulator can be performed in any manner. For example lensed fiber end faces and/or flat fiber end faces can be employed at the modulator input and/or output. A preferred configuration is shown in
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|U.S. Classification||385/2, 257/E29.078, 385/50, 385/3, 257/E29.085, 257/E31.061, 257/E31.06, 257/E21.129, 257/E31.035, 385/30|
|International Classification||G02B6/26, G02F1/035|
|Cooperative Classification||H01L29/155, G02F2203/026, H01L21/02507, G02F2201/124, H01L31/105, H01L29/165, B82Y20/00, G02F2203/02, H01L21/0262, G02F2203/023, G02F1/01708, H01L21/02532, H01L31/035254, G02F1/017, H01L21/02381, G02F2001/01766, H01L31/1037, H01L21/0245|
|European Classification||B82Y20/00, H01L21/02K4B1A3, H01L21/02K4E3C, H01L21/02K4B5L3A, H01L21/02K4C1A3, H01L21/02K4A1A3, H01L31/103D, H01L31/105, G02F1/017, H01L31/0352B3, H01L29/165, H01L29/15B2C|
|Dec 18, 2006||AS||Assignment|
Owner name: BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MILLER, DAVID A.B.;KUO, YU-HSUAN;HARRIS, JAMES S. JR.;REEL/FRAME:018719/0223
Effective date: 20061212
|May 16, 2012||FPAY||Fee payment|
Year of fee payment: 4
|Jul 8, 2016||REMI||Maintenance fee reminder mailed|
|Nov 25, 2016||LAPS||Lapse for failure to pay maintenance fees|
|Jan 17, 2017||FP||Expired due to failure to pay maintenance fee|
Effective date: 20161125