|Publication number||US7457904 B2|
|Application number||US 11/014,409|
|Publication date||Nov 25, 2008|
|Filing date||Dec 16, 2004|
|Priority date||Dec 16, 2004|
|Also published as||CN1790224A, CN1790224B, US20060136643|
|Publication number||014409, 11014409, US 7457904 B2, US 7457904B2, US-B2-7457904, US7457904 B2, US7457904B2|
|Inventors||Richard S. Lin, Jeffrey K. Jeansonne, Walter G. Fry|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (9), Referenced by (3), Classifications (15), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
In some computers, additional functionality may be added via swappable (i.e., hot-pluggable) plug-in devices known as “cards” or “modules.” When a card is plugged into an associated port or slot of a computer, the functionality of the card is accessible to the computer. If a user wishes, the card may be unplugged from one computer and plugged into another computer, thereby switching the functionality provided by the card from one computer to another.
In order for some cards to function, a computer that receives the card may need to periodically synchronize clock signals embedded in data packets with another clock signal. This periodic syncing may be performed by a reference clock. Unfortunately, permitting a reference clock to run continuously (whether or not a card is plugged in) results in increased power consumption and increased likelihood of electromagnetic interference (EMI). Further, altering an existing reference clock architecture (i.e., platform) is often costly and may cause compatibility problems.
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The term “system” refers to a collection of two or more parts and may be used to refer to a computer system or a portion of a computer system.
As disclosed herein, some embodiments of the invention enable a serial reference clock signal to be activated/deactivated based on the presence or the absence of a hot-pluggable card. When activated, a serial reference clock enables periodic synchronizing of clock signals embedded in data packets with another clock signal. For example, devices that implement a Peripheral Component Interconnect Express protocol (“PCI Express”) use a serial reference clock to periodically sync clock signals embedded in data packets with a 2.5 GHz clock signal.
In some embodiments, activation/deactivation of a serial reference clock based on the presence or absence of a hot-pluggable card is accomplished by reducing a predetermined scalability of the serial reference clock platform. As used herein, reducing the predetermined scalability of a serial reference clock platform comprises reducing the availability or quality of at least one serial reference clock signal associated with a scalable serial reference clock platform. For example, the serial reference clock platform for PCI Express is predetermined to be scalable up to a maximum of seven pairs of differential serial reference clock signals. Thus, in embodiments that implement PCI Express, reducing the predetermined scalability of a serial reference clock platform comprises reducing the availability or quality of at least one of the seven pairs of differential serial reference clock signals.
Reducing the predetermined scalability of a serial reference clock platform enables an external card signal (indicating the presence or absence of a hot-pluggable card) to be received by a serial reference clock directly. For example, a serial reference clock may be configured to receive the external card signal via a pin location that is available by reducing the predetermined scalability of the serial reference clock platform. In some embodiments, reducing the predetermined scalability of a serial reference clock platform does not affect a system's performance. For example, some systems that implement PCI Express may only use, for example, two pairs or three pairs (out of seven pairs) of the differential serial reference clocks. In such systems, reducing the predetermined scalability of PCI Express from seven pairs of differential serial reference clocks to, for example, six pairs of differential serial reference clocks does not affect the system's performance.
In alternative embodiments, activation/deactivation of a serial reference clock based on the presence or absence of a hot-pluggable card is accomplished by an interrupt routine compatible with existing hardware components of a system that implements the serial reference clock generator. For example, a hardware component (e.g., a chipset) having programmable inputs may be configured to receive a signal that indicates when a card is present (i.e., plugged into a system). When the programmable input indicates that the signal has been received, an interrupt routine compatible with the hardware component may be executed whereby one or more commands are sent to the serial reference clock generator to activate a reference clock.
In some cases, existing system architectures are predetermined or predefined such that hardware changes/additions potentially create compatibility problems and other issues. Embodiments of the invention described herein, provide the benefit of limiting or eliminating hardware changes/additions to existing system architectures, thus, reducing compatibility problems and expenses related to such hardware changes/additions.
The hot-pluggable card 120 adds a predetermined functionality to the computer 102. For example, the hot-pluggable card 120 may provide networking functionality, graphics functionality, audio functionality, peripheral bus functionality, memory or other functionality. In some embodiments, the hot-pluggable card 120 implements the PCI Express protocol and the port 110 may be a corresponding PCI Express-compatible port. Alternatively, the hot-pluggable card 120 and the port 110 may implement another communication protocol, now known or later developed.
As shown, the port 110 transmits several signals between components of the computer (e.g., the reference clock unit 104, the power switch 106, and the host chipset 108) and the hot-pluggable card 120. Table 1 shows a listing of signal labels used in
Card Present Protocol 1
Signals when a first
protocol (e.g., USB) card is
Card Present Protocol 2
Signals when a second
protocol (e.g., PCI Express)
card is present
Power supply 1
Provides a 3.3 volt signal to
Auxiliary Power Supply
Provides a 3.3 volt auxiliary
signal to the card
Power Supply 2
Provides a 1.5 volt signal to
Provides an electrical
ground to components
Protocol 2 Reset
Provides a logic level
Provides a positive and
negative clock reference to
Signals that the card
requires a clock reference
System Management Bus
signals to the clock
Protocol 2 Differential
Provides a serial bus
connection to the card
Protocol 2 Differential
Provides a serial bus
connection to the card
Protocol 1 Port
Protocol 1 connection to
Controls reset to card
As shown in Table 1, the CPP1 signal indicates when a hot-pluggable card 120 based on a first protocol (e.g., Universal Serial Bus or “USB”) is plugged into the port 110. The CPP2 signal indicates when a hot-pluggable card 120 based on a second protocol (e.g., PCI Express) is plugged into the port 110. The +3.3V signal supplies a 3.3 volt signal to the hot-pluggable card 120. The +3.3 VAUX signal supplies an auxiliary 3.3 volt signal to the hot-pluggable card. The +1.5V signal supplies a 1.5 volt signal to the hot-pluggable card 120. The GND signal represents an electrical ground for components of the system 100 and the hot-pluggable card 120.
The P2RST signal indicates when to reset a hot-pluggable card 120 based on the second protocol. For example, the P2RST signal may be asserted after valid power and reference clock signals are provided to the hot-pluggable card 120. The REFCLK+ and REFCLK− signals supply a positive clock reference and a negative clock reference respectively to the hot-pluggable card 120. The REFCLK+ and REFCLK− signals may be output from high resistance (Hi-Z) clock generator outputs. As described previously, the REFCLK+ and REFCLK− signals may be used to synchronize clock signals embedded in data packets transferred between the card 120 and the computer 102 with another clock signal.
The CLKREQ signal indicates when the hot-pluggable card 120 requests a serial reference clock signal. The SMBUS signal supplies SMBUS protocol commands between the host chipset 108 and the clock unit 104. The P2T signals provide serial bus signals from the host chipset 108 to a hot-pluggable card 120 based on the second protocol. The P2R signals provide serial bus signals from the hot-pluggable card 120 to the host chipset 108 based on the second protocol. In some embodiments, the P2T and P2R signals correspond to the data packets with embedded clock signals described previously. Thus, the REFCLK+ and REFCLK− signals may be used to sync embedded clock signals associated with the P2T and P2R signals with another clock (e.g., a 2.5 GHz clock).
The P1 signals provide signals between the host chipset 108 and the hot-pluggable card 120 based on the first protocol. The PLTRST signal enables the chipset 108 to reset devices on the platform (e.g., a PCI Express platform). As shown, the PLTRST signal is input to the power switch 106 which, in some embodiments, controls the P2RST signal as will later be described. While the signals described above are used in the exemplary embodiment of
When the computer 102 is powered up (e.g., during a power-on self-test referred to as a “POST”), a general programmable input (GPI) of the chipset 108 is configured for use with the CPP2 signal. For example, a system management interrupt (SMI) handler or an Advanced Configuration and Power Interface (ACPI) method may be executed by the processor 112 to program the GPI to generate interrupts compatible with the chipset 108 based on the CPP2 signal. In some embodiments, the SMI handler or the ACPI method described above may use Basic Input/Output System (BIOS) code. The BIOS code may be stored in the BIOS memory 113 coupled to the processor 112.
If the GPI cannot trigger on both input signal edges (rising edge and falling edge), the BIOS code (or other computer-readable instructions), when executed, causes the processor 112 to detect the state of the CPP2 signal to set up the signal edge to trigger an interrupt. As shown in
If either the CPP2 signal or the CLKREQ signal is detected to be asserted, the BIOS code causes a general programmable output (GPO) of the chipset 108 to de-assert a signal 122 to an RCLKEN (release clock enable) input of the power switch 106. De-assertion of the RCLKEN signal causes the card 120 (via the P2RST signal) to remain in a reset state.
As shown in
In response to receiving an asserted CPP2 signal or an asserted CLKREQ signal by the GPI of the host chipset 108, an interrupt routine is executed. During the interrupt routine, the host chipset 108 asserts a signal to the reference clock unit 104 whereby the reference clock unit 104 outputs the REFCLK+ and REFCLK− signals. For example,
Initially, the REFCLK+ and REFCLK− signals may be unstable. Therefore, a time period hereafter referred to as a “settling period” may be implemented to allow the REFCLK+ and REFCLK− signals to stabilize. The settling period may be a predetermined time period. Alternatively, the settling period may be determined by monitoring the REFCLK+ and REFCLK− signals to determine when the signals have stabilized. After the settling period, the host chipset 108 asserts the RCLKEN signal 122 to the power switch 106. Assertion of the RCLKEN signal 122 causes the power switch 106 to release the P2RST (reset) signal to the hot-pluggable card 120 thereby enabling the card 120 to operate.
Before the interrupt routine terminates, the GPI of the host chipset 108 is set up to trigger an interrupt in response to a rising edge of the CPP2 signal or the CLKREQ signal (i.e., in some embodiments, a rising edge is associated with a de-asserted CPP2 signal or CLKREQ signal because a “high” signal rather than a “low” signal indicates absence of the card 120). If the GPI later detects a de-asserted CPP2 signal or CLKREQ signal, the SMI handler or the ACPI code causes a SMBUS write command to be sent to the reference clock unit 104. The write command disables the REFCLK signals to the card 120. The SMI handler or the ACPI code also causes the GPO of the host chipset 108 to de-assert the RCLKEN signal to the power switch 106 thereby setting up the P2RST signal in the correct state for when the a card 120 is inserted into the port 110. Also, the GPI of the host chipset 108 is again set up to trigger in response to a falling edge (i.e., assertion) of the CPP2 signal or the CLKREQ signal.
When an asserted CLKREQ signal or CPP2 signal is received by the reduced REFCLK architecture 148 (i.e., when the hot-pluggable card 120 is plugged into the port 110 or requires a clock signal), a signal 150 is forwarded to the clock control logic 142. In response to the asserted signal 150, the clock control logic 142 asserts a signal 152 to power/reset logic 146 of the clock generator 144 whereby one or more pairs of REFCLK+ and REFCLK− signals are activated and output from the clock generator 144.
When either the CLKREQ or CPP2 signals are de-asserted (e.g., when the hot-pluggable card 120 is unplugged from the port 110 or does not require a clock signal), the reduced REFCLK architecture 148 may forward a de-asserted signal 150 to the clock control logic 142. The clock control logic 142 may then de-assert the signal 152 to the power/reset logic 146 of the clock generator 144 whereby the REFCLK+ and REFCLK− signals are deactivated.
Additionally, commands provided via the SMBUS may cause the clock control logic 142 to assert and de-assert the signal 152, thereby activating and de-activating the REFCLK+ and REFCLK− signals. For example, the SMBUS command may be provided when a computer 102 is powered up such that the REFCLK+ and REFCLK− signals are activated without consideration of the external signal. Therefore, while operation of the reference clock unit 124 may be based on an external signal, the reference clock unit 124 is also configurable to output SRC clock signals based on commands from the host chipset 108.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, embodiments of the invention may implement other software, hardware, or a combination thereof to activate/deactivate a reference clock signal based on the presence or absence of a hot-pluggable card. It is intended that the following claims be interpreted to embrace all such variations and modifications.
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|U.S. Classification||710/302, 327/291, 713/600, 710/66, 713/400, 710/36, 710/306|
|International Classification||G06F13/00, G06F3/00, G06F1/12, G06F1/04, G06F13/36, G06F13/38|
|Apr 8, 2005||AS||Assignment|
Owner name: HEWLETT-PARCKARD DEVELOPMENT COMPANY, LP, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, RICHARD S.;JEANSONNE, JEFFREY K.;FRY, WALTER G.;REEL/FRAME:016039/0639;SIGNING DATES FROM 20050407 TO 20050408
|May 12, 2009||CC||Certificate of correction|
|May 25, 2012||FPAY||Fee payment|
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|Apr 27, 2016||FPAY||Fee payment|
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