US 7459376 B2
A method of fabricating a semiconductor component includes providing a prefabricated frame that includes metal traces and lead-through contacts. A semiconductor chip is mounted into the prefabricated frame such that the semiconductor chip is embedded within a rim of the prefabricated frame. Contact regions on a surface of the semiconductor chip are electrically connected with the metal traces of the prefabricated frame such that the contact regions are electrically coupled to the lead-through contacts via the metal traces.
1. A method of fabricating a semiconductor component, the method comprising:
forming a trace attached to a substrate and made solely of conductive metal, said conductive metal trace having a first end and a second end;
providing a frame structure having a rim at least partially defining a first recess for receiving a semiconductor circuit and a bore;
filling the bore with a solder material to form a lead-through contact;
positioning said bore of said frame structure filled with said solder material to contact said first end of said metal trace on the substrate;
reflowing said solder material filling the bore to attach the first end of the metal trace to the frame structure;
detaching the metal trace from the substrate such that the first end of the metal trace is supported by the rim of the frame structure and the reflowed solder material in said lead-through contact so that the second end of the metal trace is cantilevered over said recess;
adhering a semiconductor chip to a dummy substrate;
positioning the semiconductor chip within the first recess of the frame structure such that said semiconductor chip is embedded within said rim of the frame structure;
attaching the semiconductor chip to the rim of the frame structure;
removing the dummy substrate from the semiconductor chip; and
physically connecting a contact region on a surface of the semiconductor chip directly to the cantilevered second end of said metal trace of the frame structure such that the contact region is electrically coupled to the lead-through contact via the metal trace.
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forming a sacrificial layer over the substrate;
patterning the sacrificial layer;
depositing a seed layer over the patterned sacrificial layer;
forming metal over the seed layer;
planarizing the metal to expose the patterned sacrificial layer; and
removing the patterned sacrificial layer.
9. The method of
10. The method of
The invention is concerned with a dissociated fabrication and final package of chips of integrated circuits with so called “redistribution layers” or metal traces.
It is well known for one skilled in the art that the fabrication of integrated circuits requires many fabrication steps, starting with structuring a silicon chip for the desired electrical function, e.g., a memory chip or a processor. This process covers deposition steps, photolithography steps, etching steps and other fabrication steps until the desired function is performed. After that, the integrated circuit is finally mounted on a substrate, such as a printed circuit board, and the electrical interconnections between the circuit and the board are carried out at the same time.
This electrical interconnection is often established by wiring or wire bonding. In a final step, the integrated circuit must be provided with a housing, which can be formed by molding a suitable mold compound around the chip so that the sensitive chip is protected against mechanical damage.
Most memory chips must not be exposed to temperatures above 200° C. because of so called retention failures. The result is that the applicable processing technologies and materials for packaging are limited significantly.
An example of a multichip module with stacked semiconductor chips is described in the U.S. patent application publication 2003/0015803 A1, which is incorporated herein by reference. In this publication bond pads on the rim of the chip are connected with bonding pads on a board with bond wires. Another example is described in the German patent publication 102 51 530 A1 and U.S. Patent application publication 2004/0113256 A1, which are incorporated herein by reference. In a stacked memory device, two semiconductor chips are stacked and are each provided with central rows of bond pads and redistribution layers on the top surface of each chip with inner landing pads. The inner landing pads are connected with the bond pads by wire bonding. The redistribution layers are also provided with landing pads on the rim of the chip, each being connected with contact pads at the board by wire bonding. The complete staple is molded with a mold compound so that the two bare chips and the wire loops are enclosed in this encapsulation.
Typically the fabrication of the package is performed before embedding the chip inside the package. Afterwards electrical interconnection of the chip and package by the wire bonding process as described above is followed by over-molding. Such steps are process steps at low temperatures without any influence on the thermal budget.
However, future and some currently available memory products, especially stacked chips require a different packaging method to meet desired performance, cost and reliability. Recent product generations and all known development paths for future products employ packages which are partially fabricated together with the chip. For example, so called “redistribution layers” as mentioned above are electroplated on the surface of a chip. In some cases even the package is completely “built” around the chip. As mentioned before the applicable processing methods are then limited to temperatures below 200° C.
In one aspect, the present invention is directed to decrease the temperature load on fabrication of semiconductor chips by dissociated fabrication of packages and chips. Most parts of the package are fabricated separately from the chip. This allows a higher freedom for processing temperatures and materials regarding package fabrication.
According one aspect of the invention, a multichip module is realized by stacking prefabricated semiconductor modules and then molding the stacked chips.
Each prefabricated semiconductor module includes a semiconductor chip mounted in a completely prefabricated frame provided with metal strips connecting the bond pads on the chip arranged in a central row on the top surface of the chip. The other end of the metal strips is connected with lead through connections in the frame. Such a frame can be a molded frame. The bond connects between the central bond pads and the metal strips can be realized by ultrasonic compression batch bonding.
Another aspect of the invention is to minimize the thermal induced mechanical stress of the package. For that, the semiconductor chips in the frame have no fast contact with the inside of the frame and are held only by the bond contacts of the metal strips with the bond pads on the chip. Since the chips have many degrees of freedom, thermal expansion of the chip will not lead to any mechanical stress.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The dissociated fabrication and final package of chips of integrated circuits describes completely prefabricated semiconductor chips surrounded by a frame and held in it by electrical and mechanical connections between bond pads on the chip in a central row arrangement and metal traces on the frame terminate in a semiconductor module. This semiconductor module can be stacked in a stacked arrangement.
To realize such semiconductor modules and stacked arrangement of them with a dissociated fabrication of the components will be described hereinafter.
A first example will describe a simplified process for fabricating the necessary components of a semiconductor module and finally a stacked arrangement of such modules.
The next step is sputtering a seed layer 1.7 of Cr/Au as seen from
The sequence of
Then the structure of
The last step of prefabrication of the frame 1.8 with the accompanying metal traces 1.1 is shown in
In a next step, the prefabricated structure according
Then the structure is exposed to UV-light, to release tape 1.15 and glass wafer 1.17 as shown in
A second example will be described hereinafter.
A seed layer 2.9 of Ti/Au is then deposited at the surface of the structure as shown in
The prefabrication of the metal lead 2.2 and the lead through contact 2.3 is performed by electroplating a first layer of 3 μm Au, a second layer of 9 μm Ni for mechanical stability and a third layer of 3 μm Au as shown in
The final steps are stripping of electrophoresis resist (
In parallel processing according to
As shown in
Then the frame structure is diced into single dies, as shown in
The prefabricated semiconductor module 2.17 is shown in
This prefabricated module 2.17 can be stacked on a stacked structure according
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.