|Publication number||US7463520 B2|
|Application number||US 11/277,436|
|Publication date||Dec 9, 2008|
|Filing date||Mar 24, 2006|
|Priority date||Mar 24, 2006|
|Also published as||US7826265, US20070223278, US20090109756|
|Publication number||11277436, 277436, US 7463520 B2, US 7463520B2, US-B2-7463520, US7463520 B2, US7463520B2|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (11), Classifications (11), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to memory devices and, more particularly, to a memory device with variable trim settings.
Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in portable electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory includes a memory array having a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate. Within each block, cells may be further grouped by page. Each page is associated with a particular word line of the array.
NOR and NAND flash memory devices are two common types of flash memory devices, so called for the logical form of the basic memory cell configuration in which each is arranged. Typically, for NOR flash memory devices, the control gate of each memory cell of a row of the array is connected to a word line, and the drain region of each memory cell of a column of the array is connected to a bit line. The memory array for NOR flash memory devices is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their control gates. The row of selected memory cells then place their data values on the column bit lines by flowing a differing current, depending upon their programmed states, from a connected source line to the connected column bit lines.
An array of memory cells for NAND flash memory devices is also arranged such that the control gate of each memory cell of a row of the array is connected to a word line. However, each memory cell is not directly connected to a column bit line by its drain region. Instead, the memory cells of the array are arranged together in strings (often termed NAND strings), e.g., of 32 each, with the memory cells connected together in series, source to drain, between a source line and a column bit line. The memory array for NAND flash memory devices is then accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series connected string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
Memory devices usually include trim circuits that are programmed to output bit values used to provide a variety of options for algorithms that control the operations of the memory device. Such algorithm options may include timing, pulse counts, applied voltage levels, etc. The trim bit values are usually programmed once for a memory device and are rarely changed once the memory device has reached production. Moreover, the bit values are usually applied globally to an entire memory array, which can include thousands of memory blocks, especially for NAND devices. However, as memory array sizes increase, applying the bit values globally to an entire memory array may not be sufficient. Performance variations exist across the array due to factors such as critical dimension (CD) variation within the die and inside NAND strings. Hence, it is difficult to determine a single trim set that may be applied to the entire array.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
One aspect of the present invention is seen in a memory device including a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to program at least a portion of a selected subset using the associated trim parameter.
Another aspect of the present invention is seen a method for operating a memory device. The method includes storing at least one trim parameter for each of a plurality of subsets of a memory array in the memory device within each of the subsets. At least a portion of a selected subset is programmed based on the at least one trim parameter associated with the selected subset.
The invention will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements, and:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
One or more specific embodiments of the present invention will be described below. It is specifically intended that the present invention not be limited to the embodiments and illustrations contained herein, but include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. Nothing in this application is considered critical or essential to the present invention unless explicitly indicated as being “critical” or “essential.”
The present invention will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Referring now to the drawings wherein like reference numbers correspond to similar components throughout the several views and, specifically, referring to
The flash memory device 100 includes an array 115 of memory cells. The memory cells are non-volatile floating-gate memory cells and may employ a NAND or NOR topology. The memory array 115 is arranged in banks of rows and columns. An address buffer circuit 120 is provided to latch address signals provided on address input connections A0-Ax 125. Address signals are received and decoded by a row decoder 130 and a column decoder 135 to access the memory array 115. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 115. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
Bank address lines 140 are used to access the different banks of the memory array 115. The number of banks may vary. For example, four memory banks may be provided. In such an embodiment, two bank address lines, BA1 and BA0, are required to activate a selected one of the memory banks. For example, if the memory banks are designated as Bank0 . . . Bank3, and memory bank 3 is desired to be activated, then the bank address lines are set to BA1=1 and BA0=1. If a memory embodiment has different quantities of memory banks, different quantities of bank select lines will be required.
The flash memory device 100 reads data in the memory array 115 by sensing voltage or current changes in the memory array columns using sense/latch circuitry 145. In one embodiment, the sense/latch circuitry 145 is coupled to latch a row of data from the memory array 115. Data input and output buffer circuitry 150 is included for bidirectional data communication over a plurality of data (DQ) connections 155 with the processor 105. Write/erase circuitry 160 is provided to write data to the memory array 115 or to erase the data programmed therein.
A command control circuit 165 decodes signals provided on control connections 170 from the processor 105. In one embodiment, the command control circuit 165 is implemented using a state machine that executes the functions of the memory array 115, including data read, data write, and erase operations. The state machine may also be responsible for executing the functions required for either a virtual synchronous flash memory function or a synchronous flash memory function, depending on the control word.
The processor 105 generates signals on the address, data, and control lines to the memory device 100. Alternate embodiments may use other controllers to generate these signals. Additionally, the memory device 100 may be coupled to something other than a controller or processor that generates the address, data, and control signals.
The command control circuit 165 in cooperation with the write/erase circuitry 160 employs variable trim parameters 175 for adjusting the parameters of the signals used for accessing, programming, or erasing the memory array 115 depending on the particular performance characteristics across the memory array 115. For example, parameters such as program start voltage (Vpgm_start), program step voltage (Vpgm_step_up), program pulse width, inhibit pulse width, erase start voltage (Verarse_start), erase step voltage (Verase_step), erase pulse width, etc., may be varied. In the illustrated embodiment different trim settings may be applied to different subsets of the memory array 115. For example, trim parameters 175 may be applied to a group of blocks, a single block, or pages within a block. The level to which trim parameters 175 are set depends on the particular characteristics of the memory array 115 and the expected performance variation across the array. Typically, the trim parameters are determined using a testing process performed during or after the fabrication of the memory device 100.
In the illustrated embodiment, the memory array 115 is programmed using an incremental step pulse programming technique, where multiple short pulses are applied to the cells being programmed. After each pulse, the contents are verified to determine if the device is successfully programmed. If the verify step fails, the voltage of the pulse is increased, and the program/verify operation is repeated iteratively. The incremental pulse technique reduces the likelihood that the cells will be over-programmed (i.e., exposed to a higher than necessary voltage), which can reduce the reliability of the device and shorten its operating life. The trim parameters 175 specify a starting program voltage, a step size, and a pulse width for the incremental step pulse programming technique. An erase operation may also be performed using an incremental pulse technique, with additional trim parameters 175 being provided to specify the starting erase voltage, step size, and pulse width for the erase cycle.
Turning now to
The trim parameters 175 may also be defined for a larger grouping of cells in the memory array 115, such as for a plurality of pages 210, an entire block 200, or a group 240 of blocks 200. In such instances, the trim parameters 175 need not be stored in the control region 220 for each page 210, but rather in a designated location within the trim grouping. For example, if the trim grouping corresponds to a block 200, the trim parameters 175 may be stored in the control region 220 for the first page 210 in the block 200. Similarly, if the trim grouping corresponds to a group 240 of blocks 200, the trim parameters 175 may be stored in the control region 220 for the first page 210 in the first block 200 of the group 240. Of course, the location of the trim parameters 175 may be varied depending on the particular implementation, as long as they are stored somewhere within the particular subset of the memory array 115 with which they are associated. If desired, the trim parameters 175 may be duplicated in other portions of the trim grouping. For example, the trim parameters 175 may be stored in every page 210 and/or in every block 200 of a trim grouping. The trim parameters 175 may include information specifying the size of the trim grouping (e.g., page, group of pages, block, or group of blocks).
Storing the trim parameters 175 within the subset of the memory array 115 with which it is associated is convenient in that no indexing of the trim parameters 175 to associate them with their associated subset is necessary. For example, if the trim parameters 175 were to be stored in an external buffer or other data structure, it would be necessary to link the trim parameters 175 with the associated trim grouping. Having the trim parameters 175 stored within the trim grouping makes such linking unnecessary. Also, due to the potentially large number of possible blocks 200 or pages 210 in a large memory array 115, storing the trim parameters 175 externally would require significant storage resources. By storing the trim parameters 175 in the associated trim grouping, the trim parameters 175 may be read as cells within the trim grouping are programmed.
Turning now to
As seen in
Turning now to
The default program parameters used in method block 410 may be selected based on the expected range of values typically for the memory array 115, and are implementation specific. For the default parameters, a relatively low program voltage and average pulse width may be applied. For example, the trim parameters 175 may specify a program voltage of 16V with a step increase of 0.6V. The default parameter is set at a lower value than is expected for the trim parameters 175 to avoid over-programming the memory array 115. In this example, a default program voltage of 15V may be used. Although the program voltage is less than what would have been used if the trim parameters 175 had been previously read (i.e., as in the method of
Table 1 below illustrates the program pulses employed using the methods of
Incremental Pulse Programming
Vpgm = 16 V
Initial Trim Read
Set Trim After Verify Read
Vstep = 0.6 V
The programming method of
Referring now to
In some embodiments, the techniques of
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5801985 *||Jul 28, 1995||Sep 1, 1998||Micron Technology, Inc.||Memory system having programmable control parameters|
|US7160284 *||May 21, 2003||Jan 9, 2007||Medtronic, Inc.||Implantable medical pump with multi-layer back-up memory|
|US20030031056 *||Aug 13, 2001||Feb 13, 2003||Micron Technology, Inc.||Non-volatile memory having a control mini-array|
|US20050122831||Jan 14, 2005||Jun 9, 2005||Micron Technology, Inc.||Method and architecture to calibrate read operations in synchronous flash memory|
|US20060015691 *||Jul 19, 2004||Jan 19, 2006||Micron Technology, Inc.||Memory device trims|
|US20060256620 *||May 11, 2005||Nov 16, 2006||Micron Technology, Inc.||Programming memory devices|
|US20070047315 *||Sep 1, 2005||Mar 1, 2007||Micron Technology, Inc.||Program and read trim setting|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7826265 *||Nov 2, 2010||Micron Technology, Inc.||Memory device with variable trim setting|
|US8014201 *||Sep 6, 2011||Samsung Electronics Co., Ltd.||Nonvolatile memory device extracting parameters and nonvolatile memory system including the same|
|US8358540||Jan 22, 2013||Micron Technology, Inc.||Access line dependent biasing schemes|
|US8730734||Jan 21, 2013||May 20, 2014||Micron Technology, Inc.||Access line dependent biasing schemes|
|US8804428||Aug 16, 2011||Aug 12, 2014||Micron Technology, Inc.||Determining system lifetime characteristics|
|US9007867||Feb 28, 2013||Apr 14, 2015||Micron Technology, Inc.||Loading trim address and trim data pairs|
|US9257182||Dec 21, 2012||Feb 9, 2016||Micron Technology, Inc.||Memory devices and their operation having trim registers associated with access operation commands|
|US9269452||Jul 15, 2014||Feb 23, 2016||Micron Technology, Inc.||Determining system lifetime characteristics|
|US20090109756 *||Dec 3, 2008||Apr 30, 2009||Micron Technology, Inc.||Memory device with variable trim setting|
|US20100027337 *||Jul 10, 2009||Feb 4, 2010||Samsung Electronics Co., Ltd.||Nonvolatile memory device extracting parameters and nonvolatile memory system including the same|
|US20110170353 *||Jul 14, 2011||Micron Technology, Inc.||Access line dependent biasing schemes|
|U.S. Classification||365/185.12, 365/185.18|
|Cooperative Classification||G11C16/3459, G11C16/3445, G11C16/20, G11C16/10|
|European Classification||G11C16/34V4C, G11C16/34V2C, G11C16/10, G11C16/20|
|Mar 24, 2006||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ARITOME, SEIICHI;REEL/FRAME:017362/0043
Effective date: 20060323
|Feb 10, 2009||CC||Certificate of correction|
|May 9, 2012||FPAY||Fee payment|
Year of fee payment: 4
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|May 26, 2016||FPAY||Fee payment|
Year of fee payment: 8
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426