|Publication number||US7470563 B2|
|Application number||US 11/248,914|
|Publication date||Dec 30, 2008|
|Filing date||Oct 11, 2005|
|Priority date||Jul 5, 2002|
|Also published as||US6673649, US7087995, US20040005732, US20040101991, US20060057774|
|Publication number||11248914, 248914, US 7470563 B2, US 7470563B2, US-B2-7470563, US7470563 B2, US7470563B2|
|Inventors||William Mark Hiatt, Warren Farnworth|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (85), Classifications (42), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. patent application Ser. No. 10/701,128, filed Nov. 3, 2003 now U.S. Pat. No. 7,087,995, which is a divisional of U.S. patent application Ser. No. 10/190,019, filed Jul. 5, 2002 now U.S. Pat. No. 6,673,649, both of which are incorporated herein by reference in their entireties.
The present invention is directed generally toward microelectronic device packages and methods for controlling the disposition and/or extent of non-conductive materials in such packages.
Existing microelectronic device packages typically include a microelectronic substrate or die attached to a support member, such as a printed circuit board. Bond pads or other terminals on the die are electrically connected to corresponding terminals on the support member, for example, with solder balls. The connection between the die and the support member can be encapsulated, for example, with a protective underfill material, to form a device package. The package can then be electrically connected to other microelectronic devices or circuits, for example, in a consumer or industrial electronic product such as a computer.
In one existing arrangement shown in
In one existing process, an underfill material 40 is initially disposed adjacent to two of the outer edges of the die 30. The underfill material 40 flows into the gap between the die 30 and the support member 20 to provide a protective encapsulant around the solder balls 50. The underfill material 40 can flow both directly into the gap (as indicated by arrows A) and around the outer edges of the die 30 (as indicated by arrows B).
One characteristic the process described above with reference to
One existing approach for addressing the foregoing drawback is to control the viscosity of the underfill material 40 so that it preferentially wicks more quickly through the gap than around the periphery of the die 30. For example, the viscosity can be controlled by controlling the temperature at which the underfill process is conducted, or the concentration of particulates in the underfill material 40. Alternatively, the surface characteristics of the die 30 and/or the support member 20 can be selected to produce a faster underfill flow rate through the gap than around the periphery of the die 30. Although the foregoing methods can produce satisfactory results, it may in some cases be difficult and/or expensive to accurately control the aforementioned variables. Furthermore, the underfill material 40 typically provides a permanent bond between the die 30 and the support member 20, making it difficult if not impossible to replace a defective die 30 without destroying the entire package 10.
The present invention is directed toward microelectronic packages and methods for forming such packages. A method in accordance with one aspect of the invention includes positioning a microelectronic substrate proximate to a support member, with the microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface. The support member can have a plurality of second and third connection sites. The method can further include connecting the microelectronic substrate to the support member by attaching a plurality of electrically conductive couplers between the plurality of first connection sites and the second connection sites, with neighboring conducted couplers being spaced apart to define at least one fluid flow channel, and with the support member and the microelectronic substrate forming a package. The package can then be provided for electrical coupling to other electrical structures via the third connection sites, with the at least one fluid flow channel accessible to a region external to the package.
In another aspect of the invention, flowable, electrically conductive couplers can be disposed at the first connection sites, and a generally non-conductive material can be disposed between the conductive couplers. A gap dimension can be selected based on a target underfill flow rate, and at least a portion of the generally non-conductive material can be removed to form a gap having the selected gap dimension and being positioned between neighboring conductive couplers. The microelectronic substrate and the support member can be connected by attaching the conductive couplers to the second bond sites of the support member, and an underfill material can be flowed into the gap at at least approximately the target underfill material flow rate.
A method in accordance with another aspect of the invention includes providing a first microelectronic substrate having first connection sites carrying first flowable, electrically conductive couplers that define a first plane. A first generally non-conductive material is applied to the first conductive couplers and to the first microelectronic substrate, and at least some of the first generally non-conductive material is removed to recess the first generally non-conductive material from the first plane by a first recess distance. The method can further include providing a second microelectronic substrate having second flowable, electrically conductive couplers defining a second plane spaced apart from the second microelectronic substrate by a second distance different than the first distance. A second generally non-conductive material is applied to the second conductive couplers, and at least some of the second generally non-conductive material is removed from between the second conductive couplers to recess the second generally non-conductive material from the second plane by a second recess distance that is at least approximately the same as the first recess distance.
A method in accordance with still another aspect of the invention includes connecting the microelectronic substrate to the support member by attaching the conductive couplers and disposing at least one generally non-conductive material adjacent to the conductive couplers, with the at least one generally non-conductive material being spaced apart from the support member. In another aspect of the invention, the at least one generally non-conductive material can be a first generally non-conductive material, and the method can further include disposing a second generally non-conductive material adjacent to the support member and the conductive couplers, with the second generally non-conductive material being spaced apart from the first generally non-conductive material.
A method in accordance with yet another aspect of the invention includes providing a first generally non-conductive material between flowable conductive couplers of a microelectronic substrate, with the first generally non-conductive material being recessed to define a flow channel having an inner region and an outer region disposed outwardly from the inner region. A second generally non-conductive material can be disposed on the support member to form a layer having a first region and a second region disposed outwardly from the first region, with the first region having a greater thickness than the second region. The inner region of the flow channel is then engaged with the first region of the second generally non-conductive material, while the second generally non-conductive material is at least partially flowable, and the microelectronic substrate and the support member are moved toward each other while forcing gas within the flow channel generally outwardly to the outer region of the flow channel.
The present disclosure describes microelectronic substrate packages and methods for forming such packages. The term “microelectronic substrate” is used throughout to include substrates upon which and/or in which microelectronic circuits or components, data storage elements or layers, and/or vias or conductive lines are or can be fabricated. Many specific details of certain embodiments of the invention are set forth in the following description and in
The support member 120 can include second connection sites 122 (such as bond pads) coupled to the first connection sites 133 with flowable, electrically conductive couplers 150. In one embodiment, the conductive couplers 150 can include solder balls (formed from solder particles disposed in a flux medium) or other conductive materials that can be reflowed after being applied to the microelectronic substrate 130 to form an electrical connection between the microelectronic substrate 130 and the support member 120. In other embodiments, the conductive couplers 150 can include other features and/or compositions. In any of these embodiments, the support member 120 can include third connection sites 121 (such as bond pads) configured to be electrically coupled to other devices and/or circuits external to the package 110.
In a further aspect of an embodiment shown in
In one embodiment, the dimensions of the fluid flow channel 161 can be selected according to design criteria that account for fluid flow rate, package geometry and/or support for the conductive couplers 150. For example, the fluid flow channel 161 can have a transverse or widthwise dimension W that is determined by the spacing between neighboring conductive couplers 150 and/or by the amount of non-conductive material 160 selected to strengthen the connection between the conductive couplers 150 and the first connection sites 133. The depthwise dimension D of the flow channel 161 can be determined based on the height of the conductive couplers 150 and/or by the amount of non-conductive material 160 selected to strengthen the connection between the conductive couplers 150 and the first connection sites 133. Based on these criteria, the fluid flow channel 161 can have a variety of dimensions, and can range from a relatively small channel (e.g., offset from the sides of neighboring conductive couplers 150 and offset the first surface 131 of the microelectronic substrate 120), to a relatively large channel (extending transversely to expose the sides of neighboring conductive couplers 150, and extending depthwise to expose the first surface 131). When the package 110 includes larger fluid flow channels 161, the non-conductive material 160 can be reduced in size to a small ring around each first connection site 133.
The package 110 can further include an optional adhesive layer 170 disposed around a periphery of the non-conductive material 160. The adhesive layer 170 can provide for an additional connection between the microelectronic substrate 130 and the support member 120 and can constrain the relative thermal expansion of these components as the temperature of the package 110 changes. In one embodiment, the adhesive material 170 can be disposed adjacent to two sides of the microelectronic substrate 130, leaving the regions adjacent to the remaining two sides of the microelectronic substrate 130 open to allow fluid to move into and/or out of the fluid flow channels 161.
) One feature of an embodiment of the package 110 described above with reference to
Another advantage of the fluid flow channels 161 is that they can provide an avenue for cooling flow to cool the components of the package 110. Accordingly, the cooling flow can be in more intimate contact with the interior portions of the package 110 than existing cooling flows that contact only the external surfaces of the microelectronic substrate 130 and/or the support member 120. As a result, the components in the package 110 may be less likely to overheat and fail at normal operating temperatures, and may be more likely to survive extreme operating temperatures.
In a further aspect of this embodiment, the non-conductive material 160 can strengthen the microelectronic substrate 130 and can accordingly allow operations on the microelectronic substrate 130 that would not be practical without the non-conductive material 160. For example, material can be removed from the second surface 132 of the microelectronic substrate 130 to thin the microelectronic substrate 130 and form a new second surface 132 a, as shown in
In either of the embodiments described above, at least a portion of the non-conductive material 160 can be removed to form the fluid flow channels 161 shown in
In one aspect of an embodiment described above with reference to
Referring now to
In one aspect of an embodiment of the package 410 described above with reference to
Another advantage of the gaps 464 is that they limit the structural connection between the microelectronic substrate 130 and the support member 120 to the link provided by the conductive couplers 150. Accordingly, the microelectronic substrate 130 can be removed from the support member 120, for example, by elevating the temperature of the conductive couplers 150, causing the conductive couplers 150 to reflow. If either the microelectronic substrate 130 or the support member 120 is defective, the defective component can be separated from the package 410 (without damaging the non-defective component) and replaced with another, comparable component.
In a further aspect of this embodiment, the outer surfaces of the conductive couplers 150 can define a plane P and the outer surface of the non-conductive material 560 can be recessed from the plane P to provide a gap 564. The gap 564 can be selectively sized such that when the microelectronic substrate 130 is connected to the support member 120 and an underflow material 540 flows into the gap 564 from a position adjacent to the microelectronic substrate 130, the underflow material 540 will tend to wick more quickly into the gap 564 than around the periphery of the microelectronic substrate 130. For example, the gap 564 can have a depth of about 25 microns in one embodiment. In other embodiments, the gap 564 can have other depths greater than or less than 25 microns. In still further embodiments, the gap 564 can have a size based on the mean diameter of particulates in the underflow material 540. For example, the gap 564 can have a depth that is about three times the mean diameter of such particulates. Suitable underflow materials 540 are available from Locktite Corp. of Rocky Hills, Conn., Nagase America Corp. of New York, N.Y., and Dexter Hysol of Seabrook, N.H.
In any of the foregoing embodiments described above with reference to
The second package 610 b can include a second support member 620 b and a second microelectronic substrate 630 b. The second microelectronic substrate 630 b can include second conductive couplers 650 b that are larger than the first conductive couplers 650 a and that define a plane P2. A second non-conductive material 660 b can be disposed in the interstices between neighboring second conductive couplers 650 b and can be recessed from the plane P2 to define a second gap 664 b.
In one aspect of an embodiment shown in
In a further aspect of this embodiment, the support member 720 can include an upper surface 723, connection sites 722 at least proximate to the upper surface 723, and a generally non-conductive, no-flow underfill material 740 disposed on the upper surface 723 and the second connection sites 722. Suitable no-flow underfill materials are available from Locktite Corp., Nagase America Corp., and Dexter Hysol Corp. The underfill material 740 can have a generally domed shape before the microelectronic substrate 730 is connected to the support member 720. Accordingly, when the microelectronic substrate 730 is brought into contact with the underfill material 740, the underfill material 740 will tend to fill the central portion of the gap 764 before filling the outer portion of the gap 764. As the microelectronic substrate 730 and the support member 720 move closer together, the underfill material 740 forces the gas in the gap 764 generally outwardly. Accordingly, as shown in
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5126829||Sep 25, 1989||Jun 30, 1992||Hitachi, Ltd.||Cooling apparatus for electronic device|
|US5249100||May 11, 1990||Sep 28, 1993||Hitachi, Ltd.||Electronic circuit device provided with a ceramic substrate having lead pins bonded thereto by solder|
|US5251100||Aug 25, 1992||Oct 5, 1993||Hitachi, Ltd.||Semiconductor integrated circuit device with cooling system and manufacturing method therefor|
|US5515912||Mar 4, 1991||May 14, 1996||Hitachi, Ltd.||Cooling apparatus of electronic devices|
|US5586004||Jan 20, 1994||Dec 17, 1996||Wavedriver Limited||Mounting assembly for power semiconductors|
|US5600203||Apr 26, 1994||Feb 4, 1997||Futaba Denshi Kogyo Kabushiki Kaisha||Airtight envelope for image display panel, image display panel and method for producing same|
|US5677566||May 8, 1995||Oct 14, 1997||Micron Technology, Inc.||Semiconductor chip package|
|US5774334||Aug 28, 1995||Jun 30, 1998||Hitachi, Ltd.||Low thermal resistant, fluid-cooled semiconductor module|
|US5864178||Jan 3, 1996||Jan 26, 1999||Kabushiki Kaisha Toshiba||Semiconductor device with improved encapsulating resin|
|US5866953||May 24, 1996||Feb 2, 1999||Micron Technology, Inc.||Packaged die on PCB with heat sink encapsulant|
|US5891753||Jan 24, 1997||Apr 6, 1999||Micron Technology, Inc.||Method and apparatus for packaging flip chip bare die on printed circuit boards|
|US5898224||Oct 22, 1997||Apr 27, 1999||Micron Technology, Inc.||Apparatus for packaging flip chip bare die on printed circuit boards|
|US5917231||Jul 9, 1997||Jun 29, 1999||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device including an insulative layer having a gap|
|US5920768||Dec 16, 1997||Jul 6, 1999||Denso Corporation||Manufacturing method for a resin sealed semiconductor device|
|US5933713||Apr 6, 1998||Aug 3, 1999||Micron Technology, Inc.||Method of forming overmolded chip scale package and resulting product|
|US5959363||Jun 9, 1998||Sep 28, 1999||Kabushiki Kaisha Toshiba||Semiconductor device with improved encapsulating resin|
|US5980977||Dec 9, 1996||Nov 9, 1999||Pinnacle Research Institute, Inc.||Method of producing high surface area metal oxynitrides as substrates in electrical energy storage|
|US5989941||Dec 12, 1997||Nov 23, 1999||Micron Technology, Inc.||Encapsulated integrated circuit packaging|
|US6037658||Oct 7, 1997||Mar 14, 2000||International Business Machines Corporation||Electronic package with heat transfer means|
|US6046496||Nov 4, 1997||Apr 4, 2000||Micron Technology Inc||Chip package|
|US6048744||Sep 15, 1997||Apr 11, 2000||Micron Technology, Inc.||Integrated circuit package alignment feature|
|US6048755||Nov 12, 1998||Apr 11, 2000||Micron Technology, Inc.||Method for fabricating BGA package using substrate with patterned solder mask open in die attach area|
|US6049125||Dec 29, 1997||Apr 11, 2000||Micron Technology, Inc.||Semiconductor package with heat sink and method of fabrication|
|US6072233||May 4, 1998||Jun 6, 2000||Micron Technology, Inc.||Stackable ball grid array package|
|US6075288||Jun 8, 1998||Jun 13, 2000||Micron Technology, Inc.||Semiconductor package having interlocking heat sinks and method of fabrication|
|US6081429||Jan 20, 1999||Jun 27, 2000||Micron Technology, Inc.||Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods|
|US6084300||Dec 8, 1997||Jul 4, 2000||Oki Electric Industry Co., Ltd.||Compact resin-sealed semiconductor device|
|US6097087||Oct 31, 1997||Aug 1, 2000||Micron Technology, Inc.||Semiconductor package including flex circuit, interconnects and dense array external contacts|
|US6107122||Aug 4, 1997||Aug 22, 2000||Micron Technology, Inc.||Direct die contact (DDC) semiconductor package|
|US6118179||Aug 27, 1999||Sep 12, 2000||Micron Technology, Inc.||Semiconductor component with external contact polymer support member and method of fabrication|
|US6122171||Jul 30, 1999||Sep 19, 2000||Micron Technology, Inc.||Heat sink chip package and method of making|
|US6129955||Jun 13, 1997||Oct 10, 2000||International Business Machines Corporation||Encapsulating a solder joint with a photo cured epoxy resin or cyanate|
|US6148509||Aug 26, 1998||Nov 21, 2000||Micron Technology, Inc.||Method for supporting an integrated circuit die|
|US6153924||Dec 13, 1999||Nov 28, 2000||Micron Technology, Inc.||Multilayered lead frame for semiconductor package|
|US6159764||Jul 2, 1997||Dec 12, 2000||Micron Technology, Inc.||Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages|
|US6163956||Jun 29, 1999||Dec 26, 2000||Micron Technology, Inc.||Method of making chip scale package with heat spreade|
|US6180504||Nov 15, 1999||Jan 30, 2001||Micron Technology, Inc.||Method for fabricating a semiconductor component with external polymer support layer|
|US6180527||Aug 9, 1999||Jan 30, 2001||Micron Technology, Inc.||Method and apparatus for thinning article, and article|
|US6180696||Feb 18, 1998||Jan 30, 2001||Georgia Tech Research Corporation||No-flow underfill of epoxy resin, anhydride, fluxing agent and surfactant|
|US6208519||Aug 31, 1999||Mar 27, 2001||Micron Technology, Inc.||Thermally enhanced semiconductor package|
|US6215175||Jul 6, 1998||Apr 10, 2001||Micron Technology, Inc.||Semiconductor package having metal foil die mounting plate|
|US6239484 *||Jun 9, 1999||May 29, 2001||International Business Machines Corporation||Underfill of chip-under-chip semiconductor modules|
|US6252772||Feb 10, 1999||Jun 26, 2001||Micron Technology, Inc.||Removable heat sink bumpers on a quad flat package|
|US6288451 *||Jun 24, 1998||Sep 11, 2001||Vanguard International Semiconductor Corporation||Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength|
|US6291267 *||Oct 15, 1999||Sep 18, 2001||International Business Machines Corporation||Process for underfilling chip-under-chip semiconductor modules|
|US6303981||Sep 1, 1999||Oct 16, 2001||Micron Technology, Inc.||Semiconductor package having stacked dice and leadframes and method of fabrication|
|US6310288||Jun 28, 2000||Oct 30, 2001||Micron Technology, Inc.||Underfill coating for loc package|
|US6310390||Apr 8, 1999||Oct 30, 2001||Micron Technology, Inc.||BGA package and method of fabrication|
|US6314639||Feb 23, 1998||Nov 13, 2001||Micron Technology, Inc.||Chip scale package with heat spreader and method of manufacture|
|US6326242||Oct 29, 1999||Dec 4, 2001||Micron Technology, Inc.||Semiconductor package with heat sink and method of fabrication|
|US6326687||Sep 1, 1998||Dec 4, 2001||Micron Technology, Inc.||IC package with dual heat spreaders|
|US6329222||Dec 20, 1999||Dec 11, 2001||Micron Technology, Inc.||Interconnect for packaging semiconductor dice and fabricating BGA packages|
|US6337513||Nov 30, 1999||Jan 8, 2002||International Business Machines Corporation||Chip packaging system and method using deposited diamond film|
|US6338980 *||Aug 1, 2000||Jan 15, 2002||Citizen Watch Co., Ltd.||Method for manufacturing chip-scale package and manufacturing IC chip|
|US6344976||Nov 29, 1999||Feb 5, 2002||Micron Technology, Inc.||Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die|
|US6351384||Aug 11, 2000||Feb 26, 2002||Hitachi, Ltd.||Device and method for cooling multi-chip modules|
|US6352881 *||Jul 22, 1999||Mar 5, 2002||National Semiconductor Corporation||Method and apparatus for forming an underfill adhesive layer|
|US6373142||Nov 15, 1999||Apr 16, 2002||Lsi Logic Corporation||Method of adding filler into a non-filled underfill system by using a highly filled fillet|
|US6459581||Dec 19, 2000||Oct 1, 2002||Harris Corporation||Electronic device using evaporative micro-cooling and associated methods|
|US6614122 *||Sep 29, 2000||Sep 2, 2003||Intel Corporation||Controlling underfill flow locations on high density packages using physical trenches and dams|
|US6673649||Jul 5, 2002||Jan 6, 2004||Micron Technology, Inc.||Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages|
|US6756685 *||Aug 1, 2002||Jun 29, 2004||Nec Electronics Corporation||Semiconductor device|
|US6790473||Jan 26, 2001||Sep 14, 2004||International Business Machines Corporation||Lead protective coating composition, process and structure thereof|
|US6794225||Dec 20, 2002||Sep 21, 2004||Intel Corporation||Surface treatment for microelectronic device substrate|
|US6908789||Dec 15, 2003||Jun 21, 2005||Intel Corporation||Method of making a microelectronic assembly|
|US6916684 *||Mar 18, 2003||Jul 12, 2005||Delphi Technologies, Inc.||Wafer-applied underfill process|
|US7015592 *||Mar 19, 2004||Mar 21, 2006||Intel Corporation||Marking on underfill|
|US7067350 *||Jan 31, 2005||Jun 27, 2006||Taiwan Semiconductor Manufacturing Company, Ltd.||Method of manufacturing a semiconductor device using electrical contacts formed in an isolation layer|
|US7129584 *||Jan 16, 2002||Oct 31, 2006||Micron Technology, Inc.||Elimination of RDL using tape base flip chip on flex for die stacking|
|US7189593 *||May 25, 2004||Mar 13, 2007||Micron Technology, Inc.||Elimination of RDL using tape base flip chip on flex for die stacking|
|US7199466 *||May 3, 2004||Apr 3, 2007||Intel Corporation||Package design using thermal linkage from die to printed circuit board|
|US7239024 *||Nov 19, 2003||Jul 3, 2007||Thomas Joel Massingill||Semiconductor package with recess for die|
|US7301222 *||Feb 12, 2003||Nov 27, 2007||National Semiconductor Corporation||Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages|
|US20030030134 *||Aug 1, 2002||Feb 13, 2003||Nec Corporation||Semiconductor device|
|US20030134450 *||Jan 16, 2002||Jul 17, 2003||Lee Teck Kheng||Elimination of RDL using tape base flip chip on flex for die stacking|
|US20040005732 *||Jul 5, 2002||Jan 8, 2004||Hiatt William Mark||Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages|
|US20040101991 *||Nov 3, 2003||May 27, 2004||Hiatt William Mark||Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages|
|US20040219713 *||May 25, 2004||Nov 4, 2004||Micron Technology, Inc.||Elimination of RDL using tape base flip chip on flex for die stacking|
|US20050194685 *||Feb 23, 2005||Sep 8, 2005||Kurt Weiblen||Method for mounting semiconductor chips and corresponding semiconductor chip system|
|US20050245060 *||May 3, 2004||Nov 3, 2005||Intel Corporation||Package design using thermal linkage from die to printed circuit board|
|US20060057774 *||Oct 11, 2005||Mar 16, 2006||Hiatt William M|
|US20060084191 *||Oct 20, 2004||Apr 20, 2006||Lu-Chen Hwan||Packaging method for an electronic element|
|US20070045870 *||Aug 10, 2006||Mar 1, 2007||Shinko Electric Industries Co., Ltd.||Semiconductor device|
|JP58335774A||Title not available|
|WO1999021226A1||Oct 19, 1998||Apr 29, 1999||Flip Chip Technologies L L C||Chip scale package using large ductile solder balls|
|U.S. Classification||438/105, 257/E23.129, 257/E23.098, 257/E21.503, 438/107, 438/106|
|International Classification||H01L23/467, H01L21/56, H01L23/31, H01L21/00|
|Cooperative Classification||H01L2224/10126, H01L2224/13022, H01L24/29, H01L2224/32225, H01L24/83, H01L2224/92125, H01L23/473, H01L2924/01005, H01L23/3157, H01L2224/83102, H01L2924/01075, H01L21/563, H01L2924/01074, H01L2924/01015, H01L2924/01039, H01L23/467, H01L2924/01033, H01L2224/83194, H01L2224/83192, H01L2224/83191, H01L23/3107, H01L23/3114, H01L2224/73203, H01L2224/73204, H01L2224/16225|
|European Classification||H01L24/28, H01L23/31H, H01L23/467, H01L23/473, H01L21/56F, H01L23/31H1, H01L23/31P|