|Publication number||US7475302 B2|
|Application number||US 10/945,056|
|Publication date||Jan 6, 2009|
|Filing date||Sep 20, 2004|
|Priority date||Aug 6, 2003|
|Also published as||US20050039084|
|Publication number||10945056, 945056, US 7475302 B2, US 7475302B2, US-B2-7475302, US7475302 B2, US7475302B2|
|Inventors||Richard W. Adkisson, Gary B. Gostin|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (22), Non-Patent Citations (1), Referenced by (1), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation-in-part of the following co-pending United States nonprovisional patent application(s): (i) “GENERAL PURPOSE PERFORMANCE COUNTER,” application Ser. No. 10/635,083, filed on Aug. 6, 2003, in the name(s) of Richard W. Adkisson and Tyler J. Johnson now U.S. Pat. No. 7,424,397; and (ii) “MATCH CIRCUIT FOR PERFORMANCE COUNTER,” application Ser. No. 10/635,373, filed Aug. 6, 2003, in the name(s) of Richard W. Adkisson and Tyler J. Johnson now U.S. Pat. No. 7,331,003 ; both of which are hereby incorporated by reference in their entirety.
This application is related to U.S. patent application Ser. No. 10/635,103, filed Aug. 6, 2003 entitled “DATA SELECTION CIRCUIT FOR PERFORMANCE COUNTER”, now U.S. Pat. No. 7,404,112, and U.S. patent application Ser. No.: 10/635,079, filed Aug. 6, 2003 entitled “ZEROING CIRCUIT FOR PERFORMANCE COUNTER”, now U.S. Pat. No. 7,430,696, both of which are hereby incorporated by reference in their entirety.
Increasing demand for computer system scalability (i.e., consistent price and performance and higher processor counts) combined with increases in performance of individual components continues to drive systems manufacturers to optimize core system architectures. One such systems manufacturer has introduced a server system that meets these demands for scalability with a family of application specific integrated circuits (“ASICs”) that provide scalability to tens or hundreds of processors, while maintaining a high degree of performance, reliability, and efficiency. The key ASIC in this system architecture is a cell controller (“CC”), which is a processor-I/O-memory interconnect and is responsible for communications and data transfers, cache coherency, and for providing an interface to other hierarchies of the memory subsystem.
In general, the CC comprises several major functional units, including one or more processor interfaces, memory units, I/O controllers, and external crossbar interfaces all interconnected via a central data path (“CDP”). Internal signals from these units are collected on a performance monitor bus (“PMB”). One or more specialized performance counters, or performance monitors, are connected to the PMB and are useful in collecting data from the PMB for use in debugging and assessing the performance of the system of which the CC is a part. Currently, each of the performance counters is capable of collecting data from only one preselected portion of the PMB, such that the combination of all of the performance counters together can collect all of the data on the PMB. While this arrangement is useful in some situations, there are many situations in which it would be advantageous for more than one of the performance counters to access data from the same portion of the PMB. Additionally, it would be advantageous to be able to use the performance counters in the area of determining test coverage. Finally, it would be advantageous to be able to use the performance counters to match arbitrary combinations of patterns aligned on block boundaries. These applications are not supported by the state-of-the-art performance counters.
In one embodiment, the invention is directed to a match circuit connected to a bus carrying data. The match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit comprising a decoded_match signal indicative of whether the decoded_sum signal and the mask signal match.
In the drawings, like or similar elements are designated with identical reference numerals throughout the several views thereof, and the various elements depicted are not necessarily drawn to scale.
In general, the AND/OR circuit 201 enables access to all of the bits of the debug_bus signal coming into the performance counter 200 via the observability bus 104. In one embodiment, as illustrated in
When the match/threshold circuit 202 is operating in “match” mode, a match portion 300 (
The embodiment described herein enhances the normal match with an “R” term without using any control bits in addition to mmask (the mask) and threshold (the match). This embodiment can be used for any match circuit and for any pattern recognition; it is not limited to performance counters. In particular, a match occurs if any “R” bit is a one. This is the equivalent of an ORing of all “R” input bits. If all “R” bits are zero, there is no match.
The match_thresh_event signal is one of the two bits appended to the debug_bus signal. In the illustrated embodiment, N is equal to 16.
In general, when the match/threshold circuit 202 is operating in match mode, the match portion 300 detects in the debug_bus signal any arbitrary binary pattern of up to N bits aligned on 10-bit block boundaries. This includes matching a one, zero, or “don't care” (“X”) on any bit. Additionally, as indicated above, in one embodiment, the detecting includes matching the results of an “OR” operation on all designated bits (“R”). This allows detection of specific packets or specific groups of packets or states.
In one embodiment, the match portion 300 comprises an exclusive NOR (“XNOR”) circuit, represented in
The match circuit 300 further includes an enhancement portion 301 d for matching the “R” bits. The enhancement portion 301 d includes an AND circuit, represented in
The match circuit 300 further includes a decoded match portion 301 j. In the decoded match portion 301 j, a sum[5:0] field, comprising the lowest six bits of a selected[15:0] field output from the sm_sel circuit 204, is input to a decoder 301 k, the output of which is a decoded_sum signal comprising 64 “one hot” signals. It will be recognized that if the value of sum[5:0] is equal to x, then bit x of the decoded_sum signal will be “hot” or active and the remaining bits will be zero. For example, if sum[5:0] is 000011, then decoded_sum will be high and decoded_sum[63:4] and decoded_sum[2:0] will be low. The decoded_sum signal is ANDed with a 64-bit mask designated “mask[63:0]” via an AND circuit comprising 64 two-input AND gates, represented by an AND gate 3011. The output of the AND circuit 3011 is input to a 64-input OR gate 301 m, the output of which comprises a decoded_match signal that is activated if any of the “one hots” of the decoded_sum signal designated by mask[63:0] is active. The decoded_match signal is input to a second input of the MUX 301 i. A control signal designated as decode_match_mode from a CSR 301 n controls operation of the MUX 301 i to output either the output of the AND gate 301 h (when the decode_match_mode control signal is deactivated and the match portion 300 is not operating in decode match mode) or the output of the OR gate 301 m (when the decode_match_mode signal is activated and the match portion 300 is operating in decode match mode) as a match signal.
The match signal output from the MUX 301 i is input to a first input of a MUX 301 o. When the match/threshold circuit 202 is operating in match mode (as controlled by a selection control signal, e.g., the match/thresh# control signal), the match signal is output from the MUX 301 o as the match_thresh_event signal to the AND/OR circuit, as described above.
As a result of the operation of the match portion 300, no extra random logic is required for decoding packets or states into “one-hot” signals, which are 1-bit signals that transition to a logic “1” for each value of the state. The match/threshold circuit 202 requires an N-bit pattern field and an N-bit mask field. In addition, the embodiment described herein can match a wider range of patterns than a conventional match circuit, which corresponds to a level of AND gates. The enhancement portion 301 d adds a level of OR gates to the AND gates. For example, a conventional match circuit matches if all “1” bits are one, all “0” bits are zero, and all other bits are “don't care”. The enhancement portion 301 d generates a match if all “1” bits are one, all “0” bits are zero, all “X” bits are “don't care”, and at least one of the “R” bits is one. The decoded match circuit portion 301 j adds the ability to match arbitrary combinations of patterns within the data with a single performance counter.
The ability of the decoded match portion 301 j to match arbitrary patterns of patterns will be described in greater detail below. In particular, it will be recognized that an n-bit input at the decoder 301 k produces 2n patterns. Accordingly, 2P combinations can occur, where P is equal to 2n. As an example, assuming n is equal to 2, there are 22, or 4, patterns (0, 1, 2, or 3), and 24, or 16, combinations of patterns. The decoded match portion 301 j enables the match circuit 300 to match all 16 combinations of patterns produced by a 2-bit input the decoder 301 k. These 16 possible combinations are set forth in Table I below:
match 0 or 1
match 0 or 2
match 0 or 3
match 1 or 2
match 1 or 3
match 2 or 3
match 0 or 1 or 2
match 0 or 2 or 3
match 0 or 1 or 3
match 1 or 2 or 3
match 0 or 1 or 2 or 3
Assuming that n is equal to 6, as in the illustrated embodiment, 2n, or 64, patterns can be produced; accordingly, 264, or 1.8447×1019, combinations can be matched by the decoded match portion 301 j.
An example of the usefulness of the embodiment of the match portion 300 including the decoded match portion 301 j is as follows. Given bits specifying a transaction type and four additional bits each indicating one of four destinations, a conventional match circuit cannot indicate a “match” if the specification transaction type is sent to any one of the four destinations. The embodiment illustrated herein can accomplish this result by using an “R” term for the four destination bits. As a result, the embodiment illustrated herein can add a level of logic without using any more control bits, thus allowing more patterns to be matched.
To reduce the number of control bits required, in the embodiment illustrated in
The decoded match portion 301 j enables the match circuit 300 to match arbitrary combinations of patterns. For example, if there is a six-bit field and one wishes to match a 0×1e, 0×25, 0×1a, 0×3f, 0×00, or a 0×07, then the circuit 300 can accomplish this. This example is typical of the case in which one wishes to count certain sets of transaction types. This can be accomplished with N counters, but typically, the number of counters is limited. This invention enables such counting to be accomplished with a single counter.
As alluded to previously, with a six-bit field, 26=64 patterns can be produced. The decoded matching embodiment described herein can match none, one, two, three, and so on up to all 64 of them. Specifically, there are 264=1.8447E19 combinations and the illustrated embodiment can match any of them.
When the match/threshold circuit 202 is operating in “threshold” mode, the threshold portion 302 of the circuit 202 activates the match_thresh_event signal to the AND/OR circuit 201 when an S-bit portion of the debug_bus signal selected and zeroed as described in greater detail below with reference to the sm_sel circuit 204 and the szero circuit 206 is equal to or greater than the threshold. In the illustrated embodiment, S is equal to N/2, or 8.
A compare circuit 303 of the threshold portion 302 compares a sum[7:0] signal output from the szero circuit 206, described below, with the least significant S bits of the N-bit threshold signal and outputs a logic one if the former is greater than or equal to the latter and a zero if it is not. The output of the compare circuit 303 is input to a second input of the MUX 301 o as a thresh signal. When the match/threshold circuit 202 is operating in threshold mode, the thresh signal is output from the MUX 301 o as the match_thresh_event signal to the AND/OR circuit, as described above.
The sm_sel circuit 204 selects an N-bit portion of the debug_bus signal aligned on a selected 10-bit block boundary into both the match portion 300 and the threshold portion 302 (
Additional details regarding the operation of the sm_sel circuit 204 and the szero circuit 206 are provided in U.S. patent application Ser. No.: 10/635,103, filed Aug. 6, 2003 entitled “DATA SELECTION CIRCUIT FOR PERFORMANCE COUNTER” and U.S. patent application Ser. No.: 10/635,079, filed Aug. 6, 2003 entitled “ZEROING CIRCUIT FOR PERFORMANCE COUNTER”.
In one embodiment, each general purpose performance counter, such as the performance counter 200, is 48 bits plus overflow. The performance counter 200 is general purpose in that it looks at all D bits of the debug_bus signal for an event mask plus two extra events, eight separate selections of 16 bits for the match compare operation and eight separate selections of eight bits for the threshold compare and the accumulate operations. The eight bits for the threshold compare and the accumulate operations are the bottom eight bits of the 16 bits selected for the match compare operation. Those 16 bits are aligned to 10 slot boundaries as shown in an exemplary mapping arrangement illustrated in
As best illustrated in
Referring again to
Continuing to refer to
Referring again to
The outputs of the AND portion of the first logic stage 304 are input to an 82-input OR gate 306, the output of which is input to one input of a two-input MUX 308 as an “or_result”. Similarly, the outputs of the OR portion of the first logic stage 304 are input to an 82-input AND gate 310, the output of which is input to the other input of the MUX 308 as an “and_result”. A control signal (“and/or#”) which may originate from a CSR (not shown) controls whether the AND/OR circuit 201 functions in AND mode, in which case the and_result is output from the MUX 308 as the inc signal, or in OR mode, in which case the or_result is output from the MUX as the inc signal.
As a result, when the AND/OR circuit 201 is operating in the AND mode, the inc signal comprises the and_result signal and will be activated when all of the bits of the events signal 400 that are of interest as specified by the composite mask 410 are set. When the AND/OR circuit 201 is operating in OR mode, the inc signal comprises the or_result signal and will be activated when any one of the bits of the events signal 400 that are of interest as specified by the composite mask 410 is set.
The acc bit 416 of the composite mask 410 is CSR-settable. Setting the TM bit 414 in the composite mask 410 designates the match_thresh_event signal in the events signal as a bit of interest; not setting the TM bit in the composite mask will cause the value of the match_thresh_event signal in the events signal 400, and hence the result of any match or threshold operation performed by the match/threshold circuit 202, to be ignored.
Continuing to refer to
An AND circuit, represented by an AND gate 320, bit-wise ANDs the signals output from the replicator 316 and from the MUX circuit 318. The resulting 8-bit signal is input to a register 322. An adder 324 adds the 8-bit signal stored in the register 322 to the 48-bit sum stored in the count value register 312. The new sum output from the adder 324 is input to a MUX circuit 326. Two other sets of inputs to the MUX circuit 326 are connected to a logic zero and a csr_write_value, respectively. When a csr_write enable signal to the MUX circuit 326 is activated, the value of csr_write_value is output from the MUX circuit 326 and written to the count value register 312. In this manner, a value can be loaded into the count value register 312. Similarly, when the clear_counter signal is asserted, 48 zero bits are output from the MUX circuit 326 to the count value register 312, thereby clearing the register.
If neither the csr_write signal nor the clear_counter signal is asserted and the acc signal is asserted, the output of the adder 324 is written to the count value register 312, thereby effectively adding S bits (i.e., the value of the sum[7:0] signal) to the previous value of the count value register 312. Not enabling the counter circuit 208 results in the count value register 312 being held at its current value. Finally, to increment the value of the count value register 312 by one, the counter circuit 208 must be enabled, the inc signal must be asserted, and the acc signal must not be asserted.
As described in detail above,
Previous performance counters could only match ones or use thresholding. The embodiment described herein, using the match portion 300 of the match/threshold circuit 202, can match ones, zeros, “don't care”, and “ORed” bits. It can also match groups of packets and states. For example, it can match all packets with a “ROXR1” pattern in bit positions 6 through 2 regardless of the values of the other bits or bit 4. It eliminates the need for the logic being analyzed (i.e., debugged, performance-counted, or test-covered, et cetera) to have extra logic to decode specific patterns into one-hot signals, rendering a performance counter in which it is implemented more general purpose.
As previously mentioned, prior art performance counter designs were not general purpose, in that they have limited range and are designed solely for performance calculations and debug of a system design. The embodiments described herein are general purpose, in that the AND/OR circuit can perform calculations on the entire range of the data collection bus 104. The embodiments also incorporate the concept of coverage. In particular, by observing specific states in a logic design, the designer can determine how much of the state space thereof is being covered by the test vectors of a test suite. The designer can thereby gauge whether more tests need to be run and what needs to be added to fully test the entire design.
An implementation of the invention described herein thus provides a match circuit operable with a general purpose performance counter. The embodiments shown and described have been characterized as being illustrative only; it should therefore be readily understood that various changes and modifications could be made therein without departing from the scope of the present invention as set forth in the following claims. For example, while the embodiments are described with reference to an ASIC, it will be appreciated that the embodiments may be implemented in other types of ICs, such as custom chipsets, Field Programmable Gate Arrays (“FPGAs”), programmable logic devices (“PLDs”), generic array logic (“GAL”) modules, and the like. Furthermore, while the embodiments shown may be implemented using CSRs, it will be appreciated that control signals may also be applied in a variety of other manners, including, for example, directly or may be applied via scan registers or Model Specific Registers (“MSRs”). Additionally, although specific bit field sizes have been illustrated with reference to the embodiments described, e.g., 16-bit threshold for pattern matching (where the bottom 8 bits are used for the threshold), 80-bit mask signal, 3-bit sm_sel, et cetera, various other implementations can also be had.
Accordingly, all such modifications, extensions, variations, amendments, additions, deletions, combinations, and the like are deemed to be within the ambit of the present invention whose scope is defined solely by the claims set forth hereinbelow.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5651112||Feb 22, 1996||Jul 22, 1997||Hitachi, Ltd.||Information processing system having performance measurement capabilities|
|US5796633||Jul 12, 1996||Aug 18, 1998||Electronic Data Systems Corporation||Method and system for performance monitoring in computer networks|
|US5835702||Oct 21, 1996||Nov 10, 1998||International Business Machines Corporation||Performance monitor|
|US5881223||Sep 6, 1996||Mar 9, 1999||Intel Corporation||Centralized performance monitoring architecture|
|US5887003 *||Sep 10, 1996||Mar 23, 1999||Hewlett-Packard Company||Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results|
|US6112317||Mar 10, 1997||Aug 29, 2000||Digital Equipment Corporation||Processor performance counter for sampling the execution frequency of individual instructions|
|US6112318||Aug 11, 1997||Aug 29, 2000||Digital Equipment Corporation||Performance counters controlled by programmable logic|
|US6360337||Jan 27, 1999||Mar 19, 2002||Sun Microsystems, Inc.||System and method to perform histogrammic counting for performance evaluation|
|US6463553||Oct 1, 1999||Oct 8, 2002||Stmicroelectronics, Ltd.||Microcomputer debug architecture and method|
|US6487683||Oct 1, 1999||Nov 26, 2002||Stmicroelectronics Limited||Microcomputer debug architecture and method|
|US6502210||Oct 1, 1999||Dec 31, 2002||Stmicroelectronics, Ltd.||Microcomputer debug architecture and method|
|US6519310 *||Mar 28, 2001||Feb 11, 2003||Intel Corporation||Hardware event based flow control of counters|
|US6539502 *||Nov 8, 1999||Mar 25, 2003||International Business Machines Corporation||Method and apparatus for identifying instructions for performance monitoring in a microprocessor|
|US6546359||Apr 24, 2000||Apr 8, 2003||Sun Microsystems, Inc.||Method and apparatus for multiplexing hardware performance indicators|
|US6557119||Oct 1, 1999||Apr 29, 2003||Stmicroelectronics Limited||Microcomputer debug architecture and method|
|US6615370||Oct 1, 1999||Sep 2, 2003||Hitachi, Ltd.||Circuit for storing trace information|
|US6684348||Oct 1, 1999||Jan 27, 2004||Hitachi, Ltd.||Circuit for processing trace information|
|US6732307||Oct 1, 1999||May 4, 2004||Hitachi, Ltd.||Apparatus and method for storing trace information|
|US7404112 *||Aug 6, 2003||Jul 22, 2008||Hewlett-Packard Development Company, L.P.||Data selection circuit for performance counter|
|US7430696 *||Aug 6, 2003||Sep 30, 2008||Hewlett-Packard Development Company, L.P.||Zeroing circuit for performance counter|
|US20050038930 *||Sep 12, 2002||Feb 17, 2005||Klaus-Dieter Meier||Bus station|
|WO2003032174A2 *||Sep 12, 2002||Apr 17, 2003||Robert Bosch Gmbh||Bus station|
|1||*||Meier et al. Bus Station, English translation of WO2003032174 and Figures, Publication Date Apr. 17, 2003, 9 pages.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20120226839 *||Jan 11, 2012||Sep 6, 2012||Texas Instruments Incorporated||Method and System for Monitoring and Debugging Access to a Bus Slave Using One or More Throughput Counters|
|U.S. Classification||714/724, 714/733, 710/113|
|International Classification||H04B1/74, G06F13/36, G01R31/28|
|Cooperative Classification||G06F11/364, G06F2201/88, G06F11/348|
|Sep 20, 2004||AS||Assignment|
Owner name: HEWLETTT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ADKISSON, RICHARD W.;GOSTIN, GARY B.;REEL/FRAME:015821/0089
Effective date: 20040915
|May 19, 2009||CC||Certificate of correction|
|Aug 20, 2012||REMI||Maintenance fee reminder mailed|
|Jan 6, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Feb 26, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130106