|Publication number||US7483306 B2|
|Application number||US 11/670,626|
|Publication date||Jan 27, 2009|
|Filing date||Feb 2, 2007|
|Priority date||Feb 2, 2007|
|Also published as||US20080186786|
|Publication number||11670626, 670626, US 7483306 B2, US 7483306B2, US-B2-7483306, US7483306 B2, US7483306B2|
|Inventors||Yung Feng Lin|
|Original Assignee||Macronix International Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Non-Patent Citations (1), Referenced by (7), Classifications (16), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to semiconductor memory devices, and more particularly to sensing schemes for such devices.
Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. A typical memory device comprises a number of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit.
Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell. According to one particular embodiment, the current drawn by a particular memory cell is ascertained by connecting the drain terminal of the memory cell to a sensing circuit, where the source terminal of the memory cell is connected to ground, and the gate of the memory cell is selected. The sensing circuit attempts to detect the current drawn by the memory cell, by comparing the sensed memory cell current against a reference current. If the sensed memory cell current exceeds the reference current, the memory cell is considered an erased cell (e.g., corresponding to a “1” bit). If the sensed memory cell current is below the reference current, the memory cell is considered a programmed cell (e.g., corresponding to a “0” bit).
In practice, it is desirable to have the sensed memory cell current be greater than or less than the reference current by a sufficient margin (referred to herein as the “read margin” in the present application) so as to accurately identify the charge level stored by the memory cell. However, when high density memory devices are implemented with a low supply voltage (“VCC”), such as 1.8 volts, for example, the read margin is significantly reduced. When the read margin is significantly reduced, the reliability of sensing the memory cell current also decreases. The reliability and accuracy of the read operation are thus reduced, resulting in poor performance of the memory device.
Accordingly, there is a strong need in the art to overcome deficiencies of known sensing circuits and to provide a fast and accurate sensing circuit and technique for low voltage semiconductor memory devices.
Roughly described, the invention involves a sensing circuit for a target memory cell, in which the target cell draws a target cell current from a first node in response to selection of the target cell. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node in response to selection of the reference cell, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node. Embodiments of the invention can thus achieve both a wide read margin and a fast read time.
The invention will be described with respect to particular embodiments thereof, and reference will be made to the drawings, in which:
The following detailed description is made with reference to the figures. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.
In a low supply voltage environment, however, the arrangement of
The arrangement of
Similarly on the reference side, the source of an N-channel reference cell 420 is connected to ground. The drain 422 of this cell is connected, again through cell selection circuitry, optional cascode circuitry as well as perhaps other circuitry, to a node 424, such that the cell 420 is drawing a current Iref from the node 424. The value of the current Iref is, in the usual manner, in between the value drawn by target cell 410 when it is in the program state and the value drawn by target cell 410 when it is in the erased state.
The node 414 is connected to one input 442 of a current difference generator 440, and the node 424 is connected to a second input 444 of the current difference generator 440. The current difference generator 440 has an output 446 which carries a current that is positively dependent on the difference between the current on input terminal 442 and the current on input terminal 444. The current difference generator 440 also has a second output 448, which carries a current that is negatively dependent on the difference between the current on input terminal 442 and the current on input terminal 444. As used herein, an output current is “positively dependent” upon an input current if, throughout its operating range, an increase in the input current yields an increase in the output current; that is, there is no sign change. An output current is “negatively dependent” upon an input current if, throughout its operating range, an increase in the input current yields a decrease in the output current. Preferably in both cases in
The output terminal 446 of current difference generator 440 is connected to an SD node 450, which is connected to the inverting input 434 of a second stage sense amplifier 430. Similarly, the output terminal 448 of the current difference generator 440 is connected to an SR node 452, which is connected to the non-inverting input 436 of the second stage sense amplifier 430. The second stage a sense amplifier 430 has a high equivalent input impedance on its inverting input 434, which effectively converts the current flowing into node 450 into a voltage. Similarly, the second stage sense amplifier 430 has a high equivalent input impedance on its non-inverting input 436, which effectively converts the current flowing into node 452 into a voltage. The second stage sense amplifier 430 also has a sense enable input, in response to which the amplifier 430 will amplify the difference between the voltages on its two inputs. The circuit of
The current difference generator 440 can be designed using a variety of different kinds of circuitry, as will be apparent to the reader.
As used herein, a current value can be positive or negative, and depends on an arbitrarily defined current flow “direction”. That is, a positive current flow from a node A toward a node B in a circuit is the same as a negative current flow from node B toward node A. Similarly, when current is said to be “drawn from” a particular node, this language by itself does not require that the current be positive when drawn from the particular node. The current “drawn from” the particular node can be negative, which would be the same as saying that a positive current is flowing into the particular node. In the same way, nor does a current said to be “driven into” a particular node require that the current be positive when driven into the particular node. Finally, the labeling of a current mirror terminal as an “input” or an “output” does not define either its current flow direction or its current flow sign. It merely differentiates between controlling terminals (labeled “inputs”) and controlled terminals (labeled “outputs”).
In operation, N-channel current mirror 540 draws into its output 544 current equal to the reference cell current Iref. This current is drawn from the output terminal 446 of current difference generator 440, which also receives a current equal to the target cell current Icell. Thus the current flowing into SD node 450 (
The P-channel current mirrors 510 and 520 can be designed using a variety of different kinds of circuitry, as will be apparent to the reader.
The N-channel current mirrors 530 and 540 also can be designed using a variety of different kinds of circuitry, as will be apparent to the reader.
As used herein, a given signal, event or value is “responsive” to a predecessor signal, event or value if the predecessor signal, event or value influenced the given signal, event or value. If there is an intervening processing element, step or time period, the given signal, event or value can still be “responsive” to the predecessor signal, event or value. If the intervening processing element or step combines more than one signal, event or value, the signal output of the processing element or step is considered “responsive” to each of the signal, event or value inputs. If the given signal, event or value is the same as the predecessor signal, event or value, this is merely a degenerate case in which the given signal, event or value is still considered to be “responsive” to the predecessor signal, event or value. “Dependency” of a given signal, event or value upon another signal, event or value is defined similarly.
The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. For example, the invention may also be viewed as a method for sensing a charge level on a target memory cell, by performing the steps that are performed by the circuitry described herein. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.
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|U.S. Classification||365/185.21, 365/207, 365/208|
|International Classification||G11C7/02, G11C16/06|
|Cooperative Classification||G11C2207/063, H03F2203/45096, H03F2200/91, G11C16/28, G11C7/062, H03F3/45273, H03F2200/462, H03F2203/45098|
|European Classification||H03F3/45S1B9, G11C7/06C, G11C16/28|
|Feb 2, 2007||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, YUNG FENG;REEL/FRAME:018848/0434
Effective date: 20070124
|Feb 9, 2007||AS||Assignment|
Owner name: GEMFIRE CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BULTHUIS, HINDRICK F.;BEELEN, GUNTER B.L.;REEL/FRAME:018876/0979
Effective date: 20070209
|Sep 4, 2007||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, YUNG F.;REEL/FRAME:019865/0560
Effective date: 20070124
|Jun 4, 2012||FPAY||Fee payment|
Year of fee payment: 4