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Publication numberUS7485536 B2
Publication typeGrant
Application numberUS 11/326,178
Publication dateFeb 3, 2009
Filing dateDec 30, 2005
Priority dateDec 30, 2005
Fee statusPaid
Also published asUS20070155142
Publication number11326178, 326178, US 7485536 B2, US 7485536B2, US-B2-7485536, US7485536 B2, US7485536B2
InventorsBeen-Yih Jin, Brian S. Doyle, Robert S. Chau, Jack T. Kavalieros
Original AssigneeIntel Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers
US 7485536 B2
Abstract
A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
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Claims(4)
1. A method comprising:
forming a channel region between a source region and a drain region in a layer on a substrate, a material of the channel region comprising a first dopant profile;
forming a first barrier layer between the channel region and a well of the substrate, the first barrier layer comprising a second dopant profile different from the first dopant profile wherein the first dopant profile and the second dopant profile comprise a similar carrier;
defining the source region and the drain region such that the source region and the drain region extend through the first barrier layer;
forming a second barrier layer between the source region and the well and between the drain region and the well; and
forming a source material in the source region and a drain material in the drain region and the channel and the drain material and the channel,
wherein the second barrier layer is disposed between the source material and the channel and the drain material and the channel, and
wherein the second barrier layer comprises a dopant profile different than a dopant profile of a material of the well and a dopant profile of each of the material of the source region and the material of the drain region.
2. The method of claim 1, wherein forming the barrier layer comprises atomic layer deposition processing.
3. The method of claim 1, where the dopant profile of the material of the well and the dopant profile of the material of the source material and the material of the drain material comprise a similar carrier.
4. The method of claim 1, wherein forming the second barrier layer comprises atomic layer deposition processing.
Description
BACKGROUND

1. Field

Circuit devices and methods for forming circuit devices.

2. Background

A metal oxide semiconductor field effect transistor (MOSFET) is a common element of an integrated circuit such as a microprocessor or other circuit. The transistor typically includes a source and drain junction region formed in a semiconductor substrate and a gate electrode formed on a surface of the substrate. A gate length is generally the distance between the source and drain junction region. Within the substrate, the region of the substrate beneath the gate electrode and between the source and drain junctions is generally referred to as a channel with a channel length being the distance between the source and drain junctions.

A transistor device works generally in the following way. Carriers (e.g., electrons, holes) flow between source junction and drain junction by the establishment of contacts to the source and drain regions. In order to establish the carrier flow, a voltage is applied to the gate electrode to form an inversion layer of carriers in the channel. The minimum amount of gate voltage is generally referred to as a threshold voltage (Vt).

As noted above, many transistor devices are formed in a semiconductor substrate. The substrate body may be a bulk silicon substrate or a silicon on insulator (SOI) substrate. To form ohmic contacts to carriers in the channel, dopants are introduced (e.g., via ion implantation) into the substrate. Representatively, an N-type transistor device may have source and drain regions (and gate electrode) doped with an N-type dopant such as arsenic or phosphorous. The N-type regions are formed in a well that has previously been formed in the semiconductor substrate as a P-type conductivity. A suitable P-type dopant is boron.

The silicon and SOI body described above are designed to be fully depleted (i.e., removing of essentially all bulk charge carriers by an electric field). Fully depleted FET transistors tend to have better gate control on a channel potential than planar MOSFET devices at low drain bias VDS. Full depletion however, does not ensure better short-channel effects (SCEs) at high VDS as the drain electric field can reach the source end through the substrate in bulk silicon wafers or through a buried oxide (BOX) layer in SOI wafers. In general, it is desired that SCEs are low such that the transistor off-state leakage current, IOFF, (i.e., a current flowing between source and drain regions when a transistor is in an off state) remains as low as possible. SCEs may be determined by monitoring the subthreshold slope (SS) and drain induced barrier lowering (DIBL). Subthreshold slope, which is a measure of the gate coupling to the channel potential, is defined as SS=dVG/d[logIDS], where VG is the gate voltage and IDS is the drain-to-source current. DIBL, which is a measure of the threshold voltage shift versus drain bias, is defined as DIBL=(VTLIN−VTSAT)/(VDSAT−VDLIN). VTLIN is the linear threshold voltage at low drain bias VDLIN, typically 50 mV. VTSAT is the saturate threshold voltage at high drain bias VDSAT, which is typically in the range of from 1 to 1.2V for current generation of logic transistors. A steeper SS and/or reduced DIBL shift indicates lower IOFF.

Reduced drain-to-source coupling leads to better SCEs. Drain field penetration (i.e., drain-to-source coupling), may be reduced by scaling the substrate body size (e.g., thin body width WSI for double-gated transistors such as FinFETs, and thin TSI and WSI for triple-gated transistors such as tri-gates) or by introducing heavy doping in the source tip to channel and channel to drain tip junctions of bulk Si wafers or the Si body in SOI wafers. Very small body dimensions, however, are not desirable because of a potential for large external resistance (REXT).

In addition, heavy doping in the source tip to channel and channel to drain tip junctions is generally achieved by locally implanted dopants (P-type in N-type metal oxide semiconductor FETs (NMOSFETs) and N-type dopants in P-type metal oxide semiconductor FETs (PMOSFETs) introduced in the substrate body and in the case of the SOI substrate, in the Si body. Such implants are referred to as “halo” implants. Typical halo implants for NMOSFETs include boron and indium (In)). Halo implants for PMOSFETs include arsenic (As), antimony (Sb), and phosphorous (P). These halos are typically implanted at an angle resulting in potential overlap between the halos and source/drain (S/D) regions and/or tip regions. These Halo implant are more difficult to implement in a nonplanar FINFET or TRI-Gate configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, aspects, and advantages of the invention will become more thoroughly apparent from the following detailed description, appended claims, and accompanying drawings in which:

FIG. 1 shows a schematic side view of a portion of a circuit substrate having a barrier layer formed on a surface thereof and an active layer formed on a barrier layer.

FIG. 2 shows a top perspective view of the structure of FIG. 1 after following the formation of trench isolation structures.

FIG. 3 shows the structure of FIG. 2 following the formation of a gate dielectric and gate electrode (with a dielectric etch stop on the gate electrode) on the structure.

FIG. 4 shows a cross-sectional side view through lines 4-4′ of FIG. 3 and the formation of sidewall spacers adjacent the gate electrode.

FIG. 5 shows the structure of FIG. 4 following the definition of source and drain regions in the substrate adjacent the gate electrode.

FIG. 6 shows the structure of FIG. 5 following the formation of source and drain regions in the substrate (and removal of the dielectric etch stop).

FIG. 7 shows a computer system including a microprocessor having transistors formed according to an embodiment shown in FIGS. 1-6.

DETAILED DESCRIPTION

In the following description, a transistor device is described as is a method of forming the transistor device utilizing layer-by-layer growth of in-situ doped at the layers by atomic layer deposition.

FIG. 1 shows a side view of a portion of a circuit substrate. Structure 100 may form part of a wafer in which multiple chips or die will be formed. Structure 100 includes substrate 110 of a single crystal semiconductor material, representatively silicon. In one embodiment, substrate 110 is a P-type doped substrate, for example, a silicon substrate doped with boron. The following description details the formation of a P-type device (e.g., a PMOS). It is appreciated that similar techniques may be used to form an N-type device (e.g., an NMOS) by, for example, modifying the dopant species.

Overlying substrate 110 in FIG. 1 is barrier layer 120 of an intrinsic or n++ type material and active layer 130 of an n type material (where “n++” of barrier layer 120 indicates a greater concentration of dopant than “n” of active layer 130).

As will become clear later, a portion of active layer 130 will serve as a transistor device channel. In this embodiment, barrier layer 120 is selected of a material and thickness to inhibit off-state interface leakage of a transistor device. Representatively, barrier layer 120 and active layer 130 are each epitaxial layers formed in situ by an atomic layer deposition (ALD) process. Generally speaking, an atomic layer deposition process involves forming a film or layer in a layer-by-layer process by exposing a surface to alternating pulses of reactants, each of which undergoes a self-limiting reaction, generally resulting in controlled film deposition. In one embodiment, barrier layer 120 and active layer 130 are of a similar carrier (e.g., N-type) but the dopant profile is changed. In one embodiment, using an atomic layer deposition process, by alternating pulsing of chemical reaction precursors (e.g., silane, phosphine, methylsilane, etc.), dopant gas and hydrogen gas, barrier layer 120 is, for example, a carbon-doped n++ material and active layer 130 is an n material.

As an example, a phosphine, arshine or antimony (Sb) source pulse width and flow rate determines the thicknesses and concentration profile of barrier layer 120 and active layer 130. A deposition temperature ranges from 450° C. to 900° C., and the pressure ranges from 10 torr to one atmosphere. Typical thicknesses for barrier layer 120 and active layer 130 are 10 angstroms (Å) to 100 Å, and 100 Å to 500 Å, respectively. The doping level of barrier layer 120 can be similar to a doping of a halo implant, while the doping level of active layer 130 can be similar to a well implant commonly used in planar MOSFET devices.

FIG. 2 shows the structure of FIG. 1 following the formation of trench isolation structures 140 in the substrate. In one embodiment, trench isolation structures 140 are formed by first defining the trench area using photolithographic and etching techniques (e.g., protecting a defined area of active layer 130), followed by a deposition (e.g., chemical vapor deposition (CVD)) of a dielectric material such as silicon dioxide. FIG. 2 shows trench isolation 140 formed in substrate 110 adjacent (on opposite sides) of a defined are of active layer 130 over barrier layer 120. In one embodiment, a width dimension, W, of active layer 130 is selected to define a gate width of a transistor device.

FIG. 3 shows the structure of FIG. 2 following the formation of a gate dielectric and gate electrode over active layer 130. In one embodiment, gate dielectric 150 is a dielectric material conformally deposited over trench isolation structures 140 and active layer 130. Gate dielectric 150 is selected of a dielectric material such as silicon dioxide or a material having a dielectric constant greater than silicon dioxide. Following the deposition of gate dielectric 150, a gate electrode material may be conformally deposited over the gate dielectric material e.g., over trench isolation structures 140 and active layer 130. A suitable material for a gate electrode is, for example, a metal material selected to have a work function, in this embodiment, equivalent to a P-type device. Following a conformal deposition of materials for gate dielectric 150 and gate electrode 160, dielectric etch stop layer 165 of, for example, a silicon nitride or silicon oxide nitride material is deposited on a material for gate electrode. Following deposition of dielectric etch stop layer 165, the materials may be patterned to define a gate electrode (e.g., a desired gate length, L). A photolithographic and etching process may be used to define gate electrode 160 and gate dielectric 150. Dielectric etch stop layer 165 is shown on defined gate electrode 160.

FIG. 4 shows a cross-sectional side view of the structure of FIG. 3 through lines 4-4′. FIG. 4 also shows the formation of sidewall spacers 170 adjacent gate electrode 160 (e.g., on opposing sidewalls of gate electrode 160). In one embodiment sidewall spacers 170 are a dielectric material of, for example, silicon dioxide or silicon nitride. FIG. 5 shows the structure of FIG. 4 following the definition of source and drain regions adjacent gate electrode 160 in the composite substrate including substrate 110, barrier layer 120, and active layer 130. In one embodiment, source and drain regions 180 are formed to a depth extending through active layer 130 and barrier layer 120 into substrate 110. In this embodiment, source and drain regions 180 are self-aligned to sidewall spacers 170 adjacent gate electrode 160. An anisotropic etch chemistry selective for silicon over, for example, silicon dioxide or silicon nitride (sidewall spacers 170) may be used to form source and drain regions 180.

FIG. 5 also shows the formation of barrier layer 190 conformally within each of source and drain regions 180. In one embodiment, barrier layer 190 is formed by an atomic layer deposition process. Barrier layer is selected, in one embodiment, of a material and a thickness that will inhibit diffusion of source and drain material dopants into a channel region of the device. In one embodiment, an ALD process is used to deposit a layer of N-type material conformally on the sidewalls and base of the defined source and drain regions in the composite substrate. In one embodiment, a dopant profile of barrier layer 190 is similar to a dopant profile of barrier layer 120 (e.g., similar material and dopant concentration (n++ carbon doped material)). A representative thickness of barrier layer 190 is in the range of 10 Å to 100 Å.

FIG. 6 shows the structure of FIG. 5 following the deposition of material in source and drain regions 180. In one embodiment, source and drain material 200 is a P-type epitaxial material deposited to a thickness greater than a height of the composite structure so as to form a non-planar transistor device. In one embodiment, material 200 is a p++ epitaxial silicon germanium. The source and drain material can be deposited with LPCVD epitaxial growth using SiH4, GeH4, and B2H6 gases.

Following the deposition of source and drain material 200, the dielectric etch stop 165 is selectively removed, and the source and drain material may be converted to a silicide. Interlayer isolation, contacts and interconnect structures may then be formed to source and drain regions 200 and gate electrode 160.

FIG. 6 shows a P-type metal oxide semiconductor (MOS) device having junction regions isolated/defined by barrier layer 190 in channel region formed of active layer 130 and defined by barrier layer 120 and barrier layer 190 beneath gate electrode 160. Structure 100 shown in FIG. 6 is, for example, a PMOS device of a complimentary metal oxide semiconductor (CMOS). Structure 100 may be connected through conductive interconnect material to an adjacent NMOS device to form the CMOS. It is appreciated that although a PMOS structure is shown, the same principles may be applied to form an NMOS device.

FIG. 7 shows a cross-sectional view of an integrated circuit package that can be physically and electrically connected to a printed wiring board or printed circuit board (PCB) to form an electronic assembly. The electric assembly can be part of an electronic system such as a computer (e.g., desktop, laptop, handheld, server, etc.), wireless communication device (e.g., cellular phone, cordless phone, pager, etc.), computer-related peripheral (e.g., printer, scanner, monitor, etc.), entertainment device (e.g., television, radio, stereo, tape and compact disc player, video cassette recorder, motion picture expert group audio player 3 player (MP3), and the like. FIG. 7 illustrates the assembly is part of a desktop computer. FIG. 7 shows electronic assembly 250 including die 260 physically and electrically connected to packet substrate 270. Die 260 is an integrated circuit die, such as a microprocessor die, having one or more transistor structures formed as described with reference to FIGS. 1-6. Electrical contact points (e.g., contact pads on a surface of die 260) are connected to packet substrate 270 through, for example, a conductive bump layer. Packet substrate 270 may be used to connected die 260 to printed circuit board 280 such as a motherboard or other circuit board.

In the preceding detailed description, reference is made to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4949136 *Jun 9, 1988Aug 14, 1990University Of ConnecticutSubmicron lightly doped field effect transistors
US5545575 *Oct 24, 1994Aug 13, 1996Motorola, Inc.Method for manufacturing an insulated gate semiconductor device
US5627097 *Jul 3, 1995May 6, 1997Motorola, Inc.Method for making CMOS device having reduced parasitic capacitance
US5759901 *Aug 1, 1997Jun 2, 1998Vlsi Technology, Inc.Fabrication method for sub-half micron CMOS transistor
US6143593 *Sep 29, 1998Nov 7, 2000Conexant Systems, Inc.Elevated channel MOSFET
US6383876 *Jul 27, 2000May 7, 2002Lg Semicon Co., Ltd.MOS device having non-uniform dopant concentration and method for fabricating the same
US6566204 *Mar 31, 2000May 20, 2003National Semiconductor CorporationUse of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors
US6734482 *Nov 15, 2002May 11, 2004Micron Technology, Inc.Trench buried bit line memory devices
US6808971 *Jan 14, 2004Oct 26, 2004Micron Technology, Inc.High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
US7002214 *Jul 30, 2004Feb 21, 2006International Business Machines CorporationUltra-thin body super-steep retrograde well (SSRW) FET devices
US20020033511 *Sep 7, 2001Mar 21, 2002Babcock Jeffrey A.Advanced CMOS using super steep retrograde wells
US20030235936 *May 16, 2003Dec 25, 2003Snyder John P.Schottky barrier CMOS device and method
US20060022270 *Jul 30, 2004Feb 2, 2006International Business Machines CorporationUltra-thin body super-steep retrograde well (ssrw) fet devices
Non-Patent Citations
Reference
1 *Ritala et al., Atomic layer epitaxy- a valuable tool for nanotechnology?, Nanotechnology, 10 (1999) 19-24.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7872303 *Aug 14, 2008Jan 18, 2011International Business Machines CorporationFinFET with longitudinal stress in a channel
US8080820Mar 16, 2009Dec 20, 2011Intel CorporationApparatus and methods for improving parallel conduction in a quantum well device
US8242001Oct 17, 2011Aug 14, 2012Intel CorporationApparatus and methods for improving parallel conduction in a quantum well device
US8525151Jul 10, 2012Sep 3, 2013Intel CorporationApparatus and methods for improving parallel conduction in a quantum well device
US8748940Dec 17, 2012Jun 10, 2014Intel CorporationSemiconductor devices with germanium-rich active layers and doped transition layers
WO2013095655A1 *Dec 23, 2011Jun 27, 2013Intel CorporationSemiconductor device having germanium active layer with underlying diffusion barrier layer
Classifications
U.S. Classification438/305, 257/E21.054, 257/E21.049, 257/E21.043, 257/E21.044, 438/306, 438/529, 438/527, 438/301, 438/526
International ClassificationH01L21/335
Cooperative ClassificationH01L21/823814, H01L21/823807, H01L21/823878, H01L29/66636, H01L29/165, H01L29/0847
European ClassificationH01L29/66M6T6F11E, H01L29/08E2, H01L29/165
Legal Events
DateCodeEventDescription
Oct 24, 2012FPAYFee payment
Year of fee payment: 4
Oct 24, 2012SULPSurcharge for late payment
Sep 17, 2012REMIMaintenance fee reminder mailed
Jul 23, 2007ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JIN, BEEN-YIH;DOYLE, BRIAN S.;CHAU, ROBERT S.;AND OTHERS;REEL/FRAME:019587/0526
Effective date: 20060309