US 7485536 B2
A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
1. A method comprising:
forming a channel region between a source region and a drain region in a layer on a substrate, a material of the channel region comprising a first dopant profile;
forming a first barrier layer between the channel region and a well of the substrate, the first barrier layer comprising a second dopant profile different from the first dopant profile wherein the first dopant profile and the second dopant profile comprise a similar carrier;
defining the source region and the drain region such that the source region and the drain region extend through the first barrier layer;
forming a second barrier layer between the source region and the well and between the drain region and the well; and
forming a source material in the source region and a drain material in the drain region and the channel and the drain material and the channel,
wherein the second barrier layer is disposed between the source material and the channel and the drain material and the channel, and
wherein the second barrier layer comprises a dopant profile different than a dopant profile of a material of the well and a dopant profile of each of the material of the source region and the material of the drain region.
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Circuit devices and methods for forming circuit devices.
A metal oxide semiconductor field effect transistor (MOSFET) is a common element of an integrated circuit such as a microprocessor or other circuit. The transistor typically includes a source and drain junction region formed in a semiconductor substrate and a gate electrode formed on a surface of the substrate. A gate length is generally the distance between the source and drain junction region. Within the substrate, the region of the substrate beneath the gate electrode and between the source and drain junctions is generally referred to as a channel with a channel length being the distance between the source and drain junctions.
A transistor device works generally in the following way. Carriers (e.g., electrons, holes) flow between source junction and drain junction by the establishment of contacts to the source and drain regions. In order to establish the carrier flow, a voltage is applied to the gate electrode to form an inversion layer of carriers in the channel. The minimum amount of gate voltage is generally referred to as a threshold voltage (Vt).
As noted above, many transistor devices are formed in a semiconductor substrate. The substrate body may be a bulk silicon substrate or a silicon on insulator (SOI) substrate. To form ohmic contacts to carriers in the channel, dopants are introduced (e.g., via ion implantation) into the substrate. Representatively, an N-type transistor device may have source and drain regions (and gate electrode) doped with an N-type dopant such as arsenic or phosphorous. The N-type regions are formed in a well that has previously been formed in the semiconductor substrate as a P-type conductivity. A suitable P-type dopant is boron.
The silicon and SOI body described above are designed to be fully depleted (i.e., removing of essentially all bulk charge carriers by an electric field). Fully depleted FET transistors tend to have better gate control on a channel potential than planar MOSFET devices at low drain bias VDS. Full depletion however, does not ensure better short-channel effects (SCEs) at high VDS as the drain electric field can reach the source end through the substrate in bulk silicon wafers or through a buried oxide (BOX) layer in SOI wafers. In general, it is desired that SCEs are low such that the transistor off-state leakage current, IOFF, (i.e., a current flowing between source and drain regions when a transistor is in an off state) remains as low as possible. SCEs may be determined by monitoring the subthreshold slope (SS) and drain induced barrier lowering (DIBL). Subthreshold slope, which is a measure of the gate coupling to the channel potential, is defined as SS=dVG/d[logIDS], where VG is the gate voltage and IDS is the drain-to-source current. DIBL, which is a measure of the threshold voltage shift versus drain bias, is defined as DIBL=(VTLIN−VTSAT)/(VDSAT−VDLIN). VTLIN is the linear threshold voltage at low drain bias VDLIN, typically 50 mV. VTSAT is the saturate threshold voltage at high drain bias VDSAT, which is typically in the range of from 1 to 1.2V for current generation of logic transistors. A steeper SS and/or reduced DIBL shift indicates lower IOFF.
Reduced drain-to-source coupling leads to better SCEs. Drain field penetration (i.e., drain-to-source coupling), may be reduced by scaling the substrate body size (e.g., thin body width WSI for double-gated transistors such as FinFETs, and thin TSI and WSI for triple-gated transistors such as tri-gates) or by introducing heavy doping in the source tip to channel and channel to drain tip junctions of bulk Si wafers or the Si body in SOI wafers. Very small body dimensions, however, are not desirable because of a potential for large external resistance (REXT).
In addition, heavy doping in the source tip to channel and channel to drain tip junctions is generally achieved by locally implanted dopants (P-type in N-type metal oxide semiconductor FETs (NMOSFETs) and N-type dopants in P-type metal oxide semiconductor FETs (PMOSFETs) introduced in the substrate body and in the case of the SOI substrate, in the Si body. Such implants are referred to as “halo” implants. Typical halo implants for NMOSFETs include boron and indium (In)). Halo implants for PMOSFETs include arsenic (As), antimony (Sb), and phosphorous (P). These halos are typically implanted at an angle resulting in potential overlap between the halos and source/drain (S/D) regions and/or tip regions. These Halo implant are more difficult to implement in a nonplanar FINFET or TRI-Gate configuration.
The features, aspects, and advantages of the invention will become more thoroughly apparent from the following detailed description, appended claims, and accompanying drawings in which:
In the following description, a transistor device is described as is a method of forming the transistor device utilizing layer-by-layer growth of in-situ doped at the layers by atomic layer deposition.
Overlying substrate 110 in
As will become clear later, a portion of active layer 130 will serve as a transistor device channel. In this embodiment, barrier layer 120 is selected of a material and thickness to inhibit off-state interface leakage of a transistor device. Representatively, barrier layer 120 and active layer 130 are each epitaxial layers formed in situ by an atomic layer deposition (ALD) process. Generally speaking, an atomic layer deposition process involves forming a film or layer in a layer-by-layer process by exposing a surface to alternating pulses of reactants, each of which undergoes a self-limiting reaction, generally resulting in controlled film deposition. In one embodiment, barrier layer 120 and active layer 130 are of a similar carrier (e.g., N-type) but the dopant profile is changed. In one embodiment, using an atomic layer deposition process, by alternating pulsing of chemical reaction precursors (e.g., silane, phosphine, methylsilane, etc.), dopant gas and hydrogen gas, barrier layer 120 is, for example, a carbon-doped n++ material and active layer 130 is an n material.
As an example, a phosphine, arshine or antimony (Sb) source pulse width and flow rate determines the thicknesses and concentration profile of barrier layer 120 and active layer 130. A deposition temperature ranges from 450° C. to 900° C., and the pressure ranges from 10 torr to one atmosphere. Typical thicknesses for barrier layer 120 and active layer 130 are 10 angstroms (Å) to 100 Å, and 100 Å to 500 Å, respectively. The doping level of barrier layer 120 can be similar to a doping of a halo implant, while the doping level of active layer 130 can be similar to a well implant commonly used in planar MOSFET devices.
Following the deposition of source and drain material 200, the dielectric etch stop 165 is selectively removed, and the source and drain material may be converted to a silicide. Interlayer isolation, contacts and interconnect structures may then be formed to source and drain regions 200 and gate electrode 160.
In the preceding detailed description, reference is made to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.