|Publication number||US7491588 B2|
|Application number||US 11/598,507|
|Publication date||Feb 17, 2009|
|Filing date||Nov 13, 2006|
|Priority date||Jun 12, 2001|
|Also published as||CN1263121C, CN1535478A, EP1402573A1, EP1402573A4, US6759282, US7141853, US7320918, US20020185684, US20050029592, US20050214988, US20070128784, WO2002101825A1|
|Publication number||11598507, 598507, US 7491588 B2, US 7491588B2, US-B2-7491588, US7491588 B2, US7491588B2|
|Inventors||John E. Campbell, William T. Devine, Kris V. Srikrishnan|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (39), Referenced by (12), Classifications (47), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a division of U.S. patent application Ser. No. 10/832,894 filed Apr. 27, 2004, now U.S. Pat. No. 7,141,853 which in turn, is a division of U.S. patent application Ser. No. 09/879,530 filed Jun. 12, 2001 now U.S. Pat. No. 6,759,282. The disclosures of said applications are hereby incorporated herein by reference.
1. Field of the Invention
The present invention involves fabrication of semiconductor devices using Silicon-on-Insulator (SOI) technology. More specifically the invention is directed to the use of the SOI Buried Oxide (BOX) layer as an integral component of electronic devices and circuits.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology has emerged as an electronic fabrication technique that improves characteristics such as latch-up and speed, although typically at higher manufacturing cost. The term SOI typically describes structures where devices are fabricated in single-crystal Si layers formed over an insulating film or substrate.
The first process, known as SIMOX (Separation by IMplanted OXygen), consists of implantation of oxygen into an Si substrate at a prescribed depth and heating it to form a continuous layer of SiO2. The SIMOX process requires only a single wafer. The alternate process, shown in greater detail later, is commonly referred to as “Bonded SOI” and starts with two wafers, preferably with at least one having an oxide surface. The first wafer is the carrier wafer which is joined together with the second wafer, and the second wafer is “thinned” to leave a layer of silicon bonded onto the carrier wafer, separated by an insulator layer.
Both of the techniques have experienced many variations and enhancements over the years for improvement of yield and lower cost and to achieve desirable device layer quality for uniformity and defects. An important characteristic of conventional SOI that is obvious from
The problem with this approach is that, although devices and interconnects are formed similar to conventional substrates, SOI techniques introduce newer problems such as floating body effects. Additionally, conventional SOI structure takes up considerably more chip “real estate” than required in corresponding non-SOI structure, since floating body effects which not an issue with conventional substrates require additional connections to the channel regions. There are also added process steps to provide ground interconnections to the substrate. More important, the conventional approach fails to recognize that the insulator layer could provide more functionality than merely separating predetermined groups of devices from the substrate.
The inventors have recognized that the SOI insulator layer, or BOX (Buried OXide), can be an integral part of a specific device, and further, even circuits can be advantageously built around this innovative approach. That is to say, the BOX can be considered more than a mere passive isolation mechanism separating layers of devices. It can become an integral component even of an entire circuit. As will be demonstrated, by adopting this innovative approach, a whole new possibility opens up for SOI technology that provides improved device density and speed and fewer conductor interconnects between devices.
According to an aspect of the invention a method is provided for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate, where the SOI substrate includes a single-crystal semiconductor layer separated from a bulk semiconductor region by a buried oxide layer. In such method, a plurality of field effect transistors (FETs) are formed including a first FET and a second FET. Each of the plurality of FETs has a channel region disposed in a common device layer within the single-crystal semiconductor layer. A gate of the first FET overlies an upper surface of the common device layer, and a gate of the second FET underlies a lower surface of the common device layer remote from the upper surface. In addition, the first and second FETs share a common diffusion region disposed in the common device layer and are conductively interconnected by the common diffusion region. The common diffusion region is operable as at least one of a source region or a drain region of the first FET and is simultaneously operable as at least one of a source region or a drain region of the second FET.
According to a second aspect of the invention, a method is disclosed of fabricating an electronic circuit using an SOI technique, said SOI technique resulting in formation of at least one buried oxide layer, the electronic circuit comprising a plurality of interconnected electronic devices, each electronic device comprising a respective plurality of components. The method includes fabricating a predetermined first set of respective plurality of components to be on a first side of the buried oxide layer and fabricating a predetermined second set of respective plurality of components to be on a second side of the buried oxide layer, where the second side is the opposite side of the first side, and where the buried oxide layer performs a function integral to the functioning of at least one of the electronic devices.
According to a third aspect of the invention, a method is disclosed of SOI fabrication in which a buried oxide layer is formed, where the method includes forming a first set of device components to be on a first side of the buried oxide layer and forming a second set of device components to be on the side opposite the first side, where the buried oxide layer performs a function integral to the functioning of at least one device comprised of components from the first set of components and components from the second set of components.
According to a fourth aspect of the invention, a method and structure are disclosed of fabricating a DRAM cell using an SOI technique on a substrate, where the SOI technique results in formation of at least one buried oxide layer. The method includes forming a buried capacitor beneath the buried oxide layer, subsequently forming an FET source and drain regions on top of the buried oxide layer, and interconnecting the capacitor to one of the source region or drain region with a via penetrating the buried oxide layer, where the via is a conductive material.
According to a fifth aspect of the invention, a method and structure are disclosed of fabricating a DRAM cell using an SOI technique, where the SOI technique results in formation of at least one buried oxide (BOX) layer, whereby a capacitor for the DRAM cell is formed by a process including forming a buried electrode in a substrate, wherein the buried electrode serves as a lower capacitor charge plate and forming a diffusion link between the diffusion region of a transistor located on the upper side of the BOX and a region to comprise an upper charge plate of the capacitor, where the upper charged plate of the capacitor is formed on the upper side of the BOX when impressing a bias voltage on the buried electrode.
According to a sixth aspect of the invention, a method and structure are disclosed of fabricating an electronic circuit having a plurality of electronic devices using an SOI technique, the SOI technique resulting in formation of at least one buried oxide layer. The method includes forming an interconnector of conductive material to interconnect at least two of said plurality of electronic devices, the interconnector at least partially enclosed by said buried oxide.
According to a seventh aspect of the invention, a method and structure are disclosed of fabricating a dynamic two-phase shift register. The method includes forming a buried oxide layer using an SOI technique, forming a plurality of FET transistors to be in a device layer above the buried oxide layer, forming a first clock signal conductor on top of the device layer, and forming a second clock signal conductor below the device layer, the second clock signal conductor at least partially enclosed by the buried layer.
According to an eighth aspect of the invention, a method and structure are disclosed of fabricating a CMOS circuit. The method includes forming a buried oxide layer using an SOI technique and forming a plurality of FET transistors to be in a device layer above the buried oxide layer, wherein at least two of the FET transistors share a common diffusion region, thereby electrically interconnecting the two FET transistors without using a separate interconnecting conductive material.
According to a ninth aspect of the invention, a method and structure are disclosed of fabricating a FET using an SOI technique, the SOI technique resulting in formation of at least one buried oxide layer. The method includes forming a first gate beneath the buried oxide layer and forming a second gate on top of the buried oxide layer.
According to a tenth aspect of the invention, a structure is disclosed of an electronic device including at least one SOI buried oxide layer, where the at least one buried oxide layer performs a function integral to the device.
According to an eleventh aspect of the invention, a structure is disclosed of an electronic device comprising at least one SOI buried oxide layer, where the at least one SOI buried oxide layer becomes a structural element integral to the device.
According to a twelfth aspect of the invention, a structure is disclosed of an electronic circuit comprising a plurality of interconnected devices, the circuit mounted on a wafer having at least one SOI buried oxide layer, wherein the at least one SOI buried oxide layer is a functional element integral to at least one of the devices.
According to a thirteenth aspect of the invention, a structure is disclosed of an electronic circuit comprising a plurality of interconnected devices, the circuit mounted on a wafer having at least one SOI buried oxide layer, where the at least one SOI buried oxide layer comprises a structural element integral to at least one of the devices.
According to a fourteenth aspect of the invention, a structure is disclosed of an electronic circuit comprising a plurality of interconnected devices, the circuit mounted on a wafer having at least one SOI buried oxide layer, where the two adjacent devices share at least one device component, thereby electrically interconnecting the two devices without an interconnecting conductor, and where the SOI buried oxide layer serves to isolate components of the two interconnected devices other than the shared component.
According to a fifteenth aspect of the invention, a method is disclosed of SOI fabrication wherein a buried oxide layer is formed. The method includes forming a first set of device components to be on a first side of the buried oxide layer and forming a second set of device components to be on the side opposite, where the buried oxide layer is used for an active functioning of at least one buried device.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
Note that the drawings are drawn more to illustrate the inventive processes and structures and are not drawn to scale.
Going back to
Turning now to the invention,
Concerning the bonded technique,
The process of etching vertical trenches in silicon substrate is well known. For example, for the exemplary buried gate process a standard lithography can be used to create the pattern in a resist mask, followed by a directional etching using a Cl2/Ar plasma such as described in U.S. Pat. No. 4,139,442, assigned to the assignee and incorporated herein by reference. Other commercially available etch processes are also satisfactory for the trench etch. After removing the resist mask, the substrate is similar to that shown in
Subsequently, as shown in
The width of the gate pattern for the buried gates is restricted by the specific design ground rule. The polysilicon conductor 210 when deposited typically will fill and provide approximately a planar top surface. The polysilicon is then preferably polished by chemical-mechanical polishing (“CMP”) using, for example CABOT SC-I, a colloidal silica in an aqueous KOH solution with pH i10. Other polishing slurries commercially available and known in the field for polishing polysilicon with good selectivity to silicon nitride or silicon dioxide can also be used.
At the end of polishing, the polysilicon 210 in the trench may be slightly recessed with respect to the insulator 206 but has a high degree of smoothness, typically a few nanometers. Specifically, the polishing process described in the publication “Characterization of Polysilicon Oxides Thermally Grown and Deposited on the Polished Polysilicon Films”, by Tan Fu Lei et al., IEEE Transactions on Electron Devices, vol. 45, No.4, April 1998, pages 912-917 is extremely attractive for producing a highly smooth polysilicon surface. The polish stop layer silicon nitride 203, if it was used, is now removed from the top horizontal surfaces by wet etching selective to silicon and silicon dioxide, as is well known in the art.
Alternatively, a high quality CVD silicon dioxide of about 200-1000 A is deposited and polished back to leave a desired thinner oxide layer over the polysilicon gate region. Because of the method described above for the formation of the polysilicon in the trenches, the resulting structure shown in 2E will have a thinner oxide over the polysilicon gate region 212 and a thicker oxide 213 over the silicon substrate regions.
As a possible alternative, if CVD tungsten is used as the buried gate electrode. Instead of depositing polysilicon, a seed layer of TiN or Ti/TiN or TiW is deposited and followed by CVD W deposition using well established techniques with silane, hydrogen and WF6 gases in a thermal reactor. The blanket metal film will appear similar to the polysilicon planar structure after deposition, which can be treated by CMP or plasma etched back to remove the W and the seed layers from the top surfaces. In one preferred process, the W layer will be recessed by using a plasma etch followed by forming a cap of silicide or silicon. The purpose of forming a tungsten silicide or polysilicon cap is again to form a thin oxide surface over the electrode. If a buried body contact is being formed, then there is no need to form the additional oxide on the surface of the encased conductor. Any oxide formed on the encased conductor is selectively removed. Other known variations of processes can be used to achieve essentially the structure shown in
Continuing with the bonded technique,
Device layer 32 is deposited epitaxially using, for example, SiGe, but the specific material depends upon the device to be fabricated. An etch stop layer is optionally added on top of the device layer, which could be simply a highly doped silicon layer or a silicon-germanium layer, as per the teaching of the above mentioned U.S. Pat. No. '987. A thin thermal oxide 33 of thickness 50-200 A is optionally grown on the monocrystalline surface. When the end device will include body contact, a bare silicon without oxide layer 33 is used.
Hydrogen 31 is implanted under conditions taught in '987, preferably at a depth below the deposited device layer. As shown in
The transferred device layer surface 35 is now finished to a smooth surface by polishing or etching or along the teaching of U.S. Pat. No. '987 using an optional etch-stop layer Thus, an SOI wafer 20 (see also
Referring now back to
Thereafter, oxide layer 200 is removed and any insulating layer 402 over the buried contact 209 is selectively removed by means of a block-out mask (
The energetics of the implantation controls the depth of the implanted ions 407. For a buried gate 210 or body contact 209, the implant depth is chosen to be slightly beneath the device layer. For buried wires and capacitors, since the structures are fully encased in insulator, this implantation location is less critical but preferably the implant depth is chosen to be near the device layer and substrate interface so that at least part of the BOX layer formed can cover the top of the wire and capacitor elements.
Using anneal conditions and timing such as taught in U.S. Pat. No. 6,043,166, the implanted oxygen is converted into a buried oxide layer 408 as shown in
Even though the SIMOX process has been described using a set of preferred process steps with a view to forming buried gate electrode and buried body contact elements, it should be obvious to one skilled in the art, the above described process steps can be used as well to form other elements such as buried wiring layer or capacitor elements by small variations to the above process.
Also of interest in the
In SOI devices, there is a strong need to connect the body silicon region to a common ground or substrate potential to stabilize the threshold voltage.
One of the important features of this invention is the ability to use the SOI buried layer to form separate devices while still retaining a commonality between the devices. This feature allows devices to be interconnected without having to provide interconnection conductors, thereby improving device density. This feature is exemplarily illustrated in
For many applications, the source/drain of adjacent devices can be advantageously shared, as shown in
The formation of capacitors 70A,70B in a substrate, for example, has been specifically discussed with the aid of
In contrast to processes where the buried capacitor is formed subsequent to the SOI substrate, the process described here, where the buried capacitor was formed prior to the SOI structure, offers process simplicity in comparison with other SOI trench capacitor processes and can provide better yields and lower cost.
In the embodiment of
The arrangement of electrodes of capacitor becomes clear by comparing
One aspect of novelty in this structure is the location of C1 horizontally relative to Q1. C1 may be located substantially under Q1 which produces a minimum total cell area, allowing maximum DRAM memory density on a unit area of silicon wafer. It may, however, be located substantially outside the region covered by the gate of Q1 for a minimum density result and still operate. The point is that the location of C1 relative to Q1 is non critical, so long as C1 does not come closer to bit line BL0 than some minimum dimension established by a leakage current/storage cell retention time criteria.
In a two phase dynamic shift register two transistors are used to store one bit of data. In the case of
The two phase shift register structure of this invention register is based upon the very important semiconductor processing teaching of this invention that allows transistors to be isolated by BOX layer 90 to be formed on top and in bottom of a shared region 92 of semiconducting material.
In the structure shown in
Further, if geometries of the transistors, diffusions, and gate wiring were such that a conflict for available real-estate existed when attempting to wire the gate regions of two sequential transistors in the shift register chain, such conflict would be substantially reduced or eliminated by constructing the shift register in an alternating fashion of top/bottom transistor location as shown in
The structure of the NOR circuit in
However, this invention allows a unique means to fabricate transistor Q3, Q4, one above the other, thus allowing for a significant reduction in chip size for a given logical function. It should be noted that this is the technique discussed earlier in which components are connected in parallel without requiring separate interconnection conductors.
Additional benefit will be apparent in this structure in the area required for the commonly shared source drain diffusions shared by transistors Q3, Q4. In particular the area of the common drain diffusion of Q3 and Q4 shared with the source diffusion of Q2 is reduced in area such that the switching time on the NOR circuit is significantly reduced. This common node or diffusion also serves as the output node of the circuit. Since any capacitance reduction results in a reduced circuit delay (switching time), the speed is additionally increased. The concept here is shown for a NOR circuit but is also readily applied to the popular NAND logic circuit and many other circuit types found in the current CMOS logic technology industry that produces today's microprocessor chips and ASIC chips.
These are but some examples of circuits that can be formed utilizing buried devices in conjunction with traditional FETs and other devices. Many ASIC applications can benefit with the additional design ground rules allowed by the inventive devices being available in the buried substrate.
The examples discussed also demonstrate that with these techniques the buried oxide can be used for more than simple isolation. The BOX has been shown to be available for other functions such as the gate oxide for a buried transistor and the pass-through for a body contact.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4341009||Dec 5, 1980||Jul 27, 1982||International Business Machines Corporation||Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate|
|US5343064||Mar 18, 1988||Aug 30, 1994||Spangler Leland J||Fully integrated single-crystal silicon-on-insulator process, sensors and circuits|
|US5374564||Sep 15, 1992||Dec 20, 1994||Commissariat A L'energie Atomique||Process for the production of thin semiconductor material films|
|US5376561||Apr 24, 1992||Dec 27, 1994||Kopin Corporation||High density electronic circuit modules|
|US5473181||Sep 29, 1994||Dec 5, 1995||Siemens Aktiengesellschaft||Integrated circuit arrangement having at least one power component and low-voltage components|
|US5547886||Dec 6, 1994||Aug 20, 1996||Mitsubishi Denki Kabushiki Kaisha||Method of producing a semiconductor device|
|US5604368||Mar 21, 1995||Feb 18, 1997||International Business Machines Corporation||Self-aligned double-gate MOSFET by selective lateral epitaxy|
|US5619054 *||Jun 6, 1995||Apr 8, 1997||Sony Corporation||CMOS transistor and isolated back gate electrodes on an SOI substrate|
|US5631186||Dec 28, 1995||May 20, 1997||Samsung Electronics Co., Ltd.||Method for making a dynamic random access memory using silicon-on-insulator techniques|
|US5646058||Aug 1, 1996||Jul 8, 1997||International Business Machines Corporation||Method for fabricating a self-aligned double-gate MOSFET by selective lateral epitaxy|
|US5654220||Jun 7, 1995||Aug 5, 1997||Elm Technology Corporation||Method of making a stacked 3D integrated circuit structure|
|US5656548||Sep 19, 1995||Aug 12, 1997||Kopin Corporation||Method for forming three dimensional processor using transferred thin film circuits|
|US5670387||Jan 3, 1995||Sep 23, 1997||Motorola, Inc.||Process for forming semiconductor-on-insulator device|
|US5736435||Jul 3, 1995||Apr 7, 1998||Motorola, Inc.||Process for fabricating a fully self-aligned soi mosfet|
|US5741733||Jan 12, 1995||Apr 21, 1998||Siemens Aktiengesellschaft||Method for the production of a three-dimensional circuit arrangement|
|US5767001||May 2, 1994||Jun 16, 1998||Siemens Aktiengesellschaft||Process for producing semiconductor components between which contact is made vertically|
|US5844294||Dec 30, 1996||Dec 1, 1998||Nec Corporation||Semiconductor substrate with SOI structure|
|US5882987||Aug 26, 1997||Mar 16, 1999||International Business Machines Corporation||Smart-cut process for the production of thin semiconductor material films|
|US5889293||Apr 4, 1997||Mar 30, 1999||International Business Machines Corporation||Electrical contact to buried SOI structures|
|US5889302||Apr 21, 1997||Mar 30, 1999||Advanced Micro Devices, Inc.||Multilayer floating gate field effect transistor structure for use in integrated circuit devices|
|US5891761||Aug 22, 1997||Apr 6, 1999||Cubic Memory, Inc.||Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform|
|US5939745||Apr 15, 1997||Aug 17, 1999||Samsung Electronics Co., Ltd.||Dynamic access memory using silicon-on-insulator|
|US5970339||Apr 25, 1997||Oct 19, 1999||Lg Semicon Co., Ltd.||Method of manufacturing a dynamic access memory which is suitable for increasing integration and suppressing generation of leakage current using an SOI structure|
|US5998808||Jun 26, 1998||Dec 7, 1999||Sony Corporation||Three-dimensional integrated circuit device and its manufacturing method|
|US6037617||Feb 3, 1998||Mar 14, 2000||Nec Corporation||SOI IGFETs having raised integration level|
|US6067062||Aug 23, 1991||May 23, 2000||Seiko Instruments Inc.||Light valve device|
|US6096582 *||Jul 23, 1997||Aug 1, 2000||Canon Kabushiki Kaisha||Method of making a semiconductor device|
|US6188122||Jan 14, 1999||Feb 13, 2001||International Business Machines Corporation||Buried capacitor for silicon-on-insulator structure|
|US6291858||Jan 3, 2000||Sep 18, 2001||International Business Machines Corporation||Multistack 3-dimensional high density semiconductor device and method for fabrication|
|US6384439||Feb 1, 1999||May 7, 2002||Texas Instruments, Inc.||DRAM memory cell and array having pass transistors with recessed channels|
|US6531741||Mar 3, 1999||Mar 11, 2003||International Business Machines Corporation||Dual buried oxide film SOI structure and method of manufacturing the same|
|US6531754||Feb 27, 2002||Mar 11, 2003||Kabushiki Kaisha Toshiba||Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof|
|US6538916||Sep 27, 2001||Mar 25, 2003||Kabushiki Kaisha Toshiba||Semiconductor memory device|
|US6548848||Dec 3, 2001||Apr 15, 2003||Kabushiki Kaisha Toshiba||Semiconductor memory device|
|US6611023 *||May 1, 2001||Aug 26, 2003||Advanced Micro Devices, Inc.||Field effect transistor with self alligned double gate and method of forming same|
|US6649980 *||Dec 11, 2001||Nov 18, 2003||Sony Corporation||Semiconductor device with MOS transistors sharing electrode|
|US20020063285 *||Nov 29, 2000||May 30, 2002||De-Yuan Wu||SOI device and method of fabrication|
|JP2000196103A||Title not available|
|JP2000307117A||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7939395 *||May 14, 2009||May 10, 2011||International Business Machines Corporation||High-voltage SOI MOS device structure and method of fabrication|
|US8022469||Dec 9, 2010||Sep 20, 2011||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US8325506||Dec 21, 2010||Dec 4, 2012||Soitec||Devices and methods for comparing data in a content-addressable memory|
|US8581332||Aug 11, 2011||Nov 12, 2013||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US8803273 *||Sep 10, 2013||Aug 12, 2014||Samsung Electronics Co., Ltd.||High sensitivity image sensors|
|US9184173||Oct 1, 2013||Nov 10, 2015||Semiconductor Enery Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US9331098||Jul 19, 2014||May 3, 2016||Qualcomm Switch Corp.||Semiconductor-on-insulator integrated circuit with reduced off-state capacitance|
|US9466536||Aug 4, 2014||Oct 11, 2016||Qualcomm Incorporated||Semiconductor-on-insulator integrated circuit with back side gate|
|US9478507||Jan 14, 2015||Oct 25, 2016||Qualcomm Incorporated||Integrated circuit assembly with faraday cage|
|US9530796||May 7, 2014||Dec 27, 2016||Qualcomm Incorporated||Semiconductor-on-insulator integrated circuit with interconnect below the insulator|
|US20100289079 *||May 14, 2009||Nov 18, 2010||International Business Machines Corporation||High-voltage soi mos device structure and method of fabrication|
|US20110170327 *||Dec 21, 2010||Jul 14, 2011||Carlos Mazure||Devices and methods for comparing data in a content-addressable memory|
|U.S. Classification||438/149, 438/199, 257/E21.544, 438/154|
|International Classification||H01L21/8242, H01L29/786, H01L21/02, H01L27/118, H01L27/108, H01L21/336, H01L27/08, H01L21/8238, H01L27/092, H01L27/06, H01L21/3205, H01L21/76, H01L23/52, H01L27/088, H01L21/8234, H01L21/762, H01L21/84, H01L27/12, H01L21/00|
|Cooperative Classification||H01L2924/0002, H01L29/78606, H01L21/76251, H01L29/78648, H01L21/743, H01L27/10873, H01L27/11803, H01L27/1203, H01L29/66772, H01L29/78612, H01L21/84, H01L27/10832|
|European Classification||H01L21/74B, H01L29/786D, H01L21/762D8, H01L29/786B3, H01L27/108F8E, H01L27/118G, H01L29/786B, H01L27/108M4C, H01L29/66M6T6F15C, H01L29/786D2, H01L27/12B, H01L21/84|
|Oct 1, 2012||REMI||Maintenance fee reminder mailed|
|Feb 17, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Apr 9, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130217
|Sep 3, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001
Effective date: 20150629
|Oct 5, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001
Effective date: 20150910