Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7491978 B2
Publication typeGrant
Application numberUS 11/492,754
Publication dateFeb 17, 2009
Filing dateJul 26, 2006
Priority dateJul 26, 2005
Fee statusPaid
Also published asUS20070023776
Publication number11492754, 492754, US 7491978 B2, US 7491978B2, US-B2-7491978, US7491978 B2, US7491978B2
InventorsAlexander L'Vovich Zakgeym, Seog Moon Choi, Sung Jun Lee
Original AssigneeSamsung Electro-Mechanics Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Light emitting diode package
US 7491978 B2
Abstract
A light emitting diode package is provided. The light emitting diode package comprises a submount substrate which includes a mounting region having side walls inclined upwardly, first and second cavities formed around the mounting region, and first and second grooves extending between the mounting region and the first and second cavities on an upper surface of the submount. The package further comprises first and second bump pads formed on a bottom surface of the mounting surface, first and second bonding pads formed on a bottom surface of the first and second cavities, respectively, first and second conductive lines formed along a bottom surface of the first and second grooves for connecting the first and second bump pads to the first and second bonding pads, respectively, and a light emitting diode mounted on the mounting region so as to be connected to the first and second bump pads.
Images(5)
Previous page
Next page
Claims(7)
1. A light emitting diode package, comprising:
a submount substrate including a main cavity defined as a mounting region and having side walls inclined upwardly, first and second assistant cavities formed around the main cavity, and first and second grooves extending between the main cavity and the first and second assistant cavities on an upper surface of the submount;
first and second bump pads formed on a bottom surface of the main cavity;
first and second bonding pads formed on a bottom surface of the first and second assistant cavities, respectively;
first and second conductive lines formed along a bottom surface of the first and second grooves for connecting the first and second bump pads to the first and second bonding pads, respectively; and
a light emitting diode mounted on the main cavity so as to be connected to the first and second bump pads.
2. The light emitting diode package according to claim 1, further comprising:
reflecting plates formed on the side walls of the main cavity.
3. The light emitting diode package according to claim 1, wherein the submount substrate is a silicon substrate having an insulating layer formed on an upper surface thereof.
4. The light emitting diode package according to claim 1, wherein the first and second assistant cavities, the main cavity, and the first and second grooves have substantially coplanar bottom surfaces, and the first and second conductive lines are formed on the coplanar bottom surfaces.
5. The light emitting diode package according to claim 1, wherein the main cavity is located at a center of the upper surface of the submount substrate, and the first and second assistant cavities are located at opposite sides of the main cavity, respectively.
6. The light emitting diode package according to claim 5, wherein the first and second assistant cavities, the first and second grooves, and the main cavity are integrated to a single cavity region having a predetermined width.
7. The light emitting diode package according to claim 1, wherein at least one of the first and second assistant cavities is opened at one side through a side of the submount substrate.
Description
CLAIM OF PRIORITY

This application claims the benefit of Russian Patent Application No. 2005123795 filed on Jul. 26, 2005 in the Russian Patent Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a light emitting diode package, and, more particularly, to a high power light emitting diode package, which overcomes a problem of defects in a metal wiring structure caused by a step of a submount substrate.

2. Description of the Related Art

Generally, light emitting packages must satisfy two requirements, namely, high light emitting efficiency and excellent heat dissipation. These characteristics are very important, in particular, for high power light emitting diode packages mainly used in illuminating apparatuses.

In view of the light emitting efficiency and heat dissipation, a conventional light emitting diode employs a package which comprises a semiconductor substrate such as silicon having a cavity formed therein, as a submount substrate. One example of the light emitting diode is illustrated in FIGS. 1 a and 1 b.

As shown in FIG. 1 a, a conventional light emitting diode package 10 comprises a silicon submount substrate 11 having a mounting region formed thereon. The diode package 10 further comprises an insulating layer 12 such as a SiO2 layer formed on the submount substrate 11, and a metal wiring structure formed on the insulating layer 12.

As shown in FIG. 1 b, the metal wiring structure comprises first and second bump pads 13 a and 13 b connected to respective electrodes (not shown) of a light emitting diode 18, first and second bonding pads 15 a and 15 b connected to external circuit, and first and second conductive lines 14 a and 14 b connecting the first and second bump pads 13 a and 13 b to the first and second bonding pads 15 a and 15 b, respectively.

Although silicon mainly used for the submount substrate 11 has a low thermal conductivity about a third of that of metal, it can be machined to a narrow thickness through a MEMS process, thereby ensuring a lower thermal resistance. Moreover, the mounting region has a structure wherein, after the cavity C is formed on the submount substrate 11 by typical semiconductor processing, metal reflecting plates 16 are formed at opposite sides of the cavity C. The package 10 having the metal reflecting plates 16 ensures high light emitting efficiency.

However, the conventional light emitting diode package 10 suffers defects in the wiring structure due to formation of the cavity C provided as the mounting region. That is, since the first and second conductive lines 14 a and 14 b are formed along inclined side walls of the cavity C, respectively, there is a high possibility of disconnection at portions (regions indicated by I and II) where the first and second bump pads 13 a and 13 b are connected to the first and second bonding pads 15 a and 15 b, respectively.

As such, the submount substrate having the cavity formed in the mounting region provides advantages in view of easy formation of the reflecting plates for enhancing the light emitting efficiency, and effective thermal dissipation by a small thickness of the portion of the substrate where the light emitting diode is mounted. However, since steps are formed on the submount substrate due to formation of the cavity, and cause disconnection, there is a limitation in manufacturing of a highly reliable light emitting diode package with such a submount substrate.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a light emitting diode package, which lowers a height of steps or removes the steps from a region to be formed with a wiring structure, thereby preventing undesired disconnection in the wiring structure.

In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a light emitting diode package, comprising: a submount substrate including a mounting region having side walls inclined upwardly, first and second cavities formed around the mounting region, and first and second grooves extending between the mounting region and the first and second cavities on an upper surface of the submount; first and second bump pads formed on a bottom surface of the mounting surface; first and second bonding pads formed on a bottom surface of the first and second cavities, respectively; first and second conductive lines formed along a bottom surface of the first and second grooves for connecting the first and second bump pads to the first and second bonding pads, respectively; and a light emitting diode mounted on the mounting region so as to be connected to the first and second bump pads.

The light emitting diode package may further comprise reflecting plates formed on the side walls. The submount substrate may be a silicon substrate having an insulating layer formed on an upper surface thereof. In this case, the insulating layer may be a SiO2 layer formed by a thermal oxidation process.

The first and second cavities, the mounting regions, and the first and second grooves may be formed to have substantially coplanar bottom surfaces. As a result, the first and second conductive lines can be formed on the substantially coplanar bottom surface.

The mounting region may be located at a center of the upper surface of the submount substrate, and the first and second cavities may be located at opposite sides of the mounting region. The first and second cavities, the first and second grooves, and the mounting region may be integrated to a single cavity region having a predetermined width.

At least one of the first and second cavities may be opened at one side through a side of the submount substrate. In this manner, wire bonding between the bonding pads formed on the first and second cavities and the external circuit can be easily performed.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIGS. 1 a and 1 b are a side sectional view and a plan view illustrating a conventional light emitting diode package, respectively;

FIGS. 2 a and 2 b are a side sectional view and a plan view illustrating a light emitting diode package in accordance with one embodiment of the present invention, respectively;

FIG. 3 is a plan view illustrating a light emitting diode package in accordance with another embodiment of the present invention; and

FIGS. 4 a and 4 b are a side sectional view and a plan view illustrating a light emitting diode package in accordance with yet another embodiment of the present invention, respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIGS. 2 a and 2 b are a side sectional view and a plan view illustrating a light emitting diode package 20 in accordance with one embodiment of the invention, respectively. FIG. 2 a shows a cross section taken along line X-X′ of the light emitting diode package 20 shown in FIG. 2 b.

The light emitting diode package 20 of FIG. 2 b comprises a submount substrate 21 having a main cavity C1 formed thereon. The submount substrate 21 may be a silicon substrate, which can be easily processed by MEMS. The main cavity C is provided as a mounting region, and has side walls inclined upwards. The inclined side walls of the mounting region are formed with reflecting plates 26 for enhancing light emitting efficiency of the light emitting diode 28, as shown in FIG. 2 b. The reflecting plates 28 are composed of a highly reflective metal, such as Al or Ag.

As shown in FIGS. 2 a and 2 b, first and second assistant cavities C2 and C3 are formed around the mounting region. The first and second assistant cavities C2 and C3 may be formed at opposite ends of the submount substrate 21 such that the first and second assistant cavities C2 and C3 are located at opposite sides of the mounting region, as in the present embodiment. The mounting region and the first and second assistant cavities C2 and C3 are connected via first and second grooves P12 and P13. Preferably, the first and second assistant cavities C2 and C3, and the main cavity C1 provided as the mounting region may be formed to have the same depth as that of the grooves P12 and P13 so as to have a flat bottom surface.

As shown in FIG. 2 b, first and second bump pads 23 a and 23 b are formed on the bottom surface of the mounting region, and the light emitting diode 28 are located on the first and second bump pads 23 a and 23 b such that respective electrodes (not shown) of the diode 28 are connected to the first and second bump pads 23 a and 23 b via solder bumps 27 a and 27 b. First and second bonding pads 25 a and 25 b for connection to the external circuit are formed on the bottom surface of the first and second assistant cavities C2 and C3.

The first and second bump pads 23 a and 23 b are connected to the bonding pads 25 a and 25 b via first and second conductive lines 24 a and 24 b formed on the bottom surface of the grooves P12 and P13. Unlike the conventional light emitting diode package (see FIG. 1 a), the first and second assistant cavities C2 and C3, and the grooves P12 and P13 are additionally formed on a region where the bonding pads 25 a and 25 b, and the first and second conductive lines 24 a and 24 b are formed, thereby lowering the height of the steps where the wiring structure will be formed. In particular, as shown in FIG. 2 b, the assistant cavities C2 and C3, and the grooves P12 and P13 are formed to have substantially the same depth as that of the main cavity C1 in the mounting region, thereby forming the first and second conductive lines 24 a and 24 b on the substantially flat surface. As a result, disconnection of the wiring structure (in particular, conductive lines) caused by the steps can be remarkably prevented.

As such, the present invention is characterized in that the steps are lowered in height or removed altogether from the wiring region by an additional etching process to the region where the bonding pads and the conductive lines will be formed, thereby providing a highly reliably light emitting diode package.

Unlike the structure shown in FIG. 2 b, the light emitting diode package can be realized to the structure, as shown in FIG. 3, wherein a single cavity region including a wiring region is formed.

A light emitting diode package 30 shown in FIG. 3 may comprise a silicon submount substrate (not shown) having an insulating layer 32 similar to that of FIG. 2 b formed thereon. A cavity C is formed as a single component and to a rectangular shape having an identical width on the submount substrate. Unlike the conventional package, the cavity C of the present embodiment is formed to comprise a region where bonding pads and conductive lines will be formed, as well as a region where bump pads will be formed. It can be understood that the cavity of the present embodiment is formed by integrating the first and second cavities, the first and second grooves, and the mounting region shown in FIG. 2 b. In this embodiment, since first and second bump pads 33 a and 33 b, first and second bonding pads 35 a and 35 b, and conductive lines 34 a and 34 b are also formed on a substantially coplanar bottom surface, the disconnection of the wiring structure caused by the steps can be solved.

According to the present embodiment, reflecting layers 36 on opposite side walls of the cavity C can be formed on opposite side walls adjacent to a light emitting diode 38. Thus, although the package of the embodiment is relatively low in enhancement of light emitting efficiency, it can be manufactured via a more simple process.

FIGS. 4 a and 4 b are a side sectional view and a plan view illustrating a light emitting diode package 40 in accordance with yet another embodiment of the invention, respectively.

Referring to FIGS. 4 a and 4 b, the light emitting diode package 40 according to the present embodiment comprises a submount substrate 41 having a main cavity C formed thereon. The cavity C is provided as a mounting region, and has side walls inclined upwards. The inclined side walls of the mounting region are formed with reflecting plates 46 for enhancing light emitting efficiency of the light emitting diode 28.

As shown in FIGS. 4 a and 4 b, first and second bump pads 43 a and 43 b are formed on a bottom surface of the mounting region, and the light emitting diode 48 is located on the first and second bump pads 43 a and 43 b such that respective electrodes (not shown) of the diode 48 are connected to the first and second bump pads 43 a and 43 b via solder bumps 47 a and 47 b. First and second bonding pads 45 a and 45 b are formed on a bottom surface of the first and second cavities D1 and D2, and connected to an external circuit. As with the structure shown in FIG. 2 b, the first and second cavities D1 and D2 are located at opposite sides of the main cavity C in the mounting region. The first and second cavities D1 and D2 are connected to the main cavity C via the first and second grooves P1 and P2, and are opened where the first and second cavities D1 and D2 contact lateral edges of the substrate 41. Although the cavities D1 and D2 of present embodiment are described as being opened where the first and second cavities D1 and D2 contact the lateral edges of the substrate, the cavities may be selectively opened at only one edge according to layout of bonding wire.

The present embodiment provides advantages in that an area for the reflecting layers 46 can be similar to that shown in FIG. 2 b while allowing an easy wire bonding process.

In the present embodiment, the first and second cavities D1 and D2, and the grooves P12 and P13 are formed to have the substantially same depth as that of the main cavity C1 in the mounting region, thereby allowing the first and second conductive lines 44 a and 44 b to be formed on the substantially flat surface as shown in FIG. 4 a. As a result, disconnection in the wiring structure (in particular, conductive lines) caused by the steps can be remarkably prevented.

As apparent from the description, according to the present invention, the steps are lowered in height or removed altogether from the wiring region by an additional etching process to the region where the bonding pads and the conductive lines will be formed together with a cavity provided as a mounting region and having side walls for forming reflecting layers, thereby providing a highly reliably light emitting diode package which can prevent undesired disconnection of the wiring.

It should be understood that the embodiments and the accompanying drawings have been described for illustrative purposes and the present invention is limited only by the following claims. Further, those skilled in the art will appreciate that various modifications, additions and substitutions are allowed without departing from the scope and spirit of the invention according to the accompanying claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US6838689 *Sep 25, 2002Jan 4, 2005Finisar CorporationBackside alignment and packaging of opto-electronic devices
US6881980 *Jun 17, 2004Apr 19, 2005Chunghwa Picture Tubes, Ltd.Package structure of light emitting diode
US20050087866 *Apr 16, 2004Apr 28, 2005Shih-Chang SheiFlip-chip light emitting diode package structure
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8530920 *Apr 13, 2011Sep 10, 2013Sunonwealth Electric Machine Industry Co., Ltd.Packaging structure for plural bare chips
US9064773 *Mar 15, 2013Jun 23, 2015Lg Innotek Co., Ltd.Light emitting device package
US20120224366 *Apr 13, 2011Sep 6, 2012Chong-Han TsaiPackaging Structure for Plural Bare Chips
US20140117357 *Mar 15, 2013May 1, 2014Lg Innotek Co., Ltd.Light emitting device package
Classifications
U.S. Classification257/98, 257/E33.056
International ClassificationH01L33/62
Cooperative ClassificationH01L33/62, H01L2224/16
European ClassificationH01L33/62
Legal Events
DateCodeEventDescription
Jul 26, 2006ASAssignment
Owner name: SAMSUNG ELECTRO-MECHANICS CO., LTD., KOREA, REPUBL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZAKGEYM, ALEXANDER L VOVICH;CHOI, SEOG MOON;LEE, SUNG JUN;REEL/FRAME:018092/0753;SIGNING DATES FROM 20060711 TO 20060720
Jul 22, 2010ASAssignment
Owner name: SAMSUNG LED CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG ELECTRO-MECHANICS CO., LTD.;REEL/FRAME:024723/0532
Effective date: 20100712
Jul 25, 2012FPAYFee payment
Year of fee payment: 4
Aug 7, 2012ASAssignment
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: MERGER;ASSIGNOR:SAMSUNG LED CO., LTD.;REEL/FRAME:028744/0272
Effective date: 20120403