|Publication number||US7492026 B2|
|Application number||US 11/323,074|
|Publication date||Feb 17, 2009|
|Filing date||Dec 30, 2005|
|Priority date||Dec 30, 2004|
|Also published as||EP1677364A1, US7713766, US20060145282, US20090075410|
|Publication number||11323074, 323074, US 7492026 B2, US 7492026B2, US-B2-7492026, US7492026 B2, US7492026B2|
|Inventors||Danielle Thomas, Maurice Rivoire|
|Original Assignee||Stmicroelectronics S.A.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (1), Referenced by (4), Classifications (15), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the field of micro-electronics and more specifically to light sensors associated with an integrated circuit.
2. Discussion of the Related Art
Light sensors are devices which enable turning light signal into an electric signal. Several millions of these sensors can be distributed on a surface to create an electric image comprising millions of points. Usually, a sensor is formed of a light-emitting diode and of a MOS circuit enabling collecting and processing the electric signal issued by the light-emitting diode.
The light-emitting diode may be formed of single-crystal silicon. In this case, the MOS circuit and the light-emitting diode coexist in a single-crystal silicon substrate and are located substantially in the same plane. The MOS transistors which enable collection of the electric current of the light-emitting diodes are located between the light-emitting diodes. Such an architecture is expensive since the surface area taken up in the silicon is the sum of the surface areas of the light-emitting diodes and of the MOS transistors. It has a low performance since not all the light reaches the light-emitting diodes and part of it is lost between the light-emitting diodes. The light hitting the light-emitting diodes is likely to diffuse and to disturb the operation of the MOS transistors adjacent to the light-emitting diodes.
Another solution consists of forming the light-emitting diodes above the integrated circuit comprising the MOS transistors. Such a structure is described in US patent application 2004/0135209.
In this type of architecture, the space lost between the light-emitting diodes is minimum, which enables collecting a maximum light signal for a minimum occupied surface area. It is further possible to use the entire surface of the underlying silicon to achieve complex electronic functions such as, for example, the image storage and processing. The light-emitting diode, made of amorphous silicon, exhibits a chromatic response substantially equivalent to that of the human eye. Such is not the case for the light-emitting diodes formed of single-crystal silicon which are particularly sensitive to infrared wavelengths. This chromatic response enables simplifying the arrangement of the color filters in the case where a light-emitting diode matrix capable of rendering a color image is desired to be formed.
However, up to now, such architectures result in low performance for the light sensor, in particular in low light. To collect the current generated by the light-emitting diode, the light-emitting diode junction must be reverse-biased. The light signal creates carriers close to the PN junction of the light-emitting diode. Such carriers are collected in the space charge area of the reverse-biased junction and then form a photocurrent which is processed by the underlying integrated circuit. The reverse biasing of the junction also generates a leakage current, called a dark current, which is a parasitic current. In the case of the light-emitting diode of
An object of the present invention is to provide a light sensor integrable above an integrated circuit and exhibiting optimal electric qualities, that is, both a chromatic response substantially similar to that of the human eye and a minimum dark current.
Another object of the present invention is to provide such a light sensor that can be formed with as few technological steps as possible.
Another object of the present invention is to provide such a light sensor exhibiting a high density of light-emitting diodes of minimum size and comprising color filters which are easy to form.
To achieve these and other objects, the present invention provides a light sensor located above an integrated circuit comprising a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.
According to an embodiment of the present invention, the light sensor comprises a lower chromium electrode in electric contact with the lightly-doped amorphous silicon.
According to an embodiment of the present invention, the light sensor comprises an upper ITO electrode in electric contact with heavily-doped amorphous silicon.
According to an embodiment of the present invention, the interfaces between the electrodes and the amorphous silicon layers are planar.
According to an embodiment of the present invention, the lower electrode is in contact with heavily-doped P-type amorphous silicon.
According to an embodiment of the present invention, the upper electrode is in electric contact with a heavily-doped N-type amorphous silicon layer.
The present invention also aims at an image sensor formed of light-emitting diodes such as mentioned hereabove.
According to an embodiment of the present invention, the repetition step of the light-emitting diodes is smaller than 1.5 μm.
The present invention also aims at a communicating object comprising an image sensor such as mentioned hereabove.
The present invention also aims at a method for forming a light sensor located above an integrated circuit comprising the steps of forming an integrated circuit comprising at its upper surface a first insulating component; depositing a second insulating layer; creating cavities across the thickness of the second insulating layer; depositing a metal, making the surface planar to leave the metal only in the cavity and to obtain a planar surface above and close to the cavity; depositing an amorphous silicon layer; depositing a doped silicon layer; and depositing an electrode layer.
The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
As usual in the representation of integrated circuits, the scales are not respected in the different cross-section views to better show the different layers and elements of the devices.
In an attempt to simplify the prior art structure illustrated in
The operation of this light-emitting diode is similar to that of the light-emitting diode of prior art. It can be seen that, despite changes in the light-emitting diode structure, the dark current is still significant and even greater than that measured in prior art.
Lower electrode 21 is preferably made of chromium which exhibits a barrier height with respect to amorphous silicon 22 capable of ensuring an electric contact with the lightly-doped N-type amorphous silicon. Those skilled in the art know that an electric contact can also be formed, for example, with a metal and an intermediary heavily-doped N-type silicon layer. In such a case, the forming method is more complex, but the use of chromium, which can exhibit a low adherence on oxide, is avoided. In the illustrated embodiment, this chromium adherence problem is solved by the decrease in the dimensions of the lower electrode and by the fact that the lower electrode is embedded in an insulator layer. Lower electrode 21 is electrically connected to a region 8 of the integrated circuit by a via 9 made of a conductive material.
First amorphous silicon layer 22 is not doped during the deposition. There however exists a natural N-type doping. This amorphous silicon deposited at low temperature (under 200° C.) does not exhibit clusters of measurable size.
Second amorphous silicon layer 23 is P-type doped.
ITO upper electrode 24 is connected to the integrated circuit by a metal connection not shown.
Light-emitting diode 20 of
The structures of
There is no simple explanation for this significant decrease in the dark current. The present inventors however consider that the high dark current of prior art is linked to the presence of drops in the amorphous silicon layer. The device of
The present invention provides for the amorphous silicon to rest on a planar surface across its entire useful surface and at least at the immediate periphery of this useful surface. A surface obtained by a chem.-mech polishing is considered as planar in the context of the present invention. A layer deposited on a surface exhibiting steps greater than 20 nm is considered as non-planar in the context of the present invention.
It has been seen hereabove that, in the opinion of the present inventors, the dark current is generated by the periphery of the light-emitting diodes. According to the present invention, this contribution to the dark current has been suppressed. It is then possible to significantly decrease the surface of each light-emitting diode while keeping a high ratio between the photocurrent and the dark current. The lower electrode being embedded in insulator, it is no longer useful to use a bonding layer such a titanium nitride shown in
The B, G, R color filters must however also be formed according to the sensor step. These filters are formed from negative photosensitive resists which, once insolated, remain on the image sensor. Such resins are particularly sensitive to parasitic reflections of the light on the sides exhibited by the underlying layers. In other words, to obtain a good definition for these negative resins, it is necessary to have perfectly planar underlying surfaces. This is performed according to the present invention without using an intermediary layer capable of making the surface planar.
The integrated circuit underlying the image sensor may be an integral part of a communication object such as a digital photographic camera, a fax, a portable phone, or a laptop computer. The integrated circuit may also actively take part in the operation of the communication object in which it is inserted.
An embodiment of light-emitting diodes according to
The present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the metal of the lower electrode may be different, intermediary amorphous silicon layers may be added, the dopings of the amorphous silicon layers may be modified.
The light-emitting diode is formed by the junction of the P-type and N-type amorphous silicon materials 29 and 22. Heavily-doped N-type amorphous silicon layer 31 is used to obtain an ohmic contact of upper electrode 24 with lightly-doped amorphous silicon 22.
This structure can be made out from those of prior art shown in
Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|US20100103298 *||Oct 7, 2009||Apr 29, 2010||Chang Hun Han||Image Sensor and Method for Manufacturing the Same|
|U.S. Classification||257/444, 257/291, 257/E27.128, 257/458, 257/290, 257/431|
|Cooperative Classification||H01L27/1463, H01L27/14692, H01L31/022408, H01L31/103|
|European Classification||H01L27/146A12, H01L27/146V10, H01L31/103, H01L31/0224B|
|Dec 30, 2005||AS||Assignment|
Owner name: STMICROELECTRONICS S.A., FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:THOMAS, DANIELLE;RIVOIRE, MAURICE;REEL/FRAME:017426/0143
Effective date: 20051208
|Mar 31, 2009||CC||Certificate of correction|
|Jul 25, 2012||FPAY||Fee payment|
Year of fee payment: 4
|Jul 22, 2016||FPAY||Fee payment|
Year of fee payment: 8