Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7498230 B2
Publication typeGrant
Application numberUS 11/706,820
Publication dateMar 3, 2009
Filing dateFeb 13, 2007
Priority dateFeb 13, 2007
Fee statusPaid
Also published asUS8076727, US20080191350, US20090146200
Publication number11706820, 706820, US 7498230 B2, US 7498230B2, US-B2-7498230, US7498230 B2, US7498230B2
InventorsKie Y. Ahn, Leonard Forbes
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Magnesium-doped zinc oxide structures and methods
US 7498230 B2
Abstract
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
Images(4)
Previous page
Next page
Claims(17)
1. A method of forming a transparent conducting oxide component, comprising:
forming a plurality of chemically adhered monolayers on a substrate, including:
depositing a first monolayer including zinc;
depositing a second monolayer including magnesium;
processing the plurality of chemically adhered monolayers to form a magnesium-doped zinc oxide, wherein processing includes;
annealing the plurality of chemically adhered monolayers to form a substantially uniform chemical mixture of the first and second monolayers.
2. The method of forming a transparent conducting oxide component according to claim 1, wherein depositing at least a first monolayer including zinc includes depositing a zinc oxide monolayer.
3. The method of forming a transparent conducting oxide component according to claim 1, wherein depositing at least a second monolayer including magnesium includes depositing a magnesium oxide monolayer.
4. The method of forming a transparent conducting oxide component according to claim 1, wherein processing the plurality of chemically adhered monolayers includes oxidizing one or more metallic monolayers to form a magnesium-doped zinc oxide.
5. The method of forming a transparent conducting oxide component according to claim 1, wherein processing the plurality of chemically adhered monolayers includes processing substantially amorphous monolayers at a temperature that forms a substantially amorphous magnesium-doped zinc oxide.
6. The method of forming a transparent conducting oxide component according to claim 1, wherein processing the plurality of chemically adhered monolayers includes processing the monolayers at a temperature that forms a substantially nanocrystalline magnesium-doped zinc oxide.
7. A method of forming an image sensor, comprising:
forming an array of active pixel sensors on a substrate;
forming a number of signal amplifiers coupled to pixel sensors in the array;
forming a magnesium-doped zinc oxide transparent conducting oxide structure coupled to the active pixel sensors and the signal amplifiers, including:
forming a plurality of chemically self-limiting monolayers, including:
depositing at least a first monolayer including zinc;
depositing at least a second monolayer including magnesium; and
annealing the plurality of chemically self-limiting monolayers to form a substantially uniform chemical mixture of the first and second monolayers.
8. The method of forming an image sensor according to claim 7, wherein the image sensor is formed using only complementary metal oxide semiconductor (CMOS) processing techniques.
9. The method of forming an image sensor according to claim 8, further including forming programmable logic circuitry on the same substrate as the array of active pixel sensors.
10. The method of forming an image sensor according to claim 9, further including forming a memory array on the same substrate as the array of active pixel sensors.
11. The method of forming an image sensor according to claim 7, wherein depositing at least a first monolayer including zinc includes depositing a ZnO monolayer.
12. The method of forming an image sensor according to claim 7, wherein depositing at least a second monolayer including magnesium includes depositing a MgO monolayer.
13. A method of forming an electrical device, comprising:
forming a first electrical component on a substrate;
forming a second electrical component electrically separate from the first electrical component;
forming a magnesium-doped zinc oxide transparent conducting oxide structure electrically connecting the first electrical component and the second electrical component, including:
forming a plurality of chemically adhered monolayers, at least two of which have different chemistries, including:
depositing at least a first monolayer including zinc;
depositing at least a second monolayer including magnesium; and
annealing the plurality of chemically adhered monolayers to form a chemical mixture of the first and second monolayers.
14. The method of forming an electrical device according to claim 13, wherein depositing at least a first monolayer including zinc includes atomic layer deposition (ALD) of a ZnO monolayer.
15. The method of forming an electrical device according to claim 14, wherein atomic layer deposition (ALD) of a ZnO monolayer includes oxidizing a layer formed by a diethylzinc precursor.
16. The method of forming an electrical device according to claim 13, wherein depositing at least a second monolayer including magnesium includes atomic layer deposition (ALD) of a MgO monolayer.
17. The method of forming an electrical device according to claim 16, wherein atomic layer deposition (ALD) of a MgO monolayer includes oxidizing a layer formed by a precursor chosen from a list consisting of Mg(thd)2, Mg2(thd)4, and CP2Mg.
Description
TECHNICAL FIELD

This application relates generally to transparent conducting oxide materials, fabrication methods, and electronic devices in which such conducting oxides are used.

BACKGROUND

Transparent conducting oxides (TCOs) are extensively used in electronic applications where electrical conduction and optical transparency are both required. Some example applications include liquid crystal displays (LCDs) organic light emitting diodes (LEDs), solar cells, etc. Presently, indium tin oxide (ITO) is widely used because of it's high transparency, low resistivity, and high work function. One drawback to ITO is limited chemical stability at higher temperatures.

Magnesium-doped zinc oxide materials are a promising alternative to ITO due to properties such as a wide band gap, and compatibility with gallium nitride, low electrical resistivity, high transparency, etc. However, magnesium-doped zinc oxide formation methods such as molecular beam epitaxy (MBE) or sputtering do not provide films or other structures of the quality, ease of manufacture, and cost necessary for some device applications.

What are needed are methods to form magnesium-doped zinc oxide films that produce improved structures with improved properties such as transparency, resistivity, crystallinity, step coverage, mechanical properties, etc. What are also needed are improved magnesium-doped zinc oxide films, structures, etc. and devices utilizing these structures to take advantage of the improved properties.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a surface of an electronic device in a stage of processing according to an embodiment of the invention.

FIG. 1B shows a surface of an electronic device in another stage of processing according to an embodiment of the invention.

FIG. 2 shows a method of forming a material layer or structure according to an embodiment of the invention.

FIG. 3 shows a material deposition system according to an embodiment of the invention.

FIG. 4 shows a block diagram of an electronic device according to an embodiment of the invention.

FIG. 5 shows a block diagram of an image sensor according to an embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.

The terms “wafer” and “substrate” used in the following description include any structure having an exposed surface with which to form an electronic device or device component such as a component of an integrated circuit (IC). The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing and may include other layers, such as silicon-on-insulator (SOI), etc. that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors. The term transparent is defined as a property of a material that transmits a substantial portion of incident electromagnetic energy in a give frequency range. Examples of electromagnetic energy ranges include visible frequency light, infrared, ultraviolet, etc. or combinations of frequency ranges. The term monolayer is defined as a material layer that is substantially one molecule thick. In some embodiments, one molecule includes one atom, while other molecules are comprised of several atoms. The term monolayer is further defined to be substantially uniform in thickness, although slight variations of between approximately 0 to 2 monolayers results in an average of a single monolayer as used in description below.

The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on,” “side” (as in “sidewall”), “higher,” “lower,” “over,” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

FIG. 1A shows a substrate surface 100 of an electrical device such as a semiconductor based device. The surface 100 includes variations in surface topography as illustrated by feature 110 such as a trench. Although a trench 110 is illustrated as an example, other variations in topography, both above and below an average surface level are useful to describe embodiments of the invention.

An electronic device 120 is also shown in a rough block diagram form in FIG. 1A. Examples of electronic devices 120 include optical electronic devices such as active pixel sensors, photovoltaic devices, light emitting diode (LED) devices, plasma display screen devices etc. Other devices that benefit from adjacent structures with optical transparency are within the scope of the invention.

FIG. 1B shows a deposited transparent conducting oxide layer 130 including magnesium and zinc formed over the surface 100. In one embodiment, the transparent conducting oxide layer 130 includes a magnesium-doped zinc oxide layer. As discussed above, magnesium-doped zinc oxide provides a number of useful properties over other transparent conducting oxides such as indium tin oxide. Magnesium-doped zinc oxides provide a wide band gap, compatibility with gallium nitride, low resistivity, high transparency, etc. The layer 130 is shown forming a conformal layer over challenging topography such as feature 110. The layer 130 is also shown covering at least a portion of the electronic device 120.

FIG. 1B illustrates an incoming beam 140 of electromagnetic energy such as visible frequency light, UV light, etc. Selected devices within the scope of the invention include devices such as solar cells, gas sensor components, active pixel sensors, etc. that benefit from the ability to receive the incoming beam through a transparent layer 130. FIG. 1B also illustrates an outgoing beam 142. Selected devices within the scope of the invention include likewise include devices such as light emitting diodes, plasma display screen emitters, etc. that benefit from the ability to transmit an outgoing beam through a transparent layer 130. One use of transparent conducting oxides in conjunction with devices such as these includes interconnection circuitry between devices, to an edge of an array or a chip, to a power supply, etc. Another use of transparent conducting oxides in conjunction with devices such as these includes conducting layer components of devices themselves.

The transparent conducting oxide layer 130 is formed using monolayer deposition methods as described in embodiments below. Methods include atomic layer deposition (ALD) techniques, chemically self-limiting techniques, or other techniques that form monolayers with controlled thickness. As defined above, the term monolayer defines a layer that is substantially one molecule or one atom thick. Although substantially one layer thick, some variation on the order of 0 to 2 molecules is within the scope of the invention.

The methods described form a unique structure compared to other deposition methods. Using monolayer deposition methods described below, a transparent conducting oxide structure can be formed with step coverage over surface topography that is superior to other deposition techniques such as conventional CVD, MBE, sputtering, etc. Selected monolayer processing methods can provide a substantially amorphous transparent conducting oxide structure that is not possible using other deposition techniques. Other processing variations provide a fine crystal distribution such as a nanocrystalline transparent conducting oxide structure. Micro-scale and nano-scale crystal structures provide unique physical properties such as highly durable films.

FIG. 2 shows a flow diagram of an example method of forming a transparent conducting oxide according to an embodiment of the invention. In operation 210, a monolayer that includes zinc is deposited. In one embodiment, the first monolayer is zinc oxide. One example of zinc oxide includes ZnO. Other examples of zinc oxide include ZnO2. In one embodiment the monolayer is zinc metal.

In operation 220, a monolayer that includes magnesium is deposited. In one embodiment, the second monolayer is magnesium oxide. A primary example of magnesium oxide includes MgO. In one embodiment the monolayer is magnesium metal.

Several layers including zinc containing layers and magnesium containing layers can be built up to form a laminate structure. More layers can be used to form thicker structures. Further, as discussed in more detail below, the relative number of each layer can be adjusted to provide any desired ratio between zinc and magnesium. By using monolayer deposition, the thickness and/or the ratio between layer materials is precisely controlled. Although two layers including zinc and magnesium are described, the invention is not so limited. Other layers are also included in selected embodiment to provide additional chemical and structural options.

In operation 230, the layers in the laminate are processed to form a transparent conducting oxide structure. Processing of oxide layer embodiments such as ZnO/MgO includes annealing or activating diffusion processes to mix the oxide layers and provide a magnesium-doped zinc oxide. Processing of metal layer embodiments such as Zn/Mg includes oxidizing the layers and mixing the layer to provide a magnesium-doped zinc oxide. In one embodiment mixing includes processes such as annealing, or diffusion mixing. Other embodiments include depositing both a metal layer and an oxide layer to form a laminate such as ZnO/Mg with subsequent processing to form a magnesium-doped zinc oxide. Final chemistry of the magnesium dopant and zinc oxide matrix will depend on the application of the transparent conducting oxide and any related electronic device.

Processing variable such as temperature and pressure, duration, etc. are chosen to tailor a desired structure morphology. For example, in one embodiment the individual layers in the laminate are deposited in a substantially amorphous state. By processing at a low temperature, the amorphous characteristics of the original layer is substantially preserved, and the resulting transparent conducting oxide is substantially amorphous. Likewise, other processing variables can also be chosen to produce a micro-crystalline or nano-crystalline transparent conducting oxide microstructure. As mentioned above, microstructures such as nano-crystallinity provide enhanced properties such as improved film durability.

As discussed above, monolayer deposition of material layers provides a number of useful properties for transparent conducting oxide structures. One method of depositing monolayers includes atomic layer deposition (ALD). ALD was developed in the early 1970's as a modification of chemical vapor deposition (CVD) and is also called “alternatively pulsed-CVD.” In ALD, gaseous precursors are introduced one at a time to the substrate surface mounted within a reaction chamber (or reactor). This introduction of the gaseous precursors takes the form of pulses of each gaseous precursor. Between the pulses, the reaction chamber is purged with a gas, which in many cases is an inert gas, or evacuated.

In a chemisorption-saturated ALD (CS-ALD) process, during the first pulsing phase, reaction with the substrate occurs with the precursor saturatively chemisorbed at the substrate surface. Subsequent pulsing with a purging gas removes precursor excess from the reaction chamber.

The second pulsing phase introduces another precursor on the substrate where the growth reaction of the desired film takes place. Subsequent to the film growth reaction, reaction byproducts and precursor excess are purged from the reaction chamber. With favorable precursor chemistry where the precursors adsorb and react with each other on the substrate aggressively, one ALD cycle can be preformed in less than one second in properly designed flow type reaction chambers. Typically, precursor pulse times range from about 0.5 sec to about 2 to 3 seconds.

In ALD, the saturation of all the reaction and purging phases makes the growth self-limiting. This self-limiting growth results in large area uniformity and conformality, which has important applications for applications such as planar substrates, deep trenches, and in material deposition on porous materials, other high surface area materials, powders, etc. Examples include, but are not limited to porous silicon, alumina powders, etc. Significantly, ALD provides for controlling deposition thickness in a straightforward, simple manner by controlling the number of growth cycles.

The precursors used in an ALD process may be gaseous, liquid or solid. Typically, liquid or solid precursors are volatile. The vapor pressure must be high enough for effective mass transportation. Also, solid and some liquid precursors are heated inside the reaction chamber and introduced through heated tubes to the substrates. The necessary vapor pressure is reached at a temperature below the substrate temperature to avoid the condensation of the precursors on the substrate. Due to the self-limiting growth mechanisms of ALD, relatively low vapor pressure solid precursors can be used though evaporation rates may somewhat vary during the process because of changes in their surface area.

There are several other considerations for precursors used in ALD. Thermal stability of precursors at the substrate temperature is a factor because precursor decomposition affects the surface control. ALD is heavily dependent on the reaction of the precursor at the substrate surface. A slight decomposition, if slow compared to the ALD growth, can be tolerated.

The precursors chemisorb on or react with the surface, though the interaction between the precursor and the surface as well as the mechanism for the adsorption is different for different precursors. The molecules at the substrate surface react aggressively with the second precursor to form the desired solid film. Additionally, precursors should not react with the film to cause etching, and precursors should not dissolve in the film. Using highly reactive precursors in ALD contrasts with the selection of precursors for conventional CVD.

The by-products in the reaction are typically gaseous in order to allow their easy removal from the reaction chamber. Further, the by-products should not react or adsorb on the surface.

In a reaction sequence ALD (RS-ALD) process, the self-limiting process sequence involves sequential surface chemical reactions. RS-ALD relies on chemistry between a reactive surface and a reactive molecular precursor. In an RS-ALD process, molecular precursors are pulsed into the ALD reaction chamber separately. The metal precursor reaction at the substrate is typically followed by an inert gas pulse or chamber evacuation to remove excess precursor and by-products from the reaction chamber prior to pulsing the next precursor of the fabrication sequence.

Using RS-ALD, films can be layered in equal metered sequences that are essentially identical in chemical kinetics, deposition per cycle, composition, and thickness. RS-ALD sequences generally deposit less than a full layer per cycle. Typically, a deposition or growth rate of about 0.25 to about 2.00 Å per RS-ALD cycle can be realized.

RS-ALD provides for high continuity at an interface compared with other techniques such as CVD; conformality over difficult topography on a substrate; use of low temperature and mildly oxidizing processes; growth thickness dependent solely on the number of cycles performed, and ability to engineer multilayer laminate films with resolution of one to two monolayers. RS-ALD allows for deposition control on the order on monolayers and the ability to deposit monolayers of amorphous films.

RS-ALD processes provide for robust deposition of films or other structures. Due to the unique self-limiting surface reaction materials that are deposited using RS-ALD, such films are free from processing challenges such as first wafer effects and chamber dependence. Accordingly, RS-ALD processes are easy to transfer from development to production and from 200 to 300 mm wafer sizes in production lines. Thickness depends solely on the number of cycles. Thickness can therefore be dialed in by controlling the number of cycles.

Laminate structures of multiple layers formed using ALD can also be subsequently processed to mix the individual layers together. For example, a laminate structure can be annealed to mix a plurality of different layers together, thus forming an alloy or a mixture of layer chemistries. By forming a laminate structure using ALD, and subsequently mixing the layers, the chemistry of the resulting structure is precisely controlled. Because the laminate is made up of self-limiting monolayers over a known surface area, the number of molecules from each individual layer are known to a high degree of accuracy. Chemistry can be controlled by adding or subtracting one or more layers in the laminate.

FIG. 3 shows an embodiment of an atomic layer deposition system for processing zinc containing layers and magnesium containing layers according to the teachings of the present invention. The elements depicted are those elements necessary for discussion of the present invention such that those skilled in the art may practice the present invention without undue experimentation.

In FIG. 3, a substrate 310 is located inside a reaction chamber 320 of ALD system 300. Also located within the reaction chamber 320 is a heating element 330 which is thermally coupled to substrate 310 to control the substrate temperature. A gas-distribution fixture 340 introduces precursor gases to the substrate 310. Each precursor gas originates from individual gas sources 351-354 whose flow is controlled by mass-flow controllers 356-359, respectively. The gas sources 351-354 provide a precursor gas either by storing the precursor as a gas or by providing a location and apparatus for evaporating a solid or liquid material to form the selected precursor gas.

Also included in the ALD system 300 are purging gas sources 361, 362, each of which is coupled to mass-flow controllers 366, 367, respectively. The gas sources 351-354 and the purging gas sources 361-362 are coupled by their associated mass-flow controllers to a common gas line or conduit 370 which is coupled to the gas-distribution fixture 340 inside the reaction chamber 320. Gas conduit 370 is also coupled to vacuum pump, or exhaust pump, 381 by mass-flow controller 386 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from the gas conduit 370.

Vacuum pump, or exhaust pump, 382 is coupled by mass-flow controller 387 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from the reaction chamber 320. For convenience, control displays, mounting apparatus, temperature sensing devices, substrate maneuvering apparatus, and necessary electrical connections as are known to those skilled in the art are not shown in FIG. 3. Although ALD system 300 is illustrated as an example, other ALD systems may be used.

Using ALD methods as described above there are a number of different precursor chemistries that can be used to form monolayers including zinc and monolayers including magnesium. One example chemistry for zinc oxide includes diethylzinc (DEZn) and H2O as reactant gasses. In one example, self-limiting growth occurs at substrate temperatures ranging from 105 to 165° C. A high electron mobility of 30 cm2/V s under such conditions is obtained for films only 220 nm thick. This mobility is higher than mobility for films grown by conventional CVD.

One example of chemistry for magnesium oxide includes Mg(thd)2 oxidized in ozone. Examples of substrate temperatures include 180 to 450° C. In some specific embodiments, the substrate temperatures range from 225 to 250° C. Another example of chemistry for magnesium oxide includes oxidizing bis(cyclopentadienyl)magnesium (CP2Mg). In one example substrate temperatures used are above 500° C. Other examples of chemistry for magnesium oxide includes oxidized [Mg2(thd)4], or oxidized [Mg2(thd)2 crystallized from ethanol (EtOH)2], where thd=2,2,6,6-tetramethyl-3,5-heptanedione. In one example H2O was used to oxidize precursors at a substrate temperature of between approximately 325-425° C.

Although a number of examples of precursors, oxidizers, and process conditions are listed above, the invention is not so limited. One of ordinary skill in the art, having the benefit of the present disclosure will recognize that other chemistries and process conditions that form monolayers with zinc and magnesium can be used.

FIG. 4 illustrates an electronic device 400 that includes transparent conducting oxide structures formed using monolayer deposition methods such as ALD as described above. The electronic device 400 includes a first component 420 that benefits from transparent conducting structures. Examples of first component 420 includes LEDs, active pixel sensors, solar cells, a liquid crystal display (LCD) region, a controlled visibility region of a smart window, gas sensors, electroluminescent (EL) devices etc. In these examples, device operation is improved with transparency to electromagnetic energy such as visible wavelength light, infrared light, ultra violet light, etc.

In one embodiment, the device 400 further includes a power source 430. The power source 430 is electrically connected to the first component 420 using interconnecting circuitry 440. In one embodiment, the interconnecting circuitry 440 includes magnesium-doped zinc oxide formed as a transparent conducting oxide using methods described above. In addition to depositing material as described above, techniques such as lithography with masks, and/or etching etc. can be used to pattern conducting circuitry.

In one embodiment, the device 400 further includes a secondary component 410. The secondary component is electrically connected to the first component 420 using interconnecting circuitry 442. Likewise, in one embodiment, the interconnecting circuitry 442 includes magnesium-doped zinc oxide formed as a transparent conducting oxide using methods described above. Examples of secondary components 410 include signal amplifiers, semiconductor memory, logic circuitry or other microprocessing circuits, etc. Aside from interconnecting circuitry, in one embodiment, the first component 420 and/or the secondary component 410 includes a magnesium-doped zinc oxide structure formed as a transparent conducting oxide using methods described above.

FIG. 5 shows one specific example of an electronic device including transparent conducting oxides formed as described above. An imaging device 500 is shown. The imaging device includes an image sensor 510, with a pixel array 512. In one embodiment the pixel array 512 is coupled to additional row circuitry 514 and column circuitry 516. Examples of row and/or column circuitry includes drivers, amplifiers, decoders, etc. In one embodiment, the image sensor 510 is formed on a single semiconductor substrate using CMOS processes.

FIG. 5 further shows a logic device 520 coupled to the image sensor 510 through circuitry 522. In one embodiment, the logic device 520 includes a programmable logic circuit. Other logic devices include microprocessors, etc. In one embodiment, the logic device 520 and circuitry 522 are formed on the same semiconductor substrate as the image sensor 510.

A memory device 530 is also shown in FIG. 5. In one embodiment, the memory device is coupled to the logic device 520 using circuitry 524. In one embodiment, the memory device 530, the logic device 520 and circuitry 522, 524 are formed on the same semiconductor substrate as the image sensor 510. Using CMOS processing provides the ability to form a variety of different devices, such as logic, memory, and image sensing on a single substrate. Using monolayer deposition processes as described above, magnesium-doped zinc oxide conductors can further be formed on a single substrate using CMOS processing equipment.

As shown, example applications of transparent conducting oxides include circuitry 522, 524 and circuitry within the image sensor 510. Although interconnecting circuitry applications for transparent conducting oxides are discussed, the invention is not so limited. Other regions and structures of semiconductor chips where properties such as transparency and conductivity are important are within the scope of the invention.

While a number of improved features of embodiments of the invention are described, the above lists are not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US6767795 *Jan 17, 2002Jul 27, 2004Micron Technology, Inc.Highly reliable amorphous high-k gate dielectric ZrOXNY
US6790791 *Aug 15, 2002Sep 14, 2004Micron Technology, Inc.Lanthanide doped TiOx dielectric films
US6921702 *Jul 30, 2002Jul 26, 2005Micron Technology Inc.Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US7374964 *Feb 10, 2005May 20, 2008Micron Technology, Inc.Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7390756 *Apr 28, 2005Jun 24, 2008Micron Technology, Inc.Atomic layer deposited zirconium silicon oxide films
US20020111001 *Feb 9, 2001Aug 15, 2002Micron Technology, Inc.Formation of metal oxide gate dielectric
US20050164521 *Mar 21, 2005Jul 28, 2005Micron Technology, Inc.Zr-Sn-Ti-O films
US20060024975 *Aug 2, 2004Feb 2, 2006Micron Technology, Inc.Atomic layer deposition of zirconium-doped tantalum oxide films
Non-Patent Citations
Reference
1Ahn, K Y., "Atomic Layer Deposited Titanium-Doped Indium Oxide Films", U.S. Appl. No. 11/400,836, filed Apr. 7, 2006.
2Bhattacharya, P , et al., "Fabrication of stable wide-band-gap ZnO/MgO multilayer thin films", Applied Physics Letters, 83(10), (Sep. 8, 2003),2010-2012.
3Bundesmann, C , et al., "Raman scattering in ZnO thin films doped with Fe, Sb, Al, Ga, and Li", Applied Physics Letters, 83(10), (Sep. 8, 2003),1974-76.
4Cheng, X M., et al., "Magnetic properties of expitaxial Mn-doped ZnO thin films", Journal of Applied Physics, 93(10), (May 15, 2003),7876-78.
5Han, J , et al., "Varistor behaviour of Mn-doped ZnO ceramics", Journal of the European Ceramic Society, 22, (2002),1653-60
6Hatanpaa, Timo , et al., "Properties of [Mg2(thd)4] as a Precursor for Atomic Layer Deposition of MgO Thin Films and Crystal Structures of [Mg2(thd)4] and [Mg(thd)2(EtOH)2]", Chem. Mater., 11(7), (Jun. 29, 1999),1846-1852.
7Huang, R , et al., "The surface morphology of atomic layer deposited magnesia", J. Mater. Sci Lett., 12, (1993),1444-6.
8Jeong, Sang-Hun H., et al., "Photoluminescence dependence of ZnO films grown on Si(100) by radio frequency magnetron sputtering on the growth ambient", Applied Physics Letters, 82(16), (Apr. 21, 2003),2625-2627.
9Kim, T S., et al., "Splitting of the valence band for polycrystalline ZnO", Journal of the Korean Physical Society, 38(1), (2001),42-6.
10Ko, H J., et al., "Photoluminescence properties of ZnO epilayers grown on CaF2(111) by plasma assisted molecular beam epitaxy", Applied Physics Letters, 76(14), (Apr. 3, 2000), 1905-7.
11Liu, Z F., "Epitaxial growth and properties of Ga-doped ZnO films grown by pulsed laser depostion", Journal of Crystal Growth, vol. 259, No. 1, (2003),130-136
12Look, D C., "Recent advances in ZnO materials and devices", Materials Science and Engineering, B80, (2001),383-87.
13Lu, Y F., "The effects of thermal annealing on ZnO thin films grown by pulsed laser depostion", Journal of Applied Physics, vol. 88, No. 1, (Jul. 1, 2000),498-502.
14Makino, T , et al., "Exciton spectra of ZnO epitaxial layers on lattice-matched substrates grown with laser-molecular-beam epitaxy", Applied Physics Letters, 76(24), (Jun. 12, 2000),3549-51.
15Minemoto, Takashi , et al., "Preparation of Zn1-x MgxO films by radio frequency magnetron sputtering", Thin Solid Films, 372, (2000),173-6.
16Ohtomo, A , et al., "MgxZn1 A? xO as a IIA?VI widegap semiconductor alloy", Applied Physics Letters, 72(19), (May 11, 1998),2466-2468.
17Pearton, "Recent advances in processing of ZnO", Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol. 22, Issue 3, (May 2004),932-948.
18Putkonen, Matti , et al., "Enhanced growth rate in atomic layer epitaxy deposition of magnesium oxide thin films", J. Mater. Chem., 9, (2000),1857-61.
19Ryu, Y R., et al., "Optical and structural properties of ZnO films deposited on GaAs by pulsed laser deposition", Journal of Applied Physics, 88(1), (2000),201-.
20Sang, Baosheng , et al., "Growth of transparent conductive oxide ZnO films by atomic layer deposition", Jpn. J. Appl. Phys., 35, (1996),L602-605.
21Sanon, G , et al., "Band gap narrowing and band structure in degenerate tin oxide (SnO2) films", Physical Review B, 44(11), (1988),5672-80.
22Semilius, B E., et al., "Band-gap tailoring of ZnO by means of heavy Al doping", Physical Review B,37(7), (1988),10244-48.
23Shan, F K., "Band gap energy of pure and Al-doped ZnO thin films", Journal of European Ceramic Society, 24, (2004),1869-72.
24Shan, F K., et al., "Blue shift of near band edge emission in Mg doped ZnO thin films and aging", J. Appl. Phys., 95(9), (2004),4772-76.
25Shan, F K., et al., "Optical properties of pure and Al doped ZnO thin films fabricated with plasma produced by excimer laser", Thin Solid Films, 435, (2003), 174-8.
26Shan, F K., et al., "Structral properties of zinc oxide thin films by fabrication conditions in pulsed laser deposition", J. Korean Phys. Soc. 42, (2003),S1157-60.
27Shan, F K., et al., "Substrate effects of ZnO thin films prepared by PLD technique", Journal of the European Ceramic Society, 24, (2004),1015-18.
28Sneh, Ofer , "Thin film atomic layer deposition equipment for semiconductor processing", Thin Solid Films, 402, (2002),248-261.
29So, S , et al., "Improvement in the electrical stability of semiconducting ZnO ceramic varistors with SiO2 additive", J. Dorean Phys. Soc., 40, (2002),925-9.
30Srikant, V , "On the optical band gap of zinc oxide", Journal of Applied Physics, 83(10), (May 15, 1998),5447-5451.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8076727 *Feb 11, 2009Dec 13, 2011Micron Technology, Inc.Magnesium-doped zinc oxide structures and methods
US8283744Mar 24, 2009Oct 9, 2012Micron Technology, Inc.Molybdenum-doped indium oxide structures and methods
Classifications
U.S. Classification438/311, 438/603, 257/E21.278, 257/E21.17, 257/E21.32, 438/604, 257/E21.317
International ClassificationH01L21/8222, H01L21/331
Cooperative ClassificationY02E10/50, H01L31/1884, H01L27/14685, H01L27/14643, H01L31/022466
European ClassificationH01L31/0224C, H01L27/146V2, H01L31/18J
Legal Events
DateCodeEventDescription
Aug 8, 2012FPAYFee payment
Year of fee payment: 4
Feb 13, 2007ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AHN, KIE Y.;FORBES, LEONARD;REEL/FRAME:018988/0728;SIGNING DATES FROM 20070206 TO 20070208
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AHN, KIE Y.;FORBES, LEONARD;SIGNING DATES FROM 20070206 TO 20070208;REEL/FRAME:018988/0728