|Publication number||US7517807 B1|
|Application number||US 11/493,231|
|Publication date||Apr 14, 2009|
|Filing date||Jul 26, 2006|
|Priority date||Jul 26, 2006|
|Also published as||US20090117722|
|Publication number||11493231, 493231, US 7517807 B1, US 7517807B1, US-B1-7517807, US7517807 B1, US7517807B1|
|Inventors||Jesse Berkley Tucker, Kevin Sean Matocha, Peter Wilson Waldrab, James Howard Schermerhorn, Matthew Morgan Edmonds|
|Original Assignee||General Electric Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Non-Patent Citations (8), Referenced by (8), Classifications (15), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates generally to semiconductor devices and, more particularly, to semiconductor devices with self-aligned ion implant regions.
Silicon carbide (SiC) is an attractive alternative to silicon for high voltage, high power applications due to SiC's material properties. For example, SiC's wide band gap and high thermal conductivity facilitate elevated temperature operation, and SiC's high electron mobility enables high-speed switching.
For certain devices, such as metal oxide semiconductor field effect transistors (MOSFET), it is desirable to control the channel dimensions. In particular, to achieve a low on-state resistance, it is desirable to reduce the channel width of the device. However, conventional techniques typically employ multiple lithography steps, which introduce overlay misalignments, thereby limiting the resolution of the channel length. For example, for a power MOSFET device, the channel formation typically involves the deposition and patterning of at least two photolithographic layers. For conventional processes, each of the photolithography processes typically incorporates a separate masking layer. Disadvantageously, relying on the alignment of multiple lithography steps to form the channel of a power MOSFET limits the manufacturability of the channel. Specifically, channel dimensions are generally set on the order of 1 micron or greater to account for any misalignments caused by employing multiple lithography processes with multiple masking layers. As a result, SiC MOSFETs are typically designed to have channel lengths sufficiently greater than 1 micron, in order to fall within conventional tolerance limits. These larger channel dimensions disadvantageously increase both the on-state resistance and the power dissipation of the device.
Thus, there is a need to tightly control channel dimensions for SiC MOSFETs. In addition, there is a need to align the gate with the channel. Accordingly, methods for fabricating semiconductor structures are needed to address these issues.
Briefly, one aspect of the present invention resides in a method for fabricating a semiconductor structure. The method includes forming a carbon masking layer on a semiconductor layer, forming a protective layer on the carbon masking layer, and forming an opening in the protective layer and the carbon masking layer. The method further includes processing the semiconductor layer through the opening to form a first processed region in the semiconductor layer, enlarging the opening in the carbon masking layer and performing an additional processing step on the semiconductor layer through the enlarged opening to form a second processed region in the semiconductor layer.
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
Those skilled in the art will recognize that the methods disclosed herein are described with reference to the fabrication of a single cell of a semiconductor structure. The claimed methods are intended to encompass the fabrication of semiconductor structures with one or more of such cells.
The semiconductor layer 12 may be a semiconductor substrate or an intermediate layer of a structure fabricated on an underlying substrate. For the illustrated embodiment, the semiconductor layer 12 comprises silicon carbide (SiC). There are a number of SiC polytypes, including, without limitation, 3C, 4H, 6H, 15R, 2H, 8H, 10H, 21R and 27R. In certain non-limiting examples, the semiconductor layer 12 comprises a 4H or 6H SiC polytype. The carbon masking layer 10 is particularly beneficial for use in forming SiC structures, in that graphite can withstand the high temperatures (for example, >1400 C) needed for SiC ion implant anneals. However, the present invention is not limited to SiC, and the semiconductor structure may comprise other wide band gap semiconductors, including but not limited to, Gallium Arsenide (GaAs), Aluminum Nitride (AlN) and Gallium Nitride (GaN). The semiconductor layer 12 may be p-type, n-type or undoped. It will be understood by those skilled in the art that “n-type” and “p-type” refer to the majority charge carriers, which are present in a respective layer. For example, in n-type regions, the majority carriers are electrons, and in p-type regions, the majority carriers are holes (the absence of electrons).
For the illustrated DMOSFET example, the semiconductor layer 12 is a n-type SiC epilayer with a thickness of about 11 microns and an impurity concentration of about 9×1015 atoms/cm3, where the epilayer is formed on a n+SiC substrate. This example is purely illustrative and does not limit the invention.
Various techniques may be employed to form the carbon masking layer 10. For certain embodiments, an organic layer 10 is deposited on the semiconductor layer 12. The semiconductor layer 12 and organic layer 10 are then heated to graphitize the organic layer 10. By “graphitize” it is meant that the organic layer is subjected to a heating process to remove substantially all but carbon from the layer, making the remaining layer primarily graphitic. Example organic layers include resins, and in one particular example photoresist is deposited (for example, by spinning or spraying) and baked at a temperature of about 700 degrees Celsius in vacuum or in the presence of an inert ambient, such as argon. The bake-out temperature will depend upon the material being graphitized. In this manner, a graphite masking layer is formed. In other embodiments, a diamond like carbon (DLC) layer 10 is deposited using chemical vapor deposition (CVD) techniques. The thickness of the carbon masking layer 10 will depend upon the subsequent processing steps being performed using the mask. For example, for ion implantation, the mask thickness is selected such that the mask is thick enough to mask the ion implants that are being used. According to particular embodiments, the carbon protective layer 10 has a thickness in a range of about 0.5 microns to about 2.0 microns.
The protective layer 14 is formed of a material with good etch selectivity relative to the carbon masking layer 10. Example materials for the protective layer 14 include silicon nitride (including without limitation, stoichiometric Si3N4 and non-stoichiometric SiNx), silicon dioxide (including without limitation, SiO2 and non-stoichiometric SiOx), aluminum nitride (including without limitation AlN and non-stoichiometric AlNx), indium tin oxide and combinations thereof, nonlimiting examples of which include silicon oxynitride. Depending on the deposition technique, the protective layer 14 may also contain byproducts of the species used to synthesize the material, for example, when forming a silicon nitride layer, Hydrogen may be incorporated. In one illustrated, non-limiting example, the protective layer 14 comprises Si3N4. Various techniques may be employed to deposit the protective layer 14, and the particular technique will depend upon the material being deposited. For particular embodiments Si3N4 is deposited using a plasma enhanced CVD (PECVD) process or a low pressure CVD process (LPCVD). The thickness of the protective layer 14 will depend upon the subsequent processing steps being performed. For example, for ion implantation, the Si3N4 thickness is selected such that the implants can penetrate the Si3N4. According to particular embodiments, the Si3N4 layer has a thickness in a range of about 500 Angstroms to about 5000 Angstroms, and more particularly in a range of about 500 Angstroms to about 1000 Angstroms.
Referring next to
For particular embodiments, an isotropic, dry etching process is then performed to undercut the carbon masking layer 10, as indicated in
For the illustrated embodiments, the processing steps comprise ion implantation (indicated by the vertical arrows in
To form the n+ region 20, a variety of n-type dopants (donors) may be implanted, including but not limited to, nitrogen, phosphorous, arsenic, antimony and combinations thereof. The donors are implanted through the relatively thin protective layer 14 at a temperature in a range of about 25-1000 degrees Celsius. According to a particular example, the n+ implant is performed at about 600 degrees Celsius. For the illustrated example, the n+ region is formed using a shallow n+ implant at a depth in an example range of about 0.1-1 microns. For one example, the depth of the n+ implant is about 0.25 microns. Typically, the n+ ion implantation is performed at energies in a range of about 5-200 keV, and more particularly in a range of about 15-200 keV, with successive single energy implants.
To form the p− well 22, a variety of p-type dopants (acceptors) may be implanted, including but not limited to, aluminum, boron, magnesium, carbon, calcium and combinations thereof. The implants are typically performed at elevated temperatures, for example in a range of about 25-1000 degrees Celsius, and for certain examples at about 1000 degrees Celsius. Typically, the p− ion implantation is performed at energies in a range of about 5-400 keV, with successive single energy implants. For the illustrated example, the depth of the p− well 22 is in a range of about 0.1-2 microns and for certain examples is about 0.7 microns. Example channel lengths dd are in a range of about 0.1-1.5 microns. Beneficially, because the channel length dd is defined using a dry etch process, the channel length dd can be carefully controlled.
For certain embodiments, the masking layers are removed to yield the structure shown in
Various techniques may be employed to form the carbon capping layer 24. For certain embodiments, an organic layer 24 is deposited on the remaining portions of carbon masking layer 10 and on the active region of semiconductor layer 12. The structure is then heated to graphitize the organic layer 24. As noted above, example organic layers include resins, and in one particular example photoresist is deposited (for example, by spinning or spraying) and baked at a temperature of about 700 degrees Celsius. The bake-out temperature will depend upon the material being graphitized. In this manner, a graphite capping layer 24 is formed. In other embodiments, a diamond like carbon (DLC) layer 24 is deposited using chemical vapor deposition (CVD) techniques. The thickness of the carbon capping layer 24 is selected based on the desired spacer thickness. In particular, the thickness of the carbon capping layer 24 sets the lateral spacing from the edges of the first carbon layer 10 to the second graphite layer 32, such that the carbon capping layer 24 covers the channel. For example, the thickness of the carbon capping layer 24 is selected to be slightly larger than the channel length. The channel length is defined as the distance between the edges 21 and 23, which are shown in
The anneal is performed to activate the implants. In one example, the annealing step comprises heating the semiconductor structure to a temperature of at least about 1600 degrees Celsius. Beneficially, the carbon capping layer 24 provides a protective surface for this high temperature anneal. This is in contrast to the SiO2 thin film system employed in U.S. Pat. No. 6,204,151, Peters et al., which must be removed prior to a high temperature anneal.
To finish the fabrication of the desired semiconductor device, various metal deposition and patterning processes are performed. For the illustrated DMOSFET example, a gate contact layer 40 is deposited and patterned, as illustrated for example in
For the illustrated process, ohmic metal patterning processes are then performed. For the illustrated example, a dielectric layer 42 is deposited, as indicated in
Beneficially, the present invention simplifies the fabrication process for power MOSFETs by eliminating the need for a second, tightly aligned photolithography level. In addition, the present invention enables tighter control of the alignment of the n-type and p-type implantations. In this manner, the invention provides a repeatable, controllable means for achieving reduced channel dimensions for power MOSFETs.
Although only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
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|U.S. Classification||438/739, 438/637|
|Cooperative Classification||H01L29/41766, H01L29/7802, H01L29/66068, H01L21/0332, H01L29/1095, H01L21/0465, H01L21/0337|
|European Classification||H01L29/66M4T, H01L21/04H4A10, H01L21/033F4, H01L21/033D, H01L29/78B2|
|Jul 26, 2006||AS||Assignment|
Owner name: GENERAL ELECTRIC COMPANY, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TUCKER, JESSE BERKLEY;MATOCHA, KEVIN SEAN;WALDRAB, PETERWILSON;AND OTHERS;REEL/FRAME:018138/0764
Effective date: 20060724
|Oct 15, 2012||FPAY||Fee payment|
Year of fee payment: 4