|Publication number||US7535209 B2|
|Application number||US 11/240,745|
|Publication date||May 19, 2009|
|Filing date||Sep 30, 2005|
|Priority date||Sep 30, 2005|
|Also published as||CN101310240A, CN101310240B, EP1934671A2, EP1934671B1, US7812583, US20070075698, US20090195233, WO2007040939A2, WO2007040939A3|
|Publication number||11240745, 240745, US 7535209 B2, US 7535209B2, US-B2-7535209, US7535209 B2, US7535209B2|
|Inventors||Xiaoyu Xi, Shyam S. Somayajula|
|Original Assignee||St-Ericsson Sa|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Classifications (6), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention generally relates to management of regulator-induced switching noise for sampled systems.
It is not uncommon for a highly integrated circuit to have a large number of analog blocks and subsystems. One of these blocks/subsystems may be a DC-to-DC voltage regulator, a circuit that converts a DC input voltage to either a higher or a lower DC output voltage to power other blocks/subsystems of the integrated circuit.
One type of voltage regulator is a switching regulator, which is often chosen due to its relatively smaller size and better efficiency than other types of regulators. The switching regulator typically includes an inductor (a stand-alone inductor or an inductor formed from a transformer, as examples) and one or more switches that the regulator opens and closes in a controlled manner to transfer energy between an input voltage source, the inductor and the regulator's output terminal to regulate an output voltage.
In an embodiment of the invention, a system includes sampler that is adapted to sample an input signal and a switching regulator that is separate from the sampler. The switching regulator is adapted to regulate a switching operation of the regulator in response to the sampling by the sampler.
In another embodiment of the invention, a voltage regulator includes an input terminal, an output terminal, an energy storage element, at least one switch and a controller. The input terminal receives an input voltage, and the output terminal provides an output voltage. The switch(es) are coupled to the energy storage element, the input terminal and the output terminal. The controller is adapted to operate the switch(es) to energy and de-energize the energy source element to regulate the output voltage. The controller is adapted to control the operation of the switch(es) to prevent a sampler from sampling noise generated by the voltage regulator.
In yet another embodiment of the invention, a technique includes regulating a switching operation of a switching regulator in response to sampling by a sampler to control a timing of noise that is generated by the switching regulator.
Advantages and other features of the invention will become apparent from the following drawing, description and claims.
The blocks and subsystems of a highly integrated integrated circuit may interfere with each other due to various coupling mechanisms that permit noise that is generated in a particular block/subsystem to propagate to other parts of the integrated circuit. These coupling mechanisms include, for example, supply voltages and wells in which the blocks and subsystems are fabricated, since the supply voltages may be routed to multiple blocks and subsystems and the wells may be fabricated on the same die. As a more specific example,
As a more specific example, the switching regulator 10 may generate switching noise each time a switch of the switching regulator 10 transitions between open (alternatively called “on”) and closed (alternatively called “off”) states. The sharp edge of the resulting switching current may cause the VIN voltage (as an example) to communicate noise to the subsystem 20 in the form of a “ring signal” due to bond wire inductance; and the amplitude of the ring signal may be significant, such as on the order of millivolts.
Furthermore, due to the above-described switching operation of the regulator 10, the resulting large voltage swing of a switching node of the switching regulator 10 may pump enough charge into a well (an n-well, for example) in which the subsystem 20 is fabricated to cause the voltage of the well to bounce. Additionally, the switching regulator 10 may periodically have a large output current that may cause the supply rail 14 to have periodic drops in voltage due to parasitic resistance.
The subsystem 20 includes at least one component, depicted by a sampler, or sampling circuit 30, in
The sampling circuit 30 is coupled to the switching regulator 10. Thus, the sampling circuit 30 may be fabricated in the same well as the regulator 10, may receive the VIN supply voltage, may be coupled to the VIN supply rail 14, etc. Therefore, the above-described potential switching noise from the switching regulator 10 may produce resultant noise in the VS sampled signal due to the following relationships. Assume, for purposes of example, that the switching frequency of the switching regulator 10 is “fsw,” the sampling clock frequency is “fs,” and the bandwidth of the VS signal is “fB” Any harmonics of fsw and fs that are separated by less than the fB bandwidth introduce DC offset or tones within the signal bandwidth of the VS sampled signal due to an aliasing effect. Therefore, one solution to reduce the appearance of an offset or tone within the signal bandwidth is to choose fsw relative to fs to satisfy the following relationship:
|M·f sw−N·fs|>fB Equation 1
If the above-described relationship is not satisfied, then a timing of the switching operation of the switching regulator 10 may be controlled for purposes of preventing noise from the switching regulator 10 from propagating into signals that are generated by the sampled system 20. More particularly, in accordance with some embodiments of the invention, the switching regulator 10 delays a switching event (such as the transition of a switch between open and closed states, for example) when the switching event would otherwise coincide with a time at which the sampling circuit 30 is sampling.
As a more specific example, in accordance with some embodiments of the invention, a clock generator 22 (that also generates the FS signal) of the sampling system 20 generates a signal (called “MASK,” in
In addition to the core 40, the switching regulator 10 includes a controller 80 that controls the switching actions of the NMOSFETs 54 and 64 to regulate the VDD output voltage. More specifically, neglecting for now the noise management features of the regulator 10 (further described below), a pulse width modulation (PWM) controller 84 of the controller 80 generates a pulse width modulated switching control signal (called “PWM” in
During the on time interval 106, the PWM controller 84 asserts, or drives high, the PWM signal, as depicted by the corresponding pulses 100 (pulses 100 a, 100 b, 100 c and 100 d, being depicted as examples) in the PWM switching signal. Each pulse 100 causes the NMOSFET 54 to turn on (i.e., “close”), and due to the complimentary nature of the PWM# signal, the NMOSFET 64 turns off (i.e., “opens”). Therefore, due to this arrangement, during the pulse 100 energy flows from the supply rail 14 and is stored in the inductor 66 to energize the inductor 66. During the subsequent off time interval 108, the pulse 100 disappears to cause the NMOSFET 54 to turn off and the NMOSFET 64 to turn on (due to the assertion of the PWM# signal) to couple the switching node 60 to ground. During the off time interval 108, the inductor 66 is de-energized to communicate energy the load of the regulator 10, as current flows through the inductor 66 to ground.
The PWM control 84 controls the switching cycles to regulate the VDD output voltage. For purposes of example, it is assumed the regulator 10 operates in a continuous mode of operation. By controlling a ratio, called the “duty cycle,” of the on time interval 106 to the duration of the switching cycle 104, the PWM controller 84 may regulate the VDD output voltage. For the Buck core 40, the VDD output voltage is lower than the VIN input voltage and, in general, is proportional to the product of the duty cycle and the VIN input voltage. Assuming a constant period for the switching cycles, by increasing the duration of the on time interval 106, the PWM controller 84 may raise the VDD output voltage; and conversely, by decreasing the duration of the on time interval 106, the PWM controller 84 may decrease the VDD output voltage.
It is noted that many other variations are possible and are within the scope of the appended claims. For example, it assumed above that the switching cycle 104 has a fixed duration, and the duration of the on time interval 106 is modulated to regulate the VDD output voltage. However, in other embodiments of the invention, other parameters may be varied. For example, in other embodiments of the invention, the PWM controller 84 may modulate the duration of the switching interval 104 and/or modulate the off time interval 108 for purposes of regulating the VDD output voltage. Additionally, although a Buck regulator topology is depicted in
As yet another example of an additional embodiment of the invention, the NMOSFET 64 (and the associated control circuitry that generates the PWM# signal) may be replaced by a diode (a Schottky diode, for example). In this regard, the cathode of the diode may be coupled to the switching node 60, and the anode of the diode may be coupled to ground. As another example, the NMOSFET 54 may be replaced by PMOSFET. Thus, many variations are possible and are within the scope of the appended claims.
In general, if edges (i.e., falling or rising edges) in the PWM and PWM# signals doe not occur in the vicinity of a sampling time, the noise management circuit 88 passes the PWM and PWM# signals through without timing adjustments to generate the PWM_MSKD and PWM_MSKD# signals, respectively. However, if edges of the PWM and PWM# signals occur in the vicinity of a scheduled sampling time, then the noise management circuit 88 delays these edges; and thus, for these cases, the PWM_MSKD and PWM_MSKD# signals are delayed versions of the PWM and PWM# signals, respectively.
To further illustrate operation of the noise management circuit 88,
The PWM_MSKD signal contains pulses 140 (such as exemplary pulses 140 a, 140 b, 140 c and 140 d) that generally correspond to the pulses 100 of the PWM (see
The selective delaying of the PWM signal is depicted by way of a more specific example by the pulse 100 b of the PWM signal (
Continuing the example, a falling edge 103 of the PWM pulse 100 b coincides with a pulse 110 b of the FS clock signal. Thus, if the falling edge 103 were not in the vicinity of a sampling time, the pulse 140 b would have a falling edge 154 as depicted in
In operation, the noise management circuit 88 responds to the MASK signal (
The noise management circuit 88 does not necessarily delay the falling and/or rising edge of each pulse 140 if the edge does not coincide with a sampling time. Thus, two pulses 140 a and 140 c of the PWM_MSKD signal are depicted as not being delayed (as compared to the corresponding PWM pulses 100 a and 100 c, respectively, of the PWM signal (
In some embodiments of the invention, the circuit 200 includes a D-type flip-flop 202 that has a clock input terminal that receives the PWM signal. A reset terminal of the flip-flop 202 receives the MASK signal, and the signal input terminal of the flip-flop 202 is connected to a logic one level. Due to this arrangement, the inverting output terminal of the flip-flop 202 has a logic one state when the MASK signal has a logic zero state (i.e., the inverting terminal has a logic one state in the absence of a pulse 120 (
Also depicted in
In some embodiments of the invention, the circuit 240 includes a D-type flip-flop 242. The clock input terminal of the flip-flop 242 receives the PWM# signal, the signal input at the flip-flop 242 receives a logic one signal, and a reset terminal of the flip-flop 242 receives the MASK signal. Thus, the flip-flop 242 is clocked on the falling edges of the PWM signal. The non-inverting output terminal of the flip-flop 242 provides a signal indicative of the falling edges of the pulse 140. Thus, in the absence of the MASK signal pulse 120, the non-inverting output terminal of the flip-flop 242 is de-asserted, and the signal on the output terminal of the AND gate 210 passes on through to be the PWM_MSKD signal. However, upon occurrence of the MASK signal pulse 120 and if the falling edge of PWM (rising edge of PWM#) is coincide with duration of pulse 120, the de-assertion of the pulse 140 is delayed.
As depicted in
The radio 322 is part of a transceiver 320 that may, for example, serve as a cellular telephone transceiver, in some embodiments of the invention. In addition to the radio 322, the regulator 10 may supply power to other components of the transceiver 320, such as an analog-to-digital converter (ADC) 340, a digital-to-analog converter (DAC) 352, baseband circuitry 356, a microcontroller unit (MCU) 358, a keypad scanner 376, a display driver 362, an antenna switch 346, a low noise amplifier (LNA) 344 and a power amplifier (350).
The ADC 340 is one example of a sampled subsystem that may provide the MASK signal (at a terminal 324) to the regulator 10. The transceiver 320 may include other components (such as a switched capacitor filter, a mixer, etc.) that provide MASK signals for purposes of controlling switching operations of the regulator 10 for improved noise performance.
In general, the radio 322 may include a radio frequency (RF) receiver circuit 326 that receives an RF signal from a low noise amplifier (LNA) 344. The RF receiver circuit 326 may translate the RF signal to an intermediate frequency (IF) signal that is provided to an IF receiver circuit 328. In accordance with some embodiments of the invention, the IF receiver circuit 328 may provide a baseband signal that is converted into digital form by the ADC 340. As depicted in
The radio 322 may also include, for purposes of transmitting, an IF transmitter circuit 322 that receives an analog signal from a digital-to-analog converter (DAC) 352. The IF transmitter circuit 322 translates the analog signal, at a baseband frequency, into an RF signal that is processed by an RF transmitter circuit 330. The output signal from the RF transmitter circuit 330 may be provided to, for example, a power amplifier 350.
Among the other features of the wireless system 300, as depicted in
In some embodiments of the invention, the transceiver 320 may be formed on a single die in a single semiconductor package. However, in other embodiments of the invention, the transceiver 320 may be formed on multiple dies in a single semiconductor package. In yet other embodiments of the invention, the transceiver 320 may be formed in multiple semiconductor packages. Thus, many variations are possible and are within the scope of the appended claims.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
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|Cooperative Classification||H02M1/44, G06F1/26|
|European Classification||G06F1/26, H02M1/44|
|Sep 30, 2005||AS||Assignment|
Owner name: SILICON LABORATORIES INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:XI, XIAOYU;SOMAYAJULA, SHYAM S.;REEL/FRAME:017062/0246
Effective date: 20050930
|Mar 27, 2007||AS||Assignment|
Owner name: NXP, B.V., NETHERLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SILICON LABORATORIES, INC.;REEL/FRAME:019069/0526
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|Oct 25, 2012||FPAY||Fee payment|
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|Apr 24, 2014||AS||Assignment|
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