|Publication number||US7550317 B2|
|Application number||US 11/601,808|
|Publication date||Jun 23, 2009|
|Filing date||Nov 20, 2006|
|Priority date||Feb 13, 2002|
|Also published as||DE10301432A1, DE10301432B4, US7141885, US20030153171, US20070085219|
|Publication number||11601808, 601808, US 7550317 B2, US 7550317B2, US-B2-7550317, US7550317 B2, US7550317B2|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (2), Referenced by (4), Classifications (26), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a divisional application based on pending application Ser. No. 10/073,173, filed Feb. 13, 2002, now U.S. Pat. No. 7,141,885 the entire contents of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to the field of semiconductor manufacturing and, more particularly, to a Wafer Level Package (WLP) with improved interconnection reliability and a method for manufacturing the same.
2. Description of the Related Art
In order to meet packaging requirements for newer generations of electronic products, efforts have been expended to create reliable, cost-effective, small, and high-performance packages. Such requirements are, for example, reductions in electrical signal propagation delays, reductions in overall component area, and broader latitude in input/output (I/O) connection pad placement.
To meet these requirements, a WLP has been developed, wherein an array of external I/O terminals is distributed over the semiconductor surface, rather than just located at one or more chip edges as in a conventional peripheral-leaded package. Typically, an array of solder balls provide the connection means between electrical signals of corresponding external connection pads and the WLP I/O terminals. Such distribution of terminal locations reduces the need for embedding signal lines that connect electrical circuit blocks of an integrated circuit (IC) to edge-located I/O terminal connection pads. Elimination of such signal lines improves the electrical performance of the device, since such lines typically have an associated high capacitance. Further, the area occupied by the IC with interconnections when mounted on a printed circuit board or other substrate is merely the size of the chip, rather than the size of a packaging leadframe. Thus, the size of the WLP may be made very small.
As can be, readily seen, as one or the other opposing sides of the solder connection move, such as during the aforementioned thermal expansion and contraction, a torquing can be seen on solder ball 40 and joint 30. Typically, with repeated expansion and contraction at temperatures that are below the melting point of the solder, rigid joint 30 can be stressed sufficiently to cause separation or cracking from pad 20 as indicated by the area labeled 32 in
Thus, there is a demonstrated need for a WLP having improved interconnection reliability, especially between the chip and the PCB, and a method of manufacturing the same.
A feature of the present invention is to provide a semiconductor device package product, such as a Wafer Level Package (WLP), having excellent reliability and reduced production cost.
According to a preferred embodiment of the present invention, each one of a distributed plurality of electrical connection pads feature an underlying air pad, with the connective air pads preferably being manufactured using a conventional fabrication process and screen-printing technology. Construction of the air pad consists of etching an irregularly-shaped cavity in a substrate, depositing an interim support layer made from a soluble material into that cavity, depositing a metal connection pad on that interim support layer, such that at least portions of the metal connection pad extends beyond the irregularly-shaped cavity and overlays a portion of the adjacent substrate, then dissolving the support layer to create an air cushion beneath the metal connection pad, with the metal connection pad being supported by the aforementioned overlayed substrate portions.
The air pad features at least two supporting structures, at least one of which includes a metal conductor for making electrical connection to the metal connection pad. Around the periphery of the metal connection pad is sufficient space for 1) removal of the interim soluble support material needed in the deposition/formation of the metal connection pads, and 2) general freedom of thermal and vibrational movement without making contact with the substrate.
In a preferred embodiment according to the present invention, a structure for providing resilient interconnections in a wafer level package comprises a conductive pad that overlays an air space, wherein at least a portion of the air space extends laterally beyond the conductive pad, and wherein the conductive pad overlays, and is in contact with, a plurality of perimeter interconnect support structures. Further, at least one of the plurality of perimeter interconnect support structures also supports, or is integral with, a conductive metal wire that electrically connects the conductive pad to other on-chip electrical circuitry.
A preferred shape of such conductive pads is generally rectangular, with a longitudinal axis that is preferably oriented along an axis comprising a radial from a center of mass of the WLP. In an alternate embodiment of the present invention, the conductive line may be supported by at least one perimeter interconnect support structure that is positioned relative to a center of the conductive pad less than or equal to about 60 degrees of the major axis.
According to the present invention, a method for manufacturing a structure for providing resilient interconnections in a wafer level package preferably comprises the steps of: forming a cavity having a first area in a semiconductor substrate; filling the cavity with a removable material; forming a conductive layer over the removable material; patterning the conductive layer to form a conductive pad; removing the removable material to form an air space below the conductive pad; and forming an interconnection material on the conductive pad, whereby at least a portion of the air space extends laterally beyond the conductive pad. The removable material is preferably planarized before forming the conductive layer, and such planarization may use an etch-back process or a CMP process. The removable material may be selected from the group consisting of a monomeric material, a polymeric material, and an elastomeric material, such as a B-stage-able material, for example.
The cavity is formed by depositing a dielectric layer and by patterning the dielectric layer using a photolithographic process. Additionally, after forming the conductive layer, a second dielectric layer may be deposited over the conductive layer. The method preferably also includes the additional step of, after forming the air space, depositing a protective, non-corrosive metal layer on a top and a bottom surface of the conductive pad using an electroless plating method, wherein the metal is selected from the group consisting of gold and nickel.
Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduced, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a finished soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and/or solder ball and the interconnection pad.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
According to the present invention, a resilient air pad connection structure in an integrated circuit (IC) in a Wafer Level Package (WLP) provides a low dielectric capacitance separating an input/output (I/O) metal connection pad and an underlying substrate having electrical circuitry. Conventional non-resilient air pad connection structures are typically encapsulated and supported at all edges by adjacent layers. Such structures are used solely to lower the capacitance of a node by replacing an organic or silicon based dielectric material between the electrical plates of the capacitance (i.e. the connection pad and the substrate) with air, which has a lower dielectric constant. The air pad structure of the present invention, however, provides a minimum number of support points/electrical contacts at the periphery of the connection pad to allow the connection pad a maximum amount of vertical and lateral thermal and/or mechanical movement, while still providing the lower capacitance that the air medium provides. This minimum set of contacts provides resiliency in the connection joint that can reduce destructive mechanical stresses on a solder connection.
Such an air pad may be manufactured using the steps of: 1) creating in an IC substrate a cavity that has an irregular shape with a few peripheral pad supports and that is larger than a desired connection pad; 2) filling the cavity with a soluble base material, 3) after curing the soluble base material, depositing a metal pad layer on the soluble base layer and overlaying the peripheral pad supports, and 4) dissolving and removing the soluble base layer, leaving an air gap under the metal pad layer which is supported by, and in electrical contact with, the peripheral pad supports.
On first dielectric layer 60 are formed wiring land patterns 55 preferably consisting of a metal, such as silver (Ag) or copper (Cu). Such wiring patterns 55 having a predetermined thickness and width may be formed using conventional sputtering, evaporation, electroplating, electroless-plating methods, or combination of these methods. The thickness of the wiring is preferably thicker than that of the metal layer of a conventional fabrication process, i.e., approximately 15 μm to approximately 50 μm.
Overlaying the wiring land patterns, a second dielectric layer 63 is preferably formed of a polyimide material with a thickness of about 2 μm to about 50 μm. Second dielectric layer 63 provides lateral mechanical protection for a solder ball 80, thereby protecting solder ball 80 from joint failure and reducing potential mechanical damage to the chip rather than improving the electrical properties. Material of the second dielectric layer is preferably selected for superior mechanical and chemical properties that protect the chip from the external environment stresses.
In aligned cavities in second dielectric layer 63, connection pad regions are formed and exposed using a lithographic process. The exposed pad regions are electroplated or electroless-plated with a metal such as nickel (Ni), copper (Cu), gold (Au), thereby forming metal connection pads 62. Solder balls 80 are placed on the metal connection pads 62.
As shown in
As shown in
Although the present invention preferably uses B-stage-able polymer as the decomposed material under the connection pad, other material such as polysiloxane, etc. may be substituted for the B-stage-able polymer.
The present invention provides a WLP with an air pad structure, on which patterned (open) air gaps are formed under solder ball connection pads 62, thereby improving the reliability and the electrical properties of the WLPs.
A preferred embodiment of the present invention has been disclosed herein and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.
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|1||Kohl, Paul A., et al, "Air-Gaps for Electrical Interconnections" Electrochemical and Solid-State Letters, 1(1):49-51 (1998) Copyright, The Electrochemical Society, Inc.|
|2||Kohl, Paul A., et al., "Wafer-Level Packaging Addresses Chip-to-Module Interconnections", Semiconductor International, Cahners Business Information, Reed Elsevier, Inc. (Apr. 2001) [5 pages].|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8420950||Apr 16, 2013||Stats Chippac Ltd.||Circuit system with leads and method of manufacture thereof|
|US8815650||Sep 23, 2011||Aug 26, 2014||Stats Chippac Ltd.||Integrated circuit packaging system with formed under-fill and method of manufacture thereof|
|US9093364||Jun 22, 2011||Jul 28, 2015||Stats Chippac Ltd.||Integrated circuit packaging system with exposed vertical interconnects and method of manufacture thereof|
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|U.S. Classification||438/117, 438/619|
|International Classification||H01L21/44, H01L21/56, H01L23/485, H01L23/28, H01L21/60, H01L23/50|
|Cooperative Classification||H01L2924/01082, H01L2924/14, H01L2924/01047, H01L2224/13099, H01L2924/014, H01L24/10, H01L2924/01033, H01L2924/30105, H01L2924/01005, H01L2924/01029, H01L2924/01068, H01L2924/01078, H01L2924/01004, H01L2924/01019, H01L2924/01079, H01L2924/01006, H01L24/13|